National Instruments NI PXIe-1082 User manual

INSTALLATION GUIDE
8-Slot NI PXIe-1082 Backplane
This guide describes installation requirements for the 8-slot NI PXIe-1082
backplane.
Contents
NI PXIe-1082 Backplane Overview ....................................................... 2
Interoperability with CompactPCI................................................... 3
System Controller Slot..................................................................... 3
Hybrid Peripheral Slots.................................................................... 4
PXI Express Peripheral Slots........................................................... 4
System Timing Slot ......................................................................... 4
PXI Local Bus.................................................................................. 6
PXI Trigger Bus............................................................................... 6
System Reference Clock.................................................................. 7
PXIe_SYNC_CTRL ........................................................................ 9
Mechanical Requirements....................................................................... 10
Mounting.......................................................................................... 10
Dimensions ...................................................................................... 11
Cooling............................................................................................. 11
Handling.................................................................................................. 12
Electrical Requirements .......................................................................... 13
PXI Connectors................................................................................ 13
Power ............................................................................................... 14
Connector J37 ........................................................................... 14
Connector J36 ........................................................................... 16
Connector J35 ........................................................................... 16
Connectors J2, J3, and J4.......................................................... 17
Backplane Specifications................................................................. 17
System Synchronization Clock (PXI_CLK10, PXIe_CLK100,
PXIe_SYNC100) Specifications................................................... 18
10 MHz System Reference Clock: PXI_CLK10...................... 18
100 MHz System Reference Clock: PXIe_CLK100 and
PXIe_SYNC100 .................................................................... 18
External Clock Source .............................................................. 19

8-Slot NI PXIe-1082 Backplane Installation Guide 2 ni.com
PXIe_SYNC_CTRL..................................................................19
PXI Differential Star Triggers (PXIe-DSTARA,
PXIe-DSTARB, PXIe-DSTARC) ..........................................19
Pinouts .....................................................................................................20
System Controller Slot Pinouts ........................................................21
System Timing Slot Pinouts .............................................................22
Hybrid Slot Pinouts ..........................................................................23
NI PXIe-1082 Backplane Overview
This section provides an overview of the backplane features for the
NI PXIe-1082 chassis. Figure 1 shows the backplane.
Figure 1. 8-Slot NI PXIe-1082 Backplane

©National Instruments 3 8-Slot NI PXIe-1082 Backplane Installation Guide
Interoperability with CompactPCI
With the NI PXIe-1082, you can use the following devices in a single
PXI Express system:
• PXI Express-compatible products
• CompactPCI Express-compatible 4-Link system controller products
• CompactPCI Express-compatible Type-2 peripheral products
• Hybrid-compatible PXI peripheral products
• Standard CompactPCI peripheral products
Figure 2. NI PXIe-1082 Backplane Architecture
System Controller Slot
The system controller slot is Slot 1 of the chassis and is a 4-Link
configuration system slot as defined by the CompactPCI Express and
PXI Express specifications. It has three system controller expansion slots
for system controller modules that are wider than one slot. These slots
allow the system controller to expand to the left to prevent the system
controller from using peripheral slots.
The backplane routes the first x4 PCI Express link from the system slot
directly to slot 2. The other three x4 PCI Express links each are routed
from the system slot to a PCI Express switch. The three PCI Express
switches have x4 PCI Express links routed to each remaining peripheral
Link #2
HHHH
12 3 4 5 6 7 8
PCIe/PCI
Bridge
PLX
PEX8612
PCIe Switch
0
1
5
x4
x4
x4
Link #3
Link #4
Link #1
PLX
PEX8612
PCIe Switch
0
5
1
x4
x4
PLX
PEX8616
PCIe Switch
0
6
1
x4
x4
5
x4 x4 x4

8-Slot NI PXIe-1082 Backplane Installation Guide 4 ni.com
slot. One PCI Express switch also has a x1 PCI Express link routed to a
PCI Express-to-PCI bridge that provides a 32-bit, 33 MHz PCI bus to the
four hybrid slots. Refer to Figure 2 for the connectivity of PCI Express
and PCI.
By default, the system controller controls the power supply with the
PS_ON# signals. A logic low on this line turns on the power supply.
Hybrid Peripheral Slots
The backplane includes four hybrid peripheral slots as defined by the PXI-5
PXI Express Hardware Specification: slots 5 to 8. A hybrid peripheral slot
can accept the following peripheral modules:
• A PXI Express peripheral with a x4 or x1 PCI Express link to the
system slot or through a switch to the system slot.
• A CompactPCI Express Type-2 peripheral with a x4 or x1 PCI Express
link to the system slot or through a switch to the system slot.
• A hybrid-compatible PXI peripheral module modified by replacing the
J2 connector with an XJ4 connector installed in the upper eight rows
of J2. Refer to the PXI Express Specification for details. The PXI
peripheral communicates through the backplane 32-bit PCI bus.
• A CompactPCI 32-bit peripheral on the backplane 32-bit PCI bus.
The hybrid peripheral slots provide full PXI Express functionality and
32-bit PXI functionality except for PXI Local Bus. The hybrid peripheral
slot connects only to PXI Local Bus 6 left and right.
PXI Express Peripheral Slots
There are two PXI Express peripheral slots: slots 2 and 3. PXI Express
peripheral slots can accept the following modules:
• A PXI Express peripheral with a x4 or x1 PCI Express link to the
system slot or through a switch to the system slot.
• A CompactPCI Express Type-2 peripheral with a x4 or x1 PCI Express
link to the system slot or through a switch to the system slot.
System Timing Slot
The system timing slot is slot 4. The system timing slot accepts the
following peripheral modules:
• A PXI Express system timing module with a x4 or x1 PCI Express link
to the system slot through a PCI Express switch.
• A PXI Express peripheral with a x4 or x1 PCI Express link to the
system slot through a PCI Express switch.
• A CompactPCI Express Type-2 peripheral with a x4 or x1 PCI Express
link to the system slot through a PCI Express switch.

©National Instruments 5 8-Slot NI PXIe-1082 Backplane Installation Guide
The system timing slot has three dedicated differential pairs
(PXIe_DSTAR) connected from the TP2 connector to the XP3 connector
for each PXI Express peripheral or hybrid peripheral slot, as well as routed
back to the XP3 connector of the system timing slot, as shown in Figure 3.
You can use the PXIe_DSTAR pairs for high-speed triggering,
synchronization, and clocking. Refer to the PXI Express Specification
for details.
The system timing slot also has a single-ended (PXI Star) trigger connected
to every slot. Refer to Figure 3 for details.
The system timing slot has a pin (PXI_CLK10_IN) through which a system
timing module can source a 10 MHz clock to which the backplane
phase-locks. Refer to the System Reference Clock section for details.
The system timing slot has a pin (PXIe_SYNC_CTRL) through which a
system timing module can control the PXIe_SYNC100 timing. Refer to the
PXI Express Specification and the PXIe_SYNC_CTRL section for details.
Figure 3. PXIe_DSTAR and PXI Star Connectivity Diagram
12 3
H
5
H
6
H
7
H
8
4
PXIe_DSTAR0
PXIe_DSTAR1PXIe_DSTAR1 PXIe_DSTAR2 PXIe_DSTAR1
PXIe_DSTAR8
PXIe_DSTAR9
PXIe_DSTAR10
PXIe_DSTAR11
PXI_STAR1
PXI_STAR0
PXI_STAR2
PXI_STAR3
PXI_STAR4
PXI_STAR5
PXI_STAR6

8-Slot NI PXIe-1082 Backplane Installation Guide 6 ni.com
PXI Local Bus
The PXI backplane local bus is a daisy-chained bus that connects each
peripheral slot with adjacent peripheral slots to the left and right.
The backplane routes PXI Local Bus 6 between adjacent PXI slots. The left
local bus 6 from slot 1 is not routed anywhere, and the right local bus signal
from slot 18 is not routed anywhere.
Local bus signals may range from high-speed TTL signals to analog signals
as high as 42 V.
Initialization software uses the configuration information specific to each
adjacent peripheral module to evaluate local bus compatibility.
PXI Trigger Bus
All slots on the same PXI bus segment share eight PXI trigger lines. You
can use these trigger lines in a variety of ways. For example, you can use
triggers to synchronize the operation of several different PXI peripheral
modules. In other applications, one module in the system timing slot can
control carefully timed sequences of operations performed on other
modules in the system. Modules can pass triggers to one another, allowing
precisely timed responses to asynchronous external events the system is
monitoring or controlling. Figure 4 shows the PXI trigger bus connectivity.
Figure 4. PXI Trigger Bus Connectivity Diagram
HHHH
12 3 4 5 6 7 8
PXI Trigger Bus

©National Instruments 7 8-Slot NI PXIe-1082 Backplane Installation Guide
System Reference Clock
The NI PXIe-1082 chassis supplies PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 to every peripheral slot with an independent driver for
each signal.
An independent buffer (having a source impedance matched to the
backplane and a skew of less than 500 ps between slots) drives PXI_CLK10
to each peripheral slot. You can use this common reference clock signal to
synchronize multiple modules in a measurement or control system.
An independent buffer drives PXIe_CLK100 to each peripheral slot. These
clocks are matched in skew to less than 100 ps. The differential pair must
be terminated on the peripheral with LVPECL termination for the buffer to
drive PXIe_CLK100 so that when there is no peripheral or a peripheral that
does not connect to PXIe_CLK100, no clock is being driven on the pair to
that slot. Refer to Figure 5 for a termination example.
Figure 5. CLK100 Termination
An independent buffer drives PXIe_SYNC100 to each peripheral slot. The
differential pair must be terminated on the peripheral with LVPECL
termination for the buffer to drive PXIe_SYNC100 so that when there is
no peripheral or a peripheral that does not connect to PXIe_SYNC100, no
SYNC100 signal is being driven on the pair to that slot. Refer to Figure 5
for a termination example.
In summary, PXI_CLK10 is driven to every slot. PXIE_CLK100 and
PXIE_SYNC100 are driven to every peripheral slot.
CLK100 +
CLK100 –
50 Ω50 Ω
47 Ω0.01 μF
+
–

8-Slot NI PXIe-1082 Backplane Installation Guide 8 ni.com
PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100 have the default timing
relationship described in Figure 6.
Figure 6. System Reference Clock Default Behavior
To synchronize the system to an external clock, you can drive PXI_CLK10
from an external source through the PXI_CLK10_IN pin on the System
Timing Slot. Refer to Table 10, XP4 Connector Pinout for the System
Timing Slot, for the pinout. When a 10 MHz clock is detected on this pin,
the backplane automatically phase-locks the PXI_CLK10, PXIe_CLK100,
and PXIe_SYNC100 signals to this external clock and distributes these
signals to the slots. Refer to the Backplane Specifications section for the
specification information for an external clock provided on the
PXI_CLK10_IN pin of the system timing slot.
You also can drive a 10 MHz clock on connector J36. Refer to Figure 11 for
the location of this connector. When a 10 MHz clock is detected on this
connector, the backplane automatically phase-locks the PXI_CLK10,
PXIe_CLK100, and PXIe_SYNC100 signals to this external clock and
distributes these signals to the slots. Refer to the Backplane Specifications
section for the specification information for an external clock provided
on J36.
If the 10 MHz clock is present on both the PXI_CLK10_IN pin of the
System Timing Slot and connector J36, the signal on the System Timing
Slot is selected. Refer to Table 1, which explains how the backplane selects
the 10 MHz clocks.
PXIe_CLK100
PXI_CLK10
PXIe_SYNC100
012345678901234567890123456789

©National Instruments 9 8-Slot NI PXIe-1082 Backplane Installation Guide
A copy of the backplane’s PXI_CLK10 is exported to connector J36. Refer
to Figure 11 for the location of this connector. An independent buffer drives
this clock. Refer to the Backplane Specifications section for the
specification information for the 10 MHz REF OUT signal on J36.
PXIe_SYNC_CTRL
PXIe_SYNC100 is by default a 10 ns pulse synchronous to PXI_CLK10.
The frequency of PXIe_SYNC100 is 10/nMHz, where nis a positive
integer. The default for nis 1, giving PXIe_SYNC100 a 100 ns period.
However, the backplane allows nto be programmed to other integers. For
example, setting n= 3 creates a PXIe_SYNC100 with a 300 ns period while
still maintaining its phase relationship to PXI_CLK10. The nvalue can be
any positive integer from 1 to 255.
The system timing slot has a control pin for PXIe_SYNC100 called
PXIe_SYNC_CTRL, for use when n > 1. Refer to Table 9, XP3 Connector
Pinout for the System Timing Slot, for the system timing slot pinout. Refer
to the Backplane Specifications section for the PXIe_SYNC_CTRL input
specifications.
By default, a high level detected by the backplane on the
PXIe_SYNC_CTRL pin causes a synchronous restart for the
PXIe_SYNC100 signal. On the next PXI_CLK10 edge, the
PXIe_SYNC100 signal restarts. This allows several chassis to have
their PXIe_SYNC100 in phase with each other. Refer to Figure 7 for
timing details with this method.
Table 1. Backplane External Clock Input Truth Table
System Timing Slot
PXI_CLK10_IN J36 10 MHz REF IN
Backplane PXI_CLK10,
PXIe_CLK100 and PXIe_SYNC100
No clock present No clock present Backplane generates its own clocks
No clock present 10 MHz clock present PXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 all phase-locked to
J36—10 MHz REF IN
10 MHz clock present No clock present PXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 all phase-locked to
System Timing Slot—PXI_CLK10_IN
10 MHz clock present 10 MHz clock present PXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 all phase-locked to
System Timing Slot—PXI_CLK10_IN

8-Slot NI PXIe-1082 Backplane Installation Guide 10 ni.com
Figure 7. PXIe_SYNC100 at 3.33 MHz Using PXIe_SYNC_CTRL as Restart
Mechanical Requirements
Mounting
Figure 8 shows the backplane dimensions. There are 22 holes available for
mounting with M2.5 hardware.
Use all mounting holes for proper backplane support.
Eight mounting holes on top of the backplane have plated annular pads on
the back of the backplane. Use these mounting holes to connect the
backplane ground to the chassis in which the backplane is mounted. If you
do not want to connect the backplane ground to the chassis, use insulated
washers at these mounting holes. Refer to Figure 11 for the mounting hole
positions.
PXI_CLK10
PXIe_SYNC_CTRL
PXIe_SYNC100
SYNC100 Divider
Restarted Here