National Instruments PXIe-5763 User manual

SPECIFICATIONS
PXIe-5763
PXI FlexRIO Digitizer
This document lists the specifications for the PXIe-5763. Specifications are subject to change
without notice. For the most recent device specifications, refer to ni.com/support.
Note Using the PXIe-5763 in a manner not described in this document might
impair the protection the PXIe-5763 provides.
Note These specifications are typical at 25 °C unless otherwise noted.
Note Specifications are valid under the following conditions unless otherwise
noted:
• The chassis fan speed is set to HIGH, the foam fan filters are removed if
present, and the empty slots contain PXI chassis slot blockers and filler panels.
For more information about cooling, refer to the Maintain Forced-Air Cooling
Note to Users at ni.com/manuals.
Contents
Definitions.................................................................................................................................2
Digital I/O................................................................................................................................. 2
Digital I/O Single-Ended Channels...................................................................................3
Digital I/O High-Speed Serial MGT.................................................................................3
Reconfigurable FPGA...............................................................................................................5
Onboard DRAM........................................................................................................................5
Analog Input............................................................................................................................. 6
General Characteristics..................................................................................................... 6
Typical Specifications....................................................................................................... 6
CLK/REF IN........................................................................................................................... 13
General Characteristics................................................................................................... 13
Driver and Application Software............................................................................................ 16
Bus Interface........................................................................................................................... 16
Maximum Power Requirements..............................................................................................17
Physical................................................................................................................................... 17
Environment............................................................................................................................17
Operating Environment...................................................................................................17
Storage Environment.......................................................................................................18
Shock and Vibration................................................................................................................18

TCLK Specifications...............................................................................................................18
Intermodule SMC Synchronization Using NI-TClk for Identical Modules................... 18
Compliance and Certifications................................................................................................19
Safety.............................................................................................................................. 19
Electromagnetic Compatibility....................................................................................... 19
CE Compliance .............................................................................................................. 20
Online Product Certification........................................................................................... 20
Environmental Management........................................................................................... 20
Definitions
Warranted specifications describe the performance of a model under stated operating
conditions and are covered by the device warranty.
The following characteristic specifications describe values that are relevant to the use of the
model under stated operating conditions, but are not covered by the model warranty.
•Typical (typ) specifications describe the performance a majority of models meet.
•Nominal (nom) specifications describe an attribute that is based on design, conformance
testing, or supplemental testing.
•Measured (meas) specifications describe the measured performance of a representative
model.
Specifications are Typical unless otherwise noted.
Digital I/O
Connector Molex™ Nano-Pitch I/O™
5.0 V Power ±5%, 50 mA maximum, nominal
Table 1. Digital I/O Signal Characteristics
Signal Type Direction
MGT Tx± <3..0>1Xilinx UltraScale GTH Output
MGT Rx± <3..0>1Xilinx UltraScale GTH Input
DIO <7..0> Single-ended Bidirectional
5.0 V DC Output
GND Ground —
1Multi-gigabit transceiver (MGT) signals are available on devices with KU040 and KU060 FPGAs
only.
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Digital I/O Single-Ended Channels
Number of channels 8
Signal type Single-ended
Voltage families 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V
Input impedance 100 kΩ, nominal
Output impedance 50 Ω, nominal
Direction control Per channel
Minimum required direction change
latency
200 ns
Maximum output toggle rate 60 MHz with 100 μA load, nominal
Table 2. DIGITAL I/O Single-Ended DC Signal Characteristics2
Voltage Family VIL VIH VOL
(100µA load)
VOH
(100µA load)
Maximum DC Drive
Strength
3.3 V 0.8 V 2.0 V 0.2 V 3.0 V 24 mA
2.5 V 0.7 V 1.6 V 0.2 V 2.2 V 18 mA
1.8 V 0.62 V 1.29 V 0.2 V 1.5 V 16 mA
1.5 V 0.51 V 1.07 V 0.2 V 1.2 V 12 mA
1.2 V 0.42 V 0.87 V 0.2 V 0.9 V 6 mA
Digital I/O High-Speed Serial MGT3
Note MGTs are available on devices with KU040 and KU060 FPGAs only.
Data rate 500 Mbps to 16.375 Gbps, nominal
Number of Tx channels 4
Number of Rx channels 4
I/O AC coupling capacitor 100 nF
2Voltage levels are guaranteed by design through the digital buffer specifications.
3For detailed FPGA and High-Speed Serial Link specifications, refer to Xilinx documentation.
PXIe-5763 Specifications | © National Instruments | 3

Figure 1. Digital I/O Connector
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
Reserved
GND
MGT Rx+ 0
MGT Rx– 0
GND
MGT Rx+ 1
MGT Rx– 1
GND
DIO 4
DIO 5
GND
MGT REF+ / DIO 0
MGT REF– / DIO 1
GND
MGT Rx+ 2
MGT Rx– 2
GND
MGT Rx+ 3
MGT Rx– 3
GND
5.0 V
5.0 V
GND
MGT Tx+ 0
MGT Tx– 0
GND
MGT Tx+ 1
MGT Tx– 1
GND
DIO 6
DIO 7
GND
DIO 2
DIO 3
GND
MGT Tx+ 2
MGT Tx– 2
GND
MGT Tx+ 3
MGT Tx– 3
GND
Reserved
MGT TX± <3..0> Channels
Minimum differential output voltage4170 mVpk-pk into 100 Ω, nominal
I/O coupling AC-coupled with 100 nF capacitor
MGT RX± <3..0> Channels
Differential input voltage range
≤ 6.6 GB/s 150 mVpk-pk to 2000 mVpk-pk, nominal
> 6.6 GB/s 150 mVpk-pk to 1250 mVpk-pk, nominal
Differential input resistance 100 Ω, nominal
I/O coupling DC-coupled, requires external capacitor
4800 mVpk-pk when transmitter output swing is set to the maximum setting.
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Reconfigurable FPGA
PXIe-5763 modules are available with multiple FPGA options. The following table lists the
FPGA specifications for the PXIe-5763 FPGA options.
Table 3. Reconfigurable FPGA Options
KU035 KU040 KU060
LUTs 203,128 242,200 331,680
DSP48 slices (25 × 18
multiplier)
1,700 1,920 2,760
Embedded Block RAM 19.0 Mb 21.1 Mb 38.0 Mb
Default timebase 80 MHz
Timebase reference sources PXI Express 100 MHz (PXIe_CLK100)
Data transfers DMA, interrupts, programmed I/O, multi-gigabit transceivers5
Number of DMA channels 60
Note Table 3 depicts the total number of FPGA resources available on the part.
The number of resources available to the user is slightly lower, as some FPGA
resources are consumed by board-interfacing IP for PCI Express, device
configuration, and various board I/O. For more information, contact NI support.
Note For FPGA designs using the majority of KU040 or KU060 FPGA resources
while running at clock rates over 150 MHz, the module may require more power
than is available. If the module attempts to draw more than allowed per its
specification, the module protects itself and reverts to a default FPGA personality.
Refer to the getting started guide for your module or contact NI support for more
information.
Onboard DRAM
Note DRAM is available on devices with KU040 and KU060 FPGAs only.
Memory size 4 GB (2 banks of 2 GB)
DRAM clock rate 1064 MHz
Physical bus width 32 bit
5KU040 and KU060 options only.
PXIe-5763 Specifications | © National Instruments | 5

LabVIEW FPGA DRAM clock rate 267 MHz
LabVIEW FPGA DRAM bus width 256 bit per bank
Maximum theoretical data rate 17 GB/s (8.5 GB/s per bank)
Analog Input
General Characteristics
Number of channels 4, single-ended, simultaneously sampled
Connector type SMA
Input impedance 50 Ω
Input coupling AC or DC6
Sample Rate
Internal Sample Clock 500 MHz
External Sample Clock 500 MHz7
Analog-to-digital converter (ADC) ADS54J69, 16-bit resolution
Typical Specifications
Full-scale input range (normal operating conditions)
AC-coupled 2.03 Vpp (10.15 dBm) at 10 MHz
DC-coupled 1.97 Vpp (9.87 dBm)
Gain accuracy
AC-coupled ±0.1 dB at 10 MHz
DC-coupled ±1% at DC
DC Offset
AC-coupled ±41 µV
DC-coupled ±225 µV
Bandwidth (-3 dB)8
AC-coupled 0.07 MHz to 225 MHz
DC-coupled DC to 225 MHz9
6Only one analog input path type is populated.
7You must provide a 1 GHz clock at the CLK/REF IN front panel connector to enable this rate.
8Normalized to 10 MHz.
9Upper -3 dB bandwidth limited by ADC decimation filter.
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Table 4. Single-Tone Spectral Performance
AC-Coupled DC-Coupled
Input Frequency Input Frequency
10.1 MHz 123.1 MHz 10.1 MHz 123.1 MHz
SNR10 (dBFS) 73.7 71.8 71.7 70.6
SINAD10 (dBFS) 73.5 71.7 70.7 70.5
SFDR (dBc) -85.6 -87.7 -77.2 -86.1
ENOB11 (bits) 11.9 11.6 11.5 11.4
Table 5. Noise Spectral Density
Module nV/rt (Hz) dBm/Hz dBFS/Hz
AC-coupled 9.5 -147.4 -157.5
DC-coupled 11.8 -145.6 -155.4
Note Noise spectral density is verified using a 50 Ω terminator connected to the
input.
10 Measured with a -1 dBFS signal and corrected to full-scale. 1 kHz resolution bandwidth.
11 Calculated from SINAD and corrected to full scale.
PXIe-5763 Specifications | © National Instruments | 7

Figure 2. AC-Coupled Single Tone Spectrum (10.1 MHz, -1 dBFS, 1 kHz RBW),
Measured
Figure 3. AC-Coupled Single Tone Spectrum (123.1 MHz, -1 dBFS, 1 kHz RBW),
Measured
8| ni.com | PXIe-5763 Specifications

Figure 4. DC-Coupled Single Tone Spectrum (10.1 MHz, -1 dBFS, 1 kHz RBW),
Measured
PXIe-5763 Specifications | © National Instruments | 9

Figure 5. DC-Coupled Single Tone Spectrum (123.1 MHz, -1 dBFS, 1 kHz RBW),
Measured
Channel-to-channel crosstalk AC-coupled, characteristic
10 MHz -87 dB
100 MHz -89 dB
225 MHz -85 dB
Channel-to-channel crosstalk DC-coupled, characteristic
1 MHz -94 dB
100 MHz -83 dB
225 MHz -78 dB
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Figure 6. AC-Coupled Frequency Response, Measured
Figure 7. AC-Coupled Frequency Response Zoomed In, Measured
PXIe-5763 Specifications | © National Instruments | 11

Figure 8. DC-Coupled Frequency Response, Measured
Figure 9. DC-Coupled Frequency Response Zoomed In, Measured
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Figure 10. Input Return Loss, Measured
CLK/REF IN
General Characteristics
Connector type SMA
Input impedance 50 Ω
Input coupling AC
Reference input voltage range 0.3 Vpp to 4 Vpp
Sample Clock input voltage range 0.3 Vpp to 4 Vpp
Absolute maximum voltage ±12 V DC, 4 Vpp AC
Duty cycle 45% to 55%
Onboard reference timebase stability ±0.5 ppm
Sample Clock jitter12
AC-coupled 135 fs RMS
DC-coupled 142 fs RMS
12 Integrated from 1 kHz to 10 MHz. Includes the effects of the converter aperture uncertainty and the
clock circuitry jitter. Excludes trigger jitter.
PXIe-5763 Specifications | © National Instruments | 13

Table 6. Clock Configuration Options
Clock Configuration External
Clock Type
External
Clock
Frequency
Description
Internal Reference
Clock13
— — The internal Sample Clock locks to
an onboard voltage-controlled
temperature compensated crystal
oscillator (VCTCXO).
Internal PXI_CLK10 — 10 MHz The internal Sample Clock locks to
the PXI 10 MHz Reference Clock,
which is provided through the
backplane.
External Reference
Clock (CLK/REF IN)
Reference
Clock
10 MHz14 The internal Sample Clock locks to
an external Reference Clock,
which is provided through the
CLK/REF IN front panel
connector.
External Sample
Clock (CLK/REF IN)
Sample Clock 1 GHz 15 An external Sample Clock can be
provided through the CLK/REF IN
front panel connector.
13 Default clock configuration.
14 The PLL Reference Clock must be accurate to ±25 ppm.
15 The ADC sample rate is 500 MS/s with a 1 GHz clock.
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Figure 11. AC-Coupled Phase Noise with 182.6 MHz Input Tone, Measured
PXIe-5763 Specifications | © National Instruments | 15

Figure 12. DC-Coupled Phase Noise with 182.6 MHz Input Tone, Measured
Driver and Application Software
This device is supported in NI LabVIEW Instrument Design Libraries for FlexRIO (instrument
design libraries). Instrument design libraries allow you to configure and control the device.
The instrument design libraries provide programming interfaces, documentation, and sample
projects for LabVIEW and LabVIEW FPGA Module.
Bus Interface
Form factor PCI Express Gen-3 x8
16 | ni.com | PXIe-5763 Specifications

Maximum Power Requirements
Note Power requirements are dependent on the contents of the LabVIEW FPGA
VI used in your application.
+3.3 V 3 A
+12 V 3 A
Maximum total power 36 W
Physical
Dimensions (not including connectors) 18.8 cm × 12.9 cm (7.4 in. × 5.1 in.)
Weight 190 g (6.7 oz)
Note Clean the hardware with a soft, nonmetallic brush. Make sure that the
hardware is completely dry and free of contaminants before returning it to service.
Environment
Maximum altitude 2,000 m (800 mbar) (at 25 °C ambient
temperature)
Pollution Degree 2
Indoor use only.
Operating Environment
Ambient temperature range 0 °C to 40 °C (Tested in accordance with
IEC 60068-2-1 and IEC 60068-2-2. Meets
MIL-PRF-28800F Class 3 low temperature
limit and MIL-PRF-28800F Class 4 high
temperature limit.)
Relative humidity range 10% to 90%, noncondensing (Tested in
accordance with IEC 60068-2-56.)
PXIe-5763 Specifications | © National Instruments | 17

Storage Environment
Ambient temperature range -40 °C to 71 °C (Tested in accordance
with IEC 60068-2-1 and IEC 60068-2-2. Meets
MIL-PRF-28800F Class 4 limits.)
Relative humidity range 5% to 95%, noncondensing (Tested in
accordance with IEC 60068-2-56.)
Shock and Vibration
Operating shock 30 g peak, half-sine, 11 ms pulse (Tested in
accordance with IEC 60068-2-27. Meets
MIL-PRF-28800F Class 2 limits.)
Random vibration
Operating 5 Hz to 500 Hz, 0.3 grms (Tested in accordance
with IEC 60068-2-64.)
Nonoperating 5 Hz to 500 Hz, 2.4 grms (Tested in accordance
with IEC 60068-2-64. Test profile exceeds the
requirements of MIL-PRF-28800F, Class 3.)
TCLK Specifications
You can use the NI TClk synchronization method and the NI-TClk driver to align the Sample
Clocks on any number of supported devices, in one or more chassis. For more information
about TClk synchronization, refer to the NI-TClk Synchronization Help within the FlexRIO
Help. For other configurations, including multichassis systems, contact NI Technical Support
at ni.com/support.
Intermodule SMC Synchronization Using NI-TClk for
Identical Modules
Synchronization specifications are valid under the following conditions:
• All modules are installed in one PXI Express chassis.
• The NI-TClk driver is used to align the Sample Clocks of each module.
18 | ni.com | PXIe-5763 Specifications

• All parameters are set to identical values for each module.
• Modules are synchronized without using an external Sample Clock.
Note Although you can use NI-TClk to synchronize non-identical SMC-based
modules, these specifications apply only to synchronizing identical modules.
Skew16
AC-coupled 130 ps, measured
DC-coupled 140 ps, measured
Skew after manual adjustment ≤10 ps, measured
Sample Clock delay/adjustment 1.5 ps
Compliance and Certifications
Safety
This product is designed to meet the requirements of the following electrical equipment safety
standards for measurement, control, and laboratory use:
• IEC 61010-1, EN 61010-1
• UL 61010-1, CSA C22.2 No. 61010-1
Note For UL and other safety certifications, refer to the product label or the Online
Product Certification section.
Electromagnetic Compatibility
This product meets the requirements of the following EMC standards for electrical equipment
for measurement, control, and laboratory use:
• EN 61326-1 (IEC 61326-1): Class A emissions; Basic immunity
• EN 55011 (CISPR 11): Group 1, Class A emissions
• EN 55022 (CISPR 22): Class A emissions
• EN 55024 (CISPR 24): Immunity
• AS/NZS CISPR 11: Group 1, Class A emissions
• AS/NZS CISPR 22: Class A emissions
• FCC 47 CFR Part 15B: Class A emissions
• ICES-001: Class A emissions
Note In the United States (per FCC 47 CFR), Class A equipment is intended for
use in commercial, light-industrial, and heavy-industrial locations. In Europe,
16 Caused by clock and analog delay differences. No manual adjustment performed. Tested with a
PXIe-1085 chassis with a 24 GB backplane with a maximum slot to slot skew of 100 ps. Measured
at 23 °C.
PXIe-5763 Specifications | © National Instruments | 19

Canada, Australia, and New Zealand (per CISPR 11), Class A equipment is intended
for use only in heavy-industrial locations.
Note Group 1 equipment (per CISPR 11) is any industrial, scientific, or medical
equipment that does not intentionally generate radio frequency energy for the
treatment of material or inspection/analysis purposes.
Note For EMC declarations, certifications, and additional information, refer to the
Online Product Certification section.
CE Compliance
This product meets the essential requirements of applicable European Directives, as follows:
• 2014/35/EU; Low-Voltage Directive (safety)
• 2014/30/EU; Electromagnetic Compatibility Directive (EMC)
Online Product Certification
Refer to the product Declaration of Conformity (DoC) for additional regulatory compliance
information. To obtain product certifications and the DoC for this product, visit ni.com/
certification, search by model number or product line, and click the appropriate link in the
Certification column.
Environmental Management
NI is committed to designing and manufacturing products in an environmentally responsible
manner. NI recognizes that eliminating certain hazardous substances from our products is
beneficial to the environment and to NI customers.
For additional environmental information, refer to the Minimize Our Environmental Impact
web page at ni.com/environment. This page contains the environmental regulations and
directives with which NI complies, as well as other environmental information not included in
this document.
Waste Electrical and Electronic Equipment (WEEE)
EU Customers At the end of the product life cycle, all NI products must be
disposed of according to local laws and regulations. For more information about
how to recycle NI products in your region, visit ni.com/environment/weee.
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质指令(RoHS)。关于 National Instruments 中国 RoHS 合规性信息，请登录
ni.com/environment/rohs_china。(For information about China RoHS
compliance, go to ni.com/environment/rohs_china.)
20 | ni.com | PXIe-5763 Specifications