National Instruments NI 5422 User manual

NI 5422 Specifications
NI PXI-5422 16-Bit 200 MS/s Arbitrary Waveform Generator
Unless otherwise noted, the following conditions were used for each
specification:
• Analog Filter enabled.
• Signals terminated with 50 Ω.
• Direct Path set to 1 Vpk-pk, Low-Gain Amplifier Path set to 2 Vpk-pk,
and High-Gain Amplifier Path set to 12 Vpk-pk.
• Sample rate set to 200 MS/s and the Sample Clock Source set to
Divide-by-N.
Typical values are representative of an average unit operating at room
temperature (20 °C ±3 °C). Specifications are subject to change without
notice. For the most recent NI 5422 specifications, visit ni.com/manuals.
To access all of the NI 5422 documentation, including the NI Signal
Generators Getting Started Guide, which contains functional descriptions
of the NI 5422 signals, navigate to Start»Programs»National
Instruments»NI-FGEN»Documentation.
Hot Surface If the NI 5422 has been in use, it may exceed safe handling temperatures and
cause burns. Allow the NI 5422 to cool before removing it from the chassis.
Contents
CH 0 ........................................................................................................ 2
Sample Clock .......................................................................................... 15
Onboard Clock ........................................................................................ 18
Phase-Locked Loop (PLL) Reference Clock .......................................... 18
CLK IN ................................................................................................... 19
PFI 0 and PFI 1 ....................................................................................... 20
DIGITAL DATA & CONTROL (DDC) ................................................ 22
Start Trigger ............................................................................................ 24
Markers ................................................................................................... 25
Arbitrary Waveform Generation Mode................................................... 27
Calibration............................................................................................... 29
Power ...................................................................................................... 30
Software .................................................................................................. 31

NI 5422 Specifications 2 ni.com
Environment ............................................................................................32
Safety, Electromagnetic Compatibility, and CE Compliance .................33
Physical....................................................................................................35
Where to Go for Support .........................................................................36
CH 0
(Channel 0 Analog Output, Front Panel Connector)
Table 1.
Specification Value Comments
Number of
Channels
1 —
Connector SMB (jack) —
Output Voltage Characteristics
Output Paths 1. The software-selectable Main Output Path setting
provides full-scale voltages from 12.00 Vpk-pk to
5.64 mVpk-pk into a 50 Ω load. NI-FGEN uses either the
Low-Gain Amplifier or the High-Gain Amplifier when
the Main Output Path is selected, depending on the Gain
attribute.
2. The software-selectable Direct Path is optimized for
IF applications and provides full-scale voltages from
1.000 Vpk-pk to 0.707 Vpk-pk.
—
DAC
Resolution
16 bits —

©National Instruments Corporation 3 NI 5422 Specifications
Amplitude and Offset
Amplitude
Range
Path Load
Amplitude (Vpk-pk)1. Amplitude
values assume
the full scale
of the DAC is
utilized. If an
amplitude
smaller than
the minimum
value is
desired, then
waveforms less
than full scale
of the DAC can
be used.
2. NI-FGEN
compensates
for user-
specified
resistive loads.
Minimum Value Maximum Value
Direct 50 Ω0.707 1.00
1 kΩ1.35 1.91
Open 1.41 2.00
Low-
Gain
Amplifier
50 Ω0.00564 2.00
1 kΩ0.0107 3.81
Open 0.0113 4.00
High-
Gain
Amplifier
50 Ω0.0338 12.0
1 kΩ0.0644 22.9
Open 0.0676 24.0
Amplitude
Resolution
3 digits
Offset Range Span of ±50% of Amplitude Range with increments
<0.0028% of Amplitude Range.
Not available on
the Direct Path.
Table 1. (Continued)
Specification Value Comments

NI 5422 Specifications 4 ni.com
Maximum Output Voltage
Maximum
Output
Vo l t a g e
Path Load Maximum Output Voltage (V) The combination
of Amplitude and
Offset is limited
by the Maximum
Output Voltage.
Direct 50 Ω±0.500
1 kΩ±0.953
Open ±1.000
Low-
Gain
Amplifier
50 Ω±1.000
1 kΩ±1.905
Open ±2.000
High-
Gain
Amplifier
50 Ω±6.000
1 kΩ±11.43
Open ±12.00
Accuracy
DC Accuracy For the Low-Gain or High-Gain Amplifier Path:
±0.2% of Amplitude ± 0.05% of Offset ± 500 µV
(within ±10 °C of self-calibration temperature)
±0.4% of Amplitude ± 0.05% of Offset ± 1 mV
(0 °C to 55 °C)
All paths are
calibrated for
amplitude and
gain errors. The
Low-Gain and
High-Gain
Amplifier Paths
also are
calibrated for
offset errors.
Calibrated for
high impedance
load.
For the Direct Path:
Gain Accuracy: ±0.2% (within ±10 °C of self-calibration
temperature)
Gain Accuracy: ±0.4% (0 °C to 55 °C)
DC Offset Error: ±30 mV (0 °C to 55 °C)
AC Amplitude
Accuracy
±1.0% of desired Amplitude ± 1 mV 50 kHz sine
wave.
Output Characteristics
Output
Impedance
50 Ωnominal or 75 Ω nominal, software-selectable. —
Output
Coupling
DC —
Table 1. (Continued)
Specification Value Comments

©National Instruments Corporation 5 NI 5422 Specifications
Output Characteristics (Continued)
Output Enable Software-selectable. When the Output Path is disabled, the
CH 0 Output is terminated to ground with a 1 W resistor
equal to the selected output impedance.
—
Maximum
Output
Overload
The CH 0 output can be connected to a 50 Ω, ±12 V
(±8 V for the Direct Path) source without sustaining any
damage. No damage occurs if the CH 0 output is shorted to
ground indefinitely.
—
Waveform
Summing
The CH 0 output supports waveform summing among
similar paths—specifically, the outputs of multiple NI 5422
signal generators can be connected directly together.
—
Frequency and Transient Response
Analog
Filter
Software-selectable 7-pole elliptical filter for image
suppression.
Available on
Low-Gain
Amplifier and
High-Gain
Amplifier Paths.
Pulse
Response
Path Values are
typical. Analog
Filter disabled.
Measured with a
1 m RG-223
cable.
Direct Low-Gain
Amplifier
High-Gain
Amplifier
Rise/Fall Time 1.0 ns 2.1 ns 4.8 ns
Aberration 16% 6% 8%
Table 1. (Continued)
Specification Value Comments

NI 5422 Specifications 6 ni.com
Figure 1. Normalized Passband Flatness, Direct Path
Figure 2. Normalized Passband Flatness, Low-Gain Amplifier Path
1 10 100
Frequency (MHz)
Flatness (dB)
0
–1
–2
–4
–3
1
Guaranteed Specification
Typical
+0.4 dB
–0.3 dB
–1.2 dB
–3.4 dB
+0.4 dB +0.4 dB +0.4 dB
–0.3 dB
1 10 100
Frequency (MHz)
Flatness (dB)
0
–1
–2
–4
–3
1
Guaranteed Specification
Typical
+0.3 dB
–0.5 dB
–3.4 dB
+0.7 dB +0.7 dB
–0.7 dB
+0.7 dB
–0.7 dB

©National Instruments Corporation 7 NI 5422 Specifications
Figure 3. Normalized Passband Flatness, High-Gain Amplifier Path
Figure 4. Pulse Response, Low-Gain Amplifier Path with a 50 ΩLoad
1 10 100
Frequency (MHz)
Flatness (dB)
0
–1
–2
–4
–3
1
Guaranteed Specification
Typical
+0.2 dB
–0.6 dB
+0.2 dB
–1.1 dB
+0.2 dB
–1.1 dB
05010 20 30 40 60 70 80 90 100
Time (ns)
Amplitude (V)
0.4
–1.6
–1.2
–0.8
–0.4
0
–2.0
2.0
1.6
1.2
0.8

NI 5422 Specifications 8 ni.com
Figure 5. Recommended Sine Wave Frequency Versus Amplitude
Table 1. (Continued)
Specification Value Comments
Suggested Maximum Frequencies for Common Functions
Function Path Disable the
Analog Filter for
square, ramp,
and triangle
functions.
Direct
Low-Gain
Amplifier
High-Gain
Amplifier
Sine 80 MHz 80 MHz 43 MHz
Square Not Recommended 50 MHz 25 MHz
Ramp Not Recommended 10 MHz 10 MHz
Triangle Not Recommended 10 MHz 10 MHz
Frequency (MHz)
Sine Amplitude (Vpp into 50 Ω)
0
2
4
6
8
10
14
12
0 20406080
43 MHz Not Recommended
Recommended Operation

©National Instruments Corporation 9 NI 5422 Specifications
Table 1. (Continued)
Specification Value Comments
Spectral Characteristics
Spurious-Free
Dynamic
Range
(SFDR) with
Harmonics
Path Amplitude
–1 dBFS.
Measured from
DC to 100 MHz.
Also called
harmonic
distortion.
SFDR with
harmonics at low
amplitudes is
limited by a
–148 dBm/Hz
noise floor. All
values are
typical and
include aliased
harmonics.
Direct
Low-Gain
Amplifier
High-Gain
Amplifier
1 MHz –70 dBc –65 dBc –66 dBc
5 MHz –70 dBc –65 dBc –58 dBc
10 MHz –70 dBc –65 dBc –52 dBc
20 MHz –63 dBc –64 dBc –49 dBc
30 MHz –57 dBc –60 dBc –43 dBc
40 MHz –48 dBc –53 dBc –39 dBc
50 MHz –48 dBc –53 dBc —
60 MHz –47 dBc –52 dBc —
70 MHz –47 dBc –52 dBc —
80 MHz –41 dBc –52 dBc —

NI 5422 Specifications 10 ni.com
Spectral Characteristics (Continued)
Spurious-Free
Dynamic
Range
(SFDR)
without
Harmonics
Path Amplitude
–1 dBFS.
Measured from
DC to 100 MHz.
SFDR without
harmonics at low
amplitudes is
limited by a
–148 dBm/Hz
noise floor.
All values are
typical and
include aliased
harmonics.
Direct
Low-Gain
Amplifier
High-Gain
Amplifier
1 MHz –85 dBFS –80 dBFS –77 dBFS
5 MHz –85 dBFS –80 dBFS –77 dBFS
10 MHz –80 dBFS –80 dBFS –77 dBFS
20 MHz –80 dBFS –80 dBFS –77 dBFS
30 MHz –73 dBFS –71 dBFS –68 dBFS
40 MHz –48 dBFS –58 dBFS –55 dBFS
50 MHz –48 dBFS –53 dBFS —
60 MHz –47 dBFS –52 dBFS —
70 MHz –47 dBFS –52 dBFS —
80 MHz –41 dBFS –52 dBFS —
Average Noise
Density
Path
Amplitude
Range Average Noise Density
Average Noise
Density at small
amplitudes is
limited by a
–168 dBm/Hz
noise floor.
Vpk-pk dBm dBm/Hz
dBFS/
Hz
Direct 1.00 4.0 19.9 –141 –145
Low Gain 0.06 –20.5 1.3 –164 –144
Low Gain 0.10 –16.0 2.2 –160 –144
Low Gain 0.40 –4.0 8.9 –148 –144
Low Gain 1.00 4.0 22.3 –140 –144
Low Gain 2.00 10.0 44.6 –134 –144
High Gain 4.00 16.0 93.8 –128 –144
High Gain 12.00 25.6 281.5 –118 –144
Table 1. (Continued)
Specification Value Comments
nV
Hz
-----------

©National Instruments Corporation 11 NI 5422 Specifications
Figure 6. 10 MHz Single-Tone Spectrum, Direct Path, 200 MS/s (Typical)
Note The noise floor in Figure 6 is limited by the measurement device. Refer to the
Average Noise Density specification.
0 102030405060708090100
Frequency (MHz)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
dBm

NI 5422 Specifications 12 ni.com
Figure 7. 10.00001 MHz Single-Tone Spectrum, Low-Gain Amplifier Path,
200 MS/s (Typical)
Note The noise floor in Figure 7 is limited by the measurement device. Refer to the
Average Noise Density specification.
0 102030405060708090100
Frequency (MHz)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
dBm

©National Instruments Corporation 13 NI 5422 Specifications
Figure 8. Total Harmonic Distortion, Direct Path
Figure 9. Total Harmonic Distortion, Low-Gain Amplifier Path
0.1 1 10 100
Frequency (MHz)
Total Harmonic Distortion (dBc)
–90
–80
–70
–60
–50
–40
–30
–67 dBc
–49 dBc
–44 dBc
Guaranteed Specification
Typical
0.1 1 10 100
Frequency (MHz)
Total Harmonic Distortion (dBc)
–90
–80
–70
–60
–50
–40
–30
–60 dBc
–45 dBc –45 dBc
Guaranteed Specification
Typical

NI 5422 Specifications 14 ni.com
Figure 10. Total Harmonic Distortion, High-Gain Amplifier Path
Figure 11. Intermodulation Distortion, 200 kHz Separation (Typical)
0.1 1 10 100
Frequency (MHz)
Total Harmonic Distortion (dBc)
–90
–80
–70
–60
–50
–40
–30
–45 dBc
Guaranteed Specification
Typical
–85
–50
–55
–60
–65
–70
–75
–80
1 10 100
Frequency (MHz)
Intermodulation Distortion (dBc)
Low-Gain
High-Gain
Direct Path

©National Instruments Corporation 15 NI 5422 Specifications
Figure 12. Direct Path, Two-Tone Spectrum (Typical)
Note The noise floor in Figure 12 is limited by the noise floor of the measurement device.
Refer to the Noise Floor specification.
Sample Clock
Table 2.
Specification Value Comments
Sources 1. Internal, Divide-by-N(N≥1)
2. Internal, DDS-based, High-Resolution
3. External, CLK IN (SMB front panel connector)
4. External, DDC CLK IN (DIGITAL DATA &
CONTROL front panel connector)
5. External, PXI Star trigger (backplane connector)
6. External, PXI_Trig<0..7> (backplane connector)
Refer to the
Onboard Clock
section for more
information
about Internal
Clock Sources.
0 102030405060708090100
Frequency (MHz)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
dBm

NI 5422 Specifications 16 ni.com
Sample Rate Range and Resolution
Sample Clock
Source Sample Rate Range Sample Rate Resolution
—
Divide-by-N5 MS/s to 200 MS/s Settable to (200 MS/s)/N
(1 ≤N≤40)
High
Resolution
5 MS/s to 100 MS/s
>100 MS/s to 200 MS/s
1.06 µHz
4.24 µHz
CLK IN 5 MS/s to 200 MS/s Resolution determined by
external clock source.
External Sample Clock duty
cycle tolerance 40% to 60%.
DDC CLK IN 5 MS/s to 200 MS/s
PXI Star
Trigger
5 MS/s to 105 MS/s
PXI_Trig<0..7> 5 MS/s to 20 MS/s
Sample Clock Delay Range and Resolution
Sample Clock
Source
Delay Adjustment
Range
Delay Adjustment
Resolution
—
Divide-by-N±1 sample clock period <5 ps
High-
Resolution
≤100 MHz
±1 sample clock period Sample Clock
Period/16,384
High-
Resolution
>100 MHz
±1 sample clock period Sample Clock
Period/4,096
External (all) 0 ns to 7.6 ns <15 ps
Table 2. (Continued)
Specification Value Comments

©National Instruments Corporation 17 NI 5422 Specifications
System Phase Noise and Jitter (10 MHz Carrier)
Sample Clock
Source
System Phase Noise
Density
(dBc/Hz) Offset System Output Jitter
(Integrated from
100 Hz to 100 kHz)
1. High-
Resolution
specifications
vary with
Sample Rate.
2. Values are
typical.
3. PXI Star
trigger
specification is
valid when the
Sample Clock
Source is
locked to
PXI_CLK10.
100 Hz 1 kHz 10 kHz
Divide-by-N–110 –122 –138 1.5 ps rms
High-
Resolution1
100 MS/s
–109 –120 –120 4.0 ps rms
High-
Resolution1
200 MS/s
–108 –120 –122 4.2 ps rms
CLK IN2–116 –130 –143 1.1 ps rms
PXI Star
Trigger2,3
–111 –128 –136 2.1 ps rms
External
Sample Clock
Input Jitter
Tolerance
Cycle-Cycle Jitter ±150 ps
Period Jitter ±1 ns
—
Sample Clock Exporting
Exported
Sample Clock
Destinations
1. PFI<0..1> (SMB front panel connectors)
2. DDC CLK OUT (DIGITAL DATA & CONTROL front
panel connector)
3. PXI_Trig<0..6> (backplane connector)
Exported Sample
Clocks can be
divided by integer
K(1 ≤K≤
4,194,304).
Exported
Sample Clock
Destinations
Maximum
Frequency Jitter (Typical) Duty Cycle
—
PFI<0..1> 200 MHz PFI 0: 6 ps rms
PFI 1: 12 ps rms
25% to 65%
DDC CLK
OUT
200 MHz 60 ps rms 35% to 65%
PXI_Trig<0..6> 20 MHz — —
Table 2. (Continued)
Specification Value Comments

NI 5422 Specifications 18 ni.com
Onboard Clock
(Internal VCXO)
Phase-Locked Loop (PLL) Reference Clock
Table 3.
Specification Valu e Comments
Clock Source Internal sample clocks can either be locked to a Reference
Clock using a phase-locked loop or be derived from the
onboard VCXO frequency reference.
—
Frequency
Accuracy
±25 ppm —
Table 4.
Specification Valu e Comments
Sources 1. PXI_CLK10 (backplane connector)
2. CLK IN (SMB front panel connector)
The PLL
Reference Clock
provides the
reference
frequency for the
phase-locked
loop.
Frequency
Accuracy
When using the PLL, the Frequency Accuracy of the
NI 5422 is solely dependent on the Frequency Accuracy
of the PLL Reference Clock Source.
—
Lock Time ≤200 ms —
Frequency
Range
5 MHz to 20 MHz in increments of 1 MHz.
Default of 10 MHz.
The PLL Reference Clock Frequency has to be accurate
to ±50 ppm.
—
Duty Cycle
Range
40% to 60% —
Exported PLL
Reference
Clock
Destinations
1. PFI<0..1> (SMB front panel connectors)
2. PXI_Trig<0..6> (backplane connector)
—

©National Instruments Corporation 19 NI 5422 Specifications
CLK IN
(Sample Clock and Reference Clock Input, Front Panel Connector)
Table 5.
Specification Valu e Comments
Connector SMB (jack) —
Direction Input —
Destinations 1. Sample Clock
2. PLL Reference Clock
—
Frequency
Range
5 MHz to 200 MHz (Sample Clock Destination)
5 MHz to 20 MHz (PLL Reference Clock destination)
—
Input Voltage
Range
Sine wave: 0.65 Vpk-pk to 2.8 Vpk-pk into 50 Ω
(0 dBm to +13 dBm)
Square wave: 0.2 Vpk-pk to 2.8 Vpk-pk into 50 Ω
—
Maximum
Input Overload
±10 V —
Input
Impedance
50 Ω—
Input Coupling AC —

NI 5422 Specifications 20 ni.com
PFI 0 and PFI 1
(Programmable Function Interface, Front Panel Connectors)
Table 6.
Specification Valu e Comments
Connectors Two SMB (jack) —
Direction Bi-directional —
Frequency
Range
DC to 200 MHz —
As an Input (Trigger)
Destinations Start Trigger —
Maximum
Input Overload
–2 V to +7 V —
VIH 2.0 V —
VIL 0.8 V —
Input
Impedance
1 kΩ—
As an Output (Event)
Sources 1. Sample Clock divided by integer K(1 ≤K≤4,194,304)
2. Sample Clock Timebase (200 MHz) divided
by integer M(4 ≤ M≤ 4,194,304)
3. PLL Reference Clock
4. Marker
5. Exported Start Trigger (Out Start Trigger)
—
Output
Impedance
50 Ω—