
Contents
AT-DIO-32F User Manual vi © National Instruments Corporation
Handshaking Circuitry ..................................................................................................3-4
Level Mode........................................................................................................3-5
Leading Edge Mode ..........................................................................................3-7
Trailing Edge Mode...........................................................................................3-9
Interrupt Control Circuitry ............................................................................................3-10
DMA Control Circuitry.................................................................................................3-10
RTSI Bus Interface........................................................................................................3-11
Chapter 4
Programming.......................................................................................................................4-1
Register Map .................................................................................................................4-1
Register Sizes ....................................................................................................4-3
Register Description..........................................................................................4-3
Register Description Format .................................................................4-3
Configuration and Status Register Group .........................................................4-4
CFG1 Register.......................................................................................4-5
CFG2 Register.......................................................................................4-8
CFG3 Register.......................................................................................4-11
CFG4 Register.......................................................................................4-14
STAT Register.......................................................................................4-16
CNTINTCLR Register ..........................................................................4-18
DMACLR1 Register..............................................................................4-19
DMACLR2 Register..............................................................................4-20
Digital I/O Port Register Group ........................................................................4-21
Port A Register ......................................................................................4-22
Port B Register ......................................................................................4-23
Port C Register ......................................................................................4-24
Port D Register ......................................................................................4-25
RTSI Bus Register Group..................................................................................4-26
RTSISHFT Register ..............................................................................4-27
RTSISTRB Register..............................................................................4-28
Counter Register Group.....................................................................................4-29
CNTR1 Register (REQ1 Generator) .....................................................4-30
CNTR2 Register (REQ2 Generator) .....................................................4-31
CNTR3 Register (Timebase Generator)................................................4-32
CNTRCMD Register.............................................................................4-33
Programming Considerations........................................................................................4-37
Initializing the AT-DIO-32F Board ..................................................................4-37
Mode 0 Programming........................................................................................4-38
Mode 1 Programming........................................................................................4-38
Leading Edge Mode ..............................................................................4-41
Trailing Edge Mode...............................................................................4-42
Data Settling Delay ...............................................................................4-43
Programmed I/O Transfers....................................................................4-43
Input Data Latch....................................................................................4-44
Interrupt Handling .................................................................................4-44
DMA Transfers......................................................................................4-48
32-Bit Transfers.....................................................................................4-48
Pattern Generation Using Onboard Counters....................................................4-49