NEC uPD72257 User manual

Preliminary User's Manual
µPD72256, µPD72257
Graphics Controllers
Hardware
Document No. S19203EE1V3UM00
Date published July 07, 2009
© NEC Electronics 2008
Printed in Germany

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2Preliminary User's Manual S19203EE1V3UM00

The quality grade of NEC Electronics products is "Standard" unless otherwise
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Preliminary User's Manual S19203EE1V3UM00 3

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4Preliminary User's Manual S19203EE1V3UM00

Preface
Readers This manual is intended for users who want to understand the functions of this
graphics controller.
Purpose This manual presents the hardware manual for this graphics controller.
Organization This system specification describes the following sections:
• Pin function
• Functions of each building block
Module instances These graphic controllers may contain several instances of a dedicated module.
In general the different instances of such modules are identified by the index "n",
where "n" counts from 0 to the number of instances minus one.
Legend Symbols and notation are used as follows:
• Weight in data notation: Left is high order column, right is low order
column
• Active low notation: xxx (pin or signal name is over-scored) or /xxx
(slash before signal name)
•Memory map address: High order at high stage and low order at low
stage
Note Additional remark or tip
Caution Item deserving extra attention
Numeric notation • Binary: xxxx or xxxBor xxxB
• Decimal: xxxx
• Hexadecimal: xxxxHor xxxxH or 0x xxxx
Prefixes representing powers of 2 (address space, memory capacity):
•K (kilo): 210 = 1024
•M (mega): 220 = 10242= 1,048,576
•G (giga): 230 = 10243= 1,073,741,824
Data units • Byte: 8 bit
• Half-word: 2 byte = 16 bit
• Word: 2 half-words = 4 byte = 32 bit
Register contents X, x = don’t care
Diagrams Block diagrams do not necessarily show the exact wiring in hardware but the
functional structure.
Timing diagrams are for functional explanation purposes only, without any
relevance to the real hardware implementation.
Terms and
abbreviations
Following terms and abbreviations are used:
• I/F: is short for "interface"
• S/W: is short for "software"
• H/W: is short for "hardware"
• bpp: "bits per pixel" is the number of bits holding the colour
information of a single pixel
Preliminary User's Manual S19203EE1V3UM00 5

•HSYNC: horizontal synchronization signal, that marks the beginning
of a new line
•VSYNC: vertical synchronization signal, that marks the beginning of
a new frame or field
• CSYNC: composite synchronization signal, which presents a
composition of the horizontal and vertical synchronization signals
HSYNC and VSYNC
• frame: denotes the unit of an entire image
•field: denotes the half-frame holding the even respectively odd lines
of a frame in interlaced video mode, thus one entire frame is made
up of two fields
Trademarks • AHB™ stands for "AMBA Advanced High-performance Bus" and is
a trademark of ARM Limited
• APB™ stands for "AMBA Advanced Peripheral Bus" and is a
trademark of ARM Limited
•AMBA®stands for "Advanced Microcontroller Bus Architecture" and
is a registered trademark of ARM Limited
Further Information For further information see http://www.eu.necel.com/
6Preliminary User's Manual S19203EE1V3UM00

Table of Contents
Chapter 1 Introduction ....................................................... 11
1.1 Block diagrams ................................................................... 12
Chapter 2 Pin Functions ..................................................... 15
2.1 Pin Lists .......................................................................... 15
2.1.1 Ravin-L pin list ............................................................ 16
2.1.2 Ravin-M pin list ........................................................... 21
2.2 Pull-up resistor pin groups ......................................................... 26
2.3 Ravin-L Pin Functions ............................................................. 30
2.3.1 Ravin-L pin to signals reference ............................................. 31
2.4 Ravin-M Pin Functions ............................................................ 36
2.4.1 Ravin-M pin multiplexing control ............................................ 36
2.4.2 Ravin-M pinout options .................................................... 38
2.4.3 Ravin-M pin to signals reference ............................................ 56
2.5 Recommended Connection of unused Pins ......................................... 67
2.6 Pin States with Respect to Reset ................................................... 82
Chapter 3 Memory and Register Map ................................... 83
3.1 Ravin-L Memory and Register Map ................................................. 83
3.2 Ravin-M Memory and Register Map ................................................ 85
Chapter 4 System Controller ............................................... 86
4.1 Functional Overview ............................................................... 87
4.2 Clock Generator .................................................................. 88
4.2.1 PLL configuration ......................................................... 89
4.2.2 Main system clock ........................................................ 90
4.2.3 Video Output clocks ....................................................... 90
4.2.4 Internal RAM clock (Ravin-L only) ........................................... 90
4.3 Resets ........................................................................... 91
4.3.1 PLL restart ............................................................... 92
4.3.2 Software and Watchdog reset .............................................. 93
4.3.3 Host CPU synchronization ................................................. 93
4.4 System Watchdog ................................................................. 94
4.5 Modules Control Functions ........................................................ 94
4.5.1 Internal RAM control (Ravin-L only) .......................................... 94
4.5.2 SDRAM control ........................................................... 94
4.5.3 Video Input control ........................................................ 95
4.5.4 Video Output control ...................................................... 97
4.6 Boot Mode Function ............................................................... 98
4.7 System Controller Registers .......................................................
100
4.7.1 System Controller registers overview ........................................100
4.7.2 System Controller registers write protection ..................................100
4.7.3 System Controller registers details ..........................................101
Chapter 5 Host CPU Interface .............................................119
5.1 Functional Overview ...............................................................
122
5.2 LBus Interface ....................................................................
123
Preliminary User's Manual S19203EE1V3UM00 7

5.2.1 LBus-I/F signals ..........................................................123
5.2.2 LBus-I/F addressing modes ................................................124
5.2.3 LBus-I/F protocol .........................................................125
5.2.4 LBus-I/F DMA request .....................................................132
5.3 ADBus Interface ..................................................................
133
5.3.1 ADBus-I/F signals .........................................................133
5.3.2 ADBus-I/F address offset function ...........................................133
5.3.3 ADBus-I/F data access ....................................................134
5.3.4 ADBus-I/F principle timing .................................................136
5.4 Address Alignment ................................................................
139
5.5 Interrupt Controller ................................................................
140
5.6 AHB Master Status and Interrupts ..................................................
142
5.7 Host-I/F Registers ................................................................
143
5.7.1 Host-I/F registers overview .................................................143
5.7.2 Host-I/F registers details ...................................................144
Chapter 6 Video Input (Ravin-M only) ...................................151
6.1 Functional Overview ...............................................................
152
6.2 Data Format and Synchronization ..................................................
154
6.2.1 ITU-R656 data input .......................................................154
6.2.2 RGB data input ...........................................................155
6.2.3 Synchronization status information ..........................................156
6.3 Video Capturing ...................................................................
156
6.3.1 Video capturing modes ....................................................156
6.3.2 Start and stop of video capturing ...........................................157
6.4 Scaling, Cropping and Storing .....................................................
158
6.4.1 Cropping .................................................................159
6.4.2 Scaling ..................................................................160
6.4.3 Storing ...................................................................164
6.5 Colour Format Conversions ........................................................
164
6.5.1 RGB(666)/(565) to RGB(888) conversion .....................................164
6.5.2 YUV(4:2:2) to YUV(4:4:4) conversion .........................................165
6.5.3 YUV(4:4:4) to RGB(888) conversion ..........................................166
6.6 YUV Adjustment ..................................................................
166
6.7 Dithering .........................................................................
167
6.8 Video Data FIFO and Framebuffer addressing .......................................
167
6.8.1 Video data FIFO ..........................................................167
6.8.2 Framebuffer addressing ....................................................168
6.9 Interrupts .........................................................................
169
6.9.1 Interrupt sources ..........................................................169
6.9.2 Interrupt control ...........................................................170
6.10 Video Input Registers .............................................................
171
6.10.1 Video Input registers overview ..............................................171
6.10.2 Video Input registers details ................................................172
Chapter 7 Video Output ......................................................188
7.1 Functional Overview ...............................................................
190
7.2 Colour Formats ...................................................................
191
7.2.1 CLUT palette .............................................................191
8Preliminary User's Manual S19203EE1V3UM00

7.2.2 Display data output formats ................................................192
7.3 Timing Signals ....................................................................
193
7.3.1 Display data clock signal ...................................................193
7.3.2 Synchronization signals ....................................................194
7.4 DMA FIFO and Framebuffer Addressing ............................................
196
7.4.1 FIFO watermark ...........................................................197
7.4.2 Framebuffer addressing ....................................................197
7.5 Interrupts .........................................................................
197
7.5.1 Interrupt sources ..........................................................198
7.5.2 Interrupt controller ........................................................199
7.6 Start and Stop of Video Output .....................................................
200
7.7 Video Output Registers ............................................................
201
7.7.1 Video Output registers overview ............................................201
7.7.2 Video Output registers details ..............................................202
Chapter 8 Drawing Engine ..................................................215
8.1 Functional Overview ...............................................................
216
8.2 Introduction ......................................................................
217
8.3 Drawing Features .................................................................
219
8.3.1 Drawing features summary .................................................219
8.3.2 Vector drawing ...........................................................220
8.3.3 BitBLT ...................................................................221
8.4 Input and Output Data Formats ....................................................
223
8.4.1 Source and destination data ................................................223
8.4.2 Texture colour formats .....................................................223
8.4.3 Framebuffer colour formats .................................................223
8.5 Rendering Pipeline ................................................................
225
8.5.1 Coordinate transformation .................................................225
8.5.2 Rasterization .............................................................225
8.5.3 Edge setup linear case .....................................................227
8.5.4 Edge setup quadratic case .................................................231
8.5.5 Band filter ................................................................234
8.5.6 Clamping unit .............................................................235
8.5.7 Combiner unit ............................................................236
8.5.8 Rasterization optimization ..................................................237
8.5.9 Colourization .............................................................240
8.5.10 Texturing .................................................................241
8.5.11 Blending .................................................................245
8.6 Rendering Modes .................................................................
247
8.6.1 Register based mode ......................................................247
8.6.2 Display list based mode ....................................................247
8.7 Interrupts .........................................................................
250
8.7.1 Interrupt sources ..........................................................250
8.7.2 Interrupt control ...........................................................250
8.8 Performance Counters ............................................................
252
8.9 Drawing Engine Registers .........................................................
253
8.9.1 Drawing Engine registers overview ..........................................253
8.9.2 Control registers details ....................................................255
8.9.3 Colour registers details ....................................................265
8.9.4 Limiter registers details ....................................................268
Preliminary User's Manual S19203EE1V3UM00 9

8.9.5 Texture registers details ....................................................272
8.9.6 Miscellaneous registers details ..............................................284
Chapter 9 External Memory Interface Controller ....................290
9.1 Functional Overview ...............................................................
293
9.2 SDRAM Interface .................................................................
294
9.2.1 SDRAM Initialization .......................................................295
9.2.2 SDRAM Refresh Control ...................................................297
9.3 Static Memory Interface ...........................................................
302
9.3.1 Static RAM timing .........................................................302
9.4 Address Decoder .................................................................
307
9.4.1 Chip select configuration ...................................................307
9.4.2 Address adjustment .......................................................311
9.5 Memory Controller Power-Down ...................................................
312
9.6 Memory Controller Registers ......................................................
314
9.6.1 Memory Controller registers overview ........................................314
9.6.2 Memory Controller registers details ..........................................315
Chapter 10 Register List .......................................................332
10 Preliminary User's Manual S19203EE1V3UM00

Chapter 1 Introduction
Ravin-L (µPD72256) and Ravin-M (µPD72257) are new members of NEC’s low-
cost graphics controller series, used to interface coloured TFT displays in
embedded applications like automotive dashboard- or audio applications.
Both products are focusing on cost optimization and flexibility. They are designed
featuring a high compatibility between each other and are future save as they can
be integrated into new SOC designs without changes.
Ravin-L and Ravin-M use the same design base and therefore both products only
differ in parts of the feature set. All common features have the same technical
realization behind.
Note Throughout this document the name Ravin-L is used for the µPD72256 and
Ravin-M for the µPD72257 device.
The graphics controllers provide following features:
Table 1-1 Ravin-L and Ravin-M features
Feature Ravin-L Ravin-M
Typical display size QVGA/HVGA VGA
External Memory Controller SDRAM, SRAM, NOR flash SDRAM, SRAM, NOR flash
External Memory I/F width 16-bit data bus 32-bit data bus
Internal RAM 160 KB –
Host CPU I/F 8-bit LBus 8-bit LBus / 16-bit ADBus
BitBLT √ √
Vector Drawing Engine √ √
Video Input I/F – √
Digital Video Output I/F one two
Virtual layering √ √
Alpha blending √ √
Anti aliasing Vector and bitmaps Vector and bitmaps
System frequency 40 MHz 80 MHz
Supply voltage Core supply 1.5 V 1.5 V
I/O supply 3.3 V 3.3 V
Package 176 pin QFP 176 pin QFP
√: available; –: not available
Preliminary User's Manual S19203EE1V3UM00 11

1.1 Block diagrams
The block diagrams below show the functional modules of Ravin-M and Ravin-L,
the bus systems and the external signals.
APB slave
APB AHB
Drawing
Engine
VO0CLK
VO0CLK
HCLK
HCLK HCLK
HCLK
HCLK
VO1CLK VO1CLK
SYSRESET
SYSRESET
SYSRESET SYSRESET
SYSRESETSYSRESET
Video
Input
VI0SYNC1
VI0CLK
VI0SYNC2
VI0R[5:0]
VI0G[5:0]
VI0B[5:0]
ITU0[7:0]
Video
Output
1
VO1HSYNC
VO1VSYNC
VO1CLK
VO1R[5:0]
VO1G[5:0]
VO1B[5:0]
Video
Output
0
VO0HSYNC
VO0VSYNC
VO0CLK
VO0EN
VO0R[5:0]
VO0G[5:0]
VO0B[5:0]
System
Controller XT1
XT2
RESET
Host-I/F
HLBD[7:0]
HADD[15:0]
LBus-I/FADBus-I/F
HADBEN[1:0]
HADA[20:0]
HLBWR
HLBRD
HLBCS
HLBDRQ
HINT
HADWAIT
HADWR
HADRD
HADCS
External Memory I/F
MD[31:0]
MA[24:0]
MCS0
MCS1
MDCKE
MDCLK
MDBA[1:0]
MDDQM[3:0]
MDFBCLK
MDA10PC
MDRAS
MDWE
MSOE
MSWR
MSBEN[3:0]
MDCAS
Common I/FSDRAM-I/F
Static
memory
I/F
APB master
AHB master
AHB master
AHB master
AHB slave
AHB slave
Slave
APB slave
AHB master
AHB slave
AHB master
APB slave
Ravin-M
Figure 1-1 Ravin-M block diagram
Chapter 1 Introduction
12 Preliminary User's Manual S19203EE1V3UM00

HCLK
APB slave
APB AHB
Drawing
Engine
VO0CLK
VO0CLK
HCLK
HCLK
HCLK
HCLK
SYSRESET
SYSRESET
SYSRESET
SYSRESET
SYSRESET
SYSRESET
Video
Output
0
VO0HSYNC
VO0VSYNC
VO0CLK
VO0EN
VO0R[5:0]
VO0G[5:0]
VO0B[5:0]
System
Controller XT1
XT2
RESET
Host-I/F
HLBD[7:0]
LBus-I/F
HLBWR
HLBRD
HLBCS
HLBDRQ
HINT
External Memory I/F
MD[15:0]
MA[24:0]
MCS0
MCS1
MDCKE
MDCLK
MDBA[1:0]
MDDQM[1:0]
MDFBCLK
MDA10PC
MDRAS
MDWE
MSOE
MSWR
MSBEN[1:0]
MDCAS
Common I/FSDRAM-I/F
Static
memory
I/F
APB master
AHB master
AHB master
AHB slave
Slave
AHB slave
AHB slave
AHB master
APB slave
Ravin-L
RAM
160 KB
Figure 1-2 Ravin-L block diagram
Busses The internal modules are linked via two bus systems:
•APB
The APB is used to give the external Host CPU access the control
registers of the System Controller, Video Input and Drawing Engine.
The Host-I/F module is the only APB master.
•AHB
The main purpose of the AHB is to transfer video and image content
data. Since the Video Input and Output modules, the Drawing Engine
as well as the Host CPU deal with video data, these modules can
access the AHB as bus masters. All video and image data is stored
in framebuffers in external memory and - with Ravin-L - in the internal
RAM. Hence the external and internal memory are connected as
slave AHB clients. The control registers of External Memory I/F
Controller are also accessible via its AHB slave I/F.
The AHB is also used to access the Video Output modules control
registers, whcih are equipped with AHB slave interfaces for that
purpose.
Introduction Chapter 1
Preliminary User's Manual S19203EE1V3UM00 13

Clocks The clock generation circuitry is part of the System Controller. It generates the
main system clock HCLK, that is supplied to most modules. It is also used to set
up and generate the pixel clocks VO0CLK and VO1CLK for the Video Output
modules.
Another important task of the System Controller is the generation of internal reset
signals.
Chapter 1 Introduction
14 Preliminary User's Manual S19203EE1V3UM00

Chapter 2 Pin Functions
This chapter describes the pin functions of Ravin-L and Ravin-M.
Ravin-M Ravin-M presents a variety of selectable pin functions to match different needs.
The various Ravin-M pinout configurations trade between
• Host-I/F width
• SDRAM and/or SRAM Memory Interface width
• availability of a second video output
• availability and data format of the video input
The pinout option is selected by the settings of the MODE[3:0] pins at release of
the external RESET. The settings of these pins are stored in the
SYSBOOTMODE.BOOTMODE[3:0] bits and determine also the pin multiplexing
default configuration, controlled by the initial value of SYSPINMUX.PINMUX[3:0].
Depending on the chosen pinout option some groups of pins are connected
internally to pull-up resistors after RESET release. Enabling and disabling of the
internal pull-up resistors for the 7 pin groups are controlled by the
SYSPINMUX.BUFPUEN[7:0] bits. Thus the initial value of
SYSPINMUX.BUFPUEN[7:0] is also determined by MODE[3:0].
Ravin-L Ravin-L does not feature different pinout options. For Ravin-L the boot mode pins
MODE[3:0] have to be set to 0011Bat release of RESET, which sets also
SYSBOOTMODE.BOOTMODE[3:0] and further SYSPINMUX.PINMUX[3:0] to the
same value. By this the only valid pinout is selected.
Depending on the boot mode pin MODE9, which enables respectively disables
the internal IRAM per default, internal pull-up resistors are connected to the pins
of the external memory I/F data bus MD[15:0] (pull-up group 4).
If both, the internal IRAM and external memory shall be used, it is recommended
to disable the internal pull-up resistors by setting SYSPINMUX.BUFPUEN4 = 0.
2.1 Pin Lists
The following tables list all pins with its pin numbers, names and constitution.
As some pins are gathered in groups with internal switchable pull-up resistors,
the pull-up group is given as well for those pins.
Since the Ravin-M offers several piout options, some pins can take on different
different functions. The Ravin-M pin name show all functions, a certain pin can
have, separated by an underscore "_".
Preliminary User's Manual S19203EE1V3UM00 15

2.1.1 Ravin-L pin list
Table 2-1 Ravin-L pin list
Pin
number Pin name Input/ Output Internal pull-up group
1 VO0G4_MODE10 I/O –
2 VO0G5_MODE11 I/O –
3 VO0B0 O –
4 VO0B1 O –
5 DVDD33 PWR n.a.
6 DGND33 PWR n.a.
7 VO0B2 O –
8 VO0B3 O –
9 VO0B4 O –
10 VO0B5 O –
11 VO0HSYNC O –
12 VO0VSYNC O –
13 VO0CLK O –
14 n.c. I/O 5
15 n.c. I/O 5
16 DVDD33 PWR n.a.
17 DGND33 PWR n.a.
18 n.c. I/O 5
19 n.c. I/O 5
20 n.c. I/O 5
21 n.c. I/O 5
22 n.c. I/O 5
23 DVDD15 PWR n.a.
24 DGND15 PWR n.a.
25 n.c. I/O BUFPUEN5
26 n.c. O –
27 MA2 O –
28 MA1 O –
29 DVDD33 PWR n.a.
30 DGND33 PWR n.a.
31 MA0 O –
32 MDA10PC O –
33 MDBA1 O –
34 MDBA0 O –
35 MCS0 O –
36 MDRAS O –
37 MDCAS O –
38 MDWE O –
39 DVDD33 PWR n.a.
Chapter 2 Pin Functions
16 Preliminary User's Manual S19203EE1V3UM00

Pin
number Pin name Input/ Output Internal pull-up group
40 DGND33 PWR n.a.
41 MDDQM0 O –
42 MD7 I/O 4
43 MD6 I/O 4
44 MD5 I/O 4
45 MD4 I/O 4
46 MD3 I/O 4
47 MD2 I/O 4
48 MD1 I/O 4
49 MD0 I/O 4
50 DVDD33 PWR n.a.
51 DGND33 PWR n.a.
52 MD15 I/O 4
53 MD14 I/O 4
54 MD13 I/O 4
55 MD12 I/O 4
56 MD11 I/O 4
57 MD10 I/O 4
58 DGND15 PWR n.a.
59 DVDD15 PWR n.a.
60 MD9 I/O 4
61 MD8 I/O 4
62 MDDQM1 O –
63 DVDD33 PWR n.a.
64 DGND33 PWR n.a.
65 MDCLK O –
66 MDFBCLK I 7
67 MDCKE O –
68 MA11 O –
69 MA9 O –
70 MA8 O –
71 MA7 O –
72 MA6 O –
73 MA5 O –
74 DGND33 PWR n.a.
75 DVDD33 PWR n.a.
76 MA4 O –
77 MA3 O –
78 n.c. O –
79 n.c. I/O 5
80 n.c. I/O 5
81 n.c. I/O 5
Pin Functions Chapter 2
Preliminary User's Manual S19203EE1V3UM00 17

Pin
number Pin name Input/ Output Internal pull-up group
82 n.c. I/O 5
83 n.c. I/O 5
84 n.c. I/O 5
85 DGND33 PWR n.a.
86 DVDD33 PWR n.a.
87 n.c. I/O 5
88 n.c. I/O 5
89 n.c. I 3
90 n.c. I 3
91 n.c. I 6
92 n.c. I 6
93 n.c. I 6
94 n.c. I 6
95 n.c. I 6
96 n.c. I 6
97 DVDD33 PWR n.a.
98 DGND33 PWR n.a.
99 n.c. I 6
100 n.c. I 6
101 DVDD33 I 7
102 n.c. O 1
103 MCS1 O –
104 MSWR O –
105 MSOE O –
106 n.c. O –
107 n.c. O –
108 DVDD15 PWR n.a.
109 DGND15 PWR n.a.
110 MSBEN1 O –
111 MSBEN0 O –
112 DGND33 PWR n.a.
113 DVDD33 PWR n.a.
114 MA16 O –
115 MA24 O –
116 MA23 O –
117 MA22 O –
118 n.c. I 0
119 n.c. I 0
120 n.c. I 0
121 n.c. I 0
122 n.c. I 0
123 n.c. I 0
Chapter 2 Pin Functions
18 Preliminary User's Manual S19203EE1V3UM00

Pin
number Pin name Input/ Output Internal pull-up group
124 n.c. I 0
125 n.c. I 0
126 n.c. I 0
127 VO0EN O 2
128 HINT O 7
129 DGND33 I –
130 DGND33 PWR n.a.
131 DVDD33 PWR n.a.
132 MA15 O 2
133 MA14 O 2
134 MA13 O 2
135 MA12 O –
136 MA10 O –
137 MA19 O 2
138 MA20 O 2
139 MA21 O 2
140 MA18 O 2
141 MA17 O 2
142 DGND33 PWR n.a.
143 DVDD33 PWR n.a.
144 HLBD7 I/O 1
145 HLBD6 I/O 1
146 HLBD5 I/O 1
147 HLBD4 I/O 1
148 HLBD3 I/O 1
149 HLBD2 I/O 1
150 HLBD1 I/O 1
151 HLBD0 I/O 1
152 HLBRD I –
153 HLBWR I –
154 HLBDRQ O 7
155 HLBCS I 7
156 n.c. I 3
157 DVDD15 PWR n.a.
158 DGND15 PWR n.a.
159 AVDD15 PWR n.a.
160 AGND PWR n.a.
161 XT1 A n.a.
162 XT2 A n.a.
163 RESET I n.a.
164 DGND33 I –
165 VO0R0_MODE0 I/O –
Pin Functions Chapter 2
Preliminary User's Manual S19203EE1V3UM00 19

Pin
number Pin name Input/ Output Internal pull-up group
166 VO0R1_MODE1 I/O –
167 VO0R2_MODE2 I/O –
168 VO0R3_MODE3 I/O –
169 VO0R4_MODE4 I/O –
170 DVDD33 PWR n.a.
171 DGND33 PWR n.a.
172 VO0R5_MODE5 I/O –
173 VO0G0_MODE6 I/O –
174 VO0G1_MODE7 I/O –
175 VO0G2_MODE8 I/O –
176 VO0G3_MODE9 I/O –
• n.c.: do not connect this pin, leave it open
• PWR: power supply pins
• n.a.: pull-up not applicable
• -: no internal pull-up
Chapter 2 Pin Functions
20 Preliminary User's Manual S19203EE1V3UM00