network DWC-HD-DMUX User manual

network-electronics.com
HD-SDI to SD-SDI
Down-converter
Rev. 2
Flashlink User Manual
DWC-HD

DWC-HD Rev. 2
Network Electronics AS
Nordre Kullerød 1
P.O. Box 1020
N-3204 Sandefjord, Norway
Phone: [phone]
Fax: [phone]
Email: [email protected]
www.network-electronics.com
Support Phone: [phone]
Revision history
Current revision of this document is the uppermost in the table below.
Rev. Repl. Date Sign Change description
2 1 2008-07-09 NBS Added Block diagram in Chapter 1.
1 0 2008-06-18 NBS Removed monitoring versions.
0 - 2008-06-12 TB First version for public release.
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DWC-HD Rev. 2
Contents
.......................................................................................................... 2Revision history
..................................................................................................................... 3Contents
1.......................................................................................... 5Product overview
.......................................................................................................51.1 Product versions
2............................................................................................... 7Specifications
3................................................................................................. 10Description
................................................................................................................103.1 Data path
......................................................................................................103.1.1 Audio data path
...........................................................................103.1.2 When down-converting HD video
......................................................................103.1.3 When frame synchronizing SD video
............................................................................................113.2 Video blocks overview
............................................................................113.3 Optical/ Electrical input selection
..............................................................................................................113.4 De-glitcher
..........................................................................................................123.5 Scaling block
................................................................................................123.6 Frame synchronizer
..................................................................................................133.6.1 Frame Sync mode
..................................................................................................143.6.2 Frame delay mode
......................................................................................................143.7 Video generator
...........................................................................................153.8 Video processing block
.......................................................................................................153.8.1 Gain and offset
..........................................................................................153.8.2 Video payload legalizer
............................................................................................153.9 EDH processing block
............................................................................................153.10 Video output selection
..............................................................................................................153.11 Video DAC
.......................................................................................................173.12 Audio overview
................................................................................................173.13 Audio de-embedder
.............................................................................................................173.14 Audio delay
.........................................................................................173.15 Audio cross point matrix
.............................................................................................173.16 Audio fallback options
......................................................................................................173.17 Audio generator
...........................................................................................183.18 Audio processing block
.....................................................................................................183.19 Audio embedder
................................................................................................183.20 Analog audio output
4.............................................................................................. 19Configuration
...............................................................................................194.1 DIP switch functions
........................................................................................204.2 FACTORY reset function
..............................................................................214.2.1 Rotary switch and push buttons
.........................................................................................................214.2.2 Slide switches
...........................................................................................................214.3 GYDA mode
.....................................................................................................214.3.1 Information page
.................................................................................................224.3.2 Configuration page
5............................................................................................... 23Connections
6................................................................................................... 24Operation
.....................................................................................246.1 Front panel LED indicators
..................................................................................................246.2 RS422 commands
...................................................................................246.2.1 FLP4.0 required commands
.............................................................................................266.2.2 Normal control blocks
..........................................................316.2.3 Commands intended for debug/lab use only
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DWC-HD Rev. 2
................ 32General environmental requirements for Network Electronics equipment
...................................................................................................... 33Product Warranty ...........................34Appendix A Materials declaration and recycling information
.............................................................................34A.1 Materials declaration
............................................................................34A.2 Recycling information
................................................................................... 35EC Declaration of Conformity
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DWC-HD Rev. 2
1 Product overview
The Flashlink DWC-HD-DMUX converts an HD-SDI input signal to an SD-SDI output signal
with user selectable aspect ratio.
Four digital outputs and a set of configurable analog video outputs are provided, all of which
can be set to output the SD signal or the re-clocked original HD signal.
For SD input the card will act as an SD frame synchronizer with an adjustable delay relative
to the sync signal. This frame synchronizer functionality is also present when down-
converting. The card is prepared to accept black & burst or a tri-level signal from the frame.
The DWC-HD-DMUX also has a de-glitcher to give error-free synchronous switching.
The audio embedded in the HD-SDI or SD-SDI stream is de-embedded and can be delayed
relative to video. Each audio channel can be swapped in an audio matrix before they are re-
embedded in the SD-SDI data output stream. For SD-SDI inputs it is possible to turn
embedding completely off and leave the SDI stream unaltered.
A selection of user parameters of the card can be controlled by switches on the board.
Complete control of all parameters is available by use of the Flashlink RS422 Control
Protocol Version 4, which is supported by the Gyda system controller from software release
2.13.
Figure 1: DWC-HD-DMUX-R block diagram
1.1 Product versions
DWC-HD HD down-converter. With 2XSDI out, SD/HD analog out, internal
audio handling, and frame synchronizer functionality.
DWC-HD-R HD down-converter. With high sensitivity 9/125µm single mode
optical input, 2XSDI out, SD/HD analog out, internal audio handling,
and frame synchronizer functionality.
DWC-HD-DMUX HD down-converter. With 2XSDI out, SD/HD analog out, internal
audio handling, analog stereo out, AES (or RS-422 data) out, and
frame synchronizer functionality.
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DWC-HD Rev. 2
DWC-HD-DMUX-R HD down-converter. With high sensitivity 9/125µm single mode
optical input, 2XSDI out, SD/HD analog out, internal audio handling,
analog stereo out, AES (or RS-422 data) out, and frame
synchronizer functionality.
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DWC-HD Rev. 2
2 Specifications
Optical SDI input
Data rate optical: 270 – 1485 Mbps
Sensitivity
- HD-SDI (1485 Mbps): Better than -22dBm
- SD-SDI (270 Mbps): Better than -22dBm
Detector overload threshold: Min. -3dBm
Detector damage threshold: >+1dBm
Optical wavelength: 1200-1620nm
Transmission circuit fiber: 9/125um Single Mode
Connector return loss: >40dB w/ SM fiber
Connector: SC/UPC
Electrical SDI input
Connectors 75 Ohm BNC
Equalization Automatic:
->300m @270Mbps w/Belden 8281, BER < 10E-12
->100m @1485Mbps w/Belden 1694A, BER < 10E-12
Input Return loss >15dB, 5MHz -1.5GHz
-SD limit:Jitter tolerance -10Hz-1kHz: >1 UI
-10kHz – 5MHz: >0.2 UI
-HD limit:
-10Hz-100kHz: >1 UI
-100kHz–10MHz: >0.2 UI
Electrical Sync input
Connector 75 Ohm BNC
Format Black & Burst, Tri-level
Input Return loss <-35dB @ < 10MHz,
30dB @ < 30MHz
Electrical SDI outputs
Number of outputs 2
Connectors 75 Ohm BNC
Output Return loss >15dB, 5MHz -1.5GHz
Output signal level 800mV +/- 10%
-SD limit: [0.4ns – 1.5ns]; <0.5ns rise/fall var.Output signal rise / -HD limit: < 270ps, <100ps rise/fall var.fall time, 20% - 80%
Amplitude overshoot <10%
-SD: <0.2 UIOutput timing jitter -HD: <1 UI
-SD: <0.15 UIOutput alignment jitter -HD: <0.15 UI
Analog Video output, NTSC/PAL
Number of outputs 1 Component RGB/ YUV or 3 CVBS
Connector 3 x 75R BNC
DC offset < 0±15mV
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White level, NTSC 100±1 IRE
Sync level, NTSC 40±1 IRE
Return loss > 35dB @ 10MHz, >40dB @ 5MHz
White level, PAL 100±1 IRE
Sync level, PAL 40±1 IRE
Diff gain <0.5%
Diff phase <1deg
AM noise < -60dB
PM noise < -60dB
S/N < -60dB
2T K-factor < 0.5%
(2T pulse distortion)
Luma non-linearity < 2%
Analog Video output, HD
Number of outputs 1 component RGB/ YPbPr
Connector 3 x 75R BNC
DC offset < 0±15mV
White level 100±1 IRE
Return loss > 30dB @ 30MHz
Analog Audio output
Number of outputs 1 stereo pair
Connectors 2 x WECO audio connectors
Impedance < 66R
Dynamic range >100dB(A)
Crosstalk < -60dB 20Hz-20kHz
THD+N -70dB
Frequency response 20Hz-20kHz +/- 0.5dB
Output level 24dBu +/- 1dB
Common mode DC 0 – 48V
immunity
Level adjustment range 0 – 24dBu with 1db step
Two tone intermodulation < -80dB
AES output
Number of outputs 1
Connectors WECO audio connector
Return loss 110R +/-20% 0.1MHz – 6.144MHz
Output jitter <0.0025UI peak
Supported standards
SD, 270 Mbps SMPTE 259M, SMPTE 272M-AC
HD, 1485 Mbps SMPTE 292M, SMPTE 274M, SMPTE 291M, SMPTE 296M,
SMPTE 299M
Analog video SMPTE 170M, SMPTE 274M, ITU-R. BT.470,
ITU-R. BT.709 Part 2
Centre of picture definition SMPTE RP187, ITU-R. BT.470
Aspect ratio preservation SMPTE RP199-1999, SMPTE RP221
Color space conversion HD: ITU-R. BT.709
SD: ITU-R. BT.601
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DWC-HD Rev. 2
See also ITU-R. BT.1361 for more information
Video switch point SMPTE RP168 (tri-level), SMPTE 170M, ITU-R. BT.470
definition and sync
AES AES3-1996
Optical SMPTE 297M, SMPTE 292M
EDH Compliant to SMPTE RP165
Video Payload SMPTE 352M-2002
Identification
Other
Power consumption 5V – 5.3W (4.9W without optical receiver)
15V – 2.55W
-15V – 0.7W
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DWC-HD Rev. 2
3 Description
3.1 Data path
The HD/SD-SDI input selected from the optical or electrical input is equalized, re-clocked and
de-serialized and transferred to a processing unit (FPGA). In the FPGA the signal is sent
through a de-glitcher that cleans up erroneous video lines, for instance due to switching.
After the de-glitcher the video is sent to the Audio de-embedders, where audio is split from
the video.
3.1.1 Audio data path
The 16 audio channels coming out of the de-embedder are bundled in pairs and sent to an
audio store buffer. After a user specified delay the audio is fetched from the audio store
buffer and sent to an Audio Cross Point. The 10 audio outputs from the Audio Cross Point
can be any pair of audio channels de-embedded from the incoming video stream, a
generated 1 kHz sine, or a generated black sound (a legal audio stream with silence only).
As part of the audio cross point, missing output pairs can be replaced with generated fallback
signals. From the cross point outputs each stereo pair enters an Audio Processing Block
where channels can be processed or rearranged within each channel pair. Finally, eight
stereo pairs are routed to the Audio Embedder and the two remaining pairs are sent to the
audio DAC and the AES out, respectively.
3.1.2 When down-converting HD video
The video is routed to a Scaling block and the resulting SD video is passed to a Frame
synchronizer block. If video is missing, an internal video generator can be switched in as a
fallback source. The video then passes through a Video processing block with an integrated
Legalizer, before entering an EDH processing block where the user can select to insert
updated EDH flags. Although audio is re-embedded before the video processing block, the
video processing and EDH processing blocks will not manipulate the audio data.
After passing the EDH block, the video stream with embedded audio is sent in parallel out of
the FPGA and into a serializer that re-clocks the data and sends the SDI to a buffered output
switch.
The buffered output switch can be viewed as 3 simple switches, each selecting between the
equalized and re-clocked output (Through mode) and the down-converted output (Processed
mode). The output of the first two switches are sent to two paired (inverting and non-
inverting) digital outputs, whereas output of the third switch is sent to the onboard video
DAC.
3.1.3 When frame synchronizing SD video
The video data path when operating as an SD frame synchronizer is conceptually the same
as when down-converting, except that the Scaling block is not needed, placing the Frame
synchronizer block directly after the de-glitcher.
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DWC-HD Rev. 2
3.2 Video blocks overview
Figure 2: Video function blocks when down-converting HD to SD
3.3 Optical/ Electrical input selection
The DWC-HD-DMUX has both an optical and an electrical input. The active input can be
chosen either by an automatic selection based on a prioritized list of inputs and a selected
rule of switching or by manual selection. When in Gyda over-ride mode (control by DIP
switches), the card will use the priorities and rule saved from the last Gyda session.
Automatic selection mode
Mode under Video in in Gyda must be set to auto. Three input choices can be made for three
priorities; optical, electrical or mute. The priority is the order in which the board will look for a
valid input.
It is also possible to set a rule for when the input should be switched to the next priority. The
rules are:
-lol (loss of lock)
-los (loss of signal)
-EDH (Errors are found in the video frame)
Hold time determines how long a signal has to be missing/unlockable/contain errors to be
considered lost, while Lock time determines how long a higher prioritized signal has to be
present/locked/error free before it again can be considered to be present and stable. This is
described in more detail in chapter 3.6.1, most mainly in the two “If video input disappears”
sections.
3.4 De-glitcher
The de-glitcher corrects timing errors within a line of video.
The de-glitcher has a buffer of 13.6 µs for HD and 50 µs for SD. When the first signal is
present, we call it the “initial phase signal”, data is taken from the centre of this buffer. If the
timing reference of the video signal changes, for instance when a new source is being
switched into the signal path, the timing errors occurring by this change will be corrected if
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DWC-HD Rev. 2
the new timing reference is within ±6.8 µs (for HD, ±25 µs for SD) of the “initial phase signal”.
This also goes for all consecutive timing references.
If a signal occurs that is more than ±6.8 µs (for HD, ±25 µs for SD) off relative to the “initial
phase signal”, the output will repeat the last frame, refill the buffer and take out data from the
centre of the buffer. This new signal is now considered the “initial phase signal”.
Hence, it produces an error free video output without frame wrapping when the video input
comes from a router with synchronous input video signals that all lies within ±6.8 µs (for HD,
±25 µs for SD) of each other.
3.5 Scaling block
The Scaling block is the heart of the down-converter. The frame rate of the HD input dictates
the video standard that the Scaling block will produce: If the input is 50Hz-based, e.g.
1080/25p, the output will be 576/50i, and if the input is 60Hz-based (with or without
pulldown), e.g. 720/59.94p or 1080/24p, the output will be 486/29.97i.
The following assumes that the aspect ratio of the incoming HD is 16:9, and that the pictures
are such that objects are shown geometrically correct on a 16:9 monitor. The user must then
set the crop and aspect ratio of the output and the illustration below shows the options
available. The figure assumes a 4:3 monitor that ignores the WideScreen Signaling bits
(WSS bits can be inserted automatically according to the selected aspect ratio, or they can
be turned off or replaced by a user selected value. See chapter 3.11 for details.) Had the
monitor in the example processed WSS bits, the full-frame picture in the lower left would’ve
been internally converted and shown letterboxed to preserve picture geometry. The cropped
edge 4:3 and letterboxed 16:9 options should normally only be used for 4:3 monitor.
Figure 3: Picture cropping and geometry options
3.6 Frame synchronizer
The frame synchronizer consists of a frame store buffer and some control logic. The frame
store buffer can store up to 8 SD frames. When the input is an HD source to be converted to
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DWC-HD Rev. 2
SD, the frame synchronizer is placed after the Scaling block. When the input is SD, the frame
synchronizer is placed directly after the De-glitcher block. The control logic sets the frame
synchronizer in different modes of operation based on the presence of a sync input.
3.6.1 Frame Sync mode
If a sync input (B&B or Tri-level) is present, the frame synchronizer will output a signal that
has a delay relative to this signal. Two parameters can be set; output phase delay and
minimum delay.
The output phase delay can be positive or negative and sets the difference between the
phase of the sync input and the video output.
The minimum delay sets the minimum delay between video output and video input. The
actual delay can be larger than the minimum delay (hence the name), because the card must
also adjust the phase relative to the sync input.
Example: The HD-SDI input signal is 12 lines delayed to a tri-level input signal. The minimum
delay is set to 1 frame, 0 lines and 0 samples. The output phase delay is set to 5 samples.
The actual delay between the input video and the output video will be 2 frames and 5
samples.
If video input disappears
Given that stable SDI input and sync input both exists: If the SDI input disappears, and Video
in and Processed video out are set to Auto, the board will hold on to the current input whilst
frame freezing for a time set by Hold time in Video in. The board will then select the next
input in the prioritized list. If that input is the internal video generator, the pattern selected in
Video generator will be output. Defaults are optical input as first priority, then electrical, and
finally fallback to Black video, with a Hold time of 3 seconds.
Note that input selection can be based on several rules, of which only Loss of signal (los) is
based on a status that can be checked for both inputs at the same time. This means that for
Los a direct jump from priority 1 to priority 3 is possible (in one Hold time period, because
priority 2 can be checked at the same time as priority 1), while the other rules require one
Hold time period for each jump between priority levels. It the board only has one physical
input in use, it is therefore recommended to set Video generator as the second priority.
If the SDI signal disappears and mode is set to manual in one or both of Video in and
processed video out, the effect will be that the board can frame freeze but will never switch to
another video input, including the fallback generator.
If video input reappears
Given stable sync input, the video will reappear after a user specified time of locked video.
This Lock time (in Video in) defaults to 3 seconds.
If sync input disappears
Given that stable SDI input and sync input exists: If the sync signal disappears, the board will
act as in frame delay mode, see Chapter 3.6.2.
NOTE: This will result in a frame roll as the delay changes.
If sync input reappears
Given that a stable SDI input exists: If the sync signal reappears the delay mode will change
back to Frame Sync mode. Hence the internal clock will be locked to the sync signal and the
delay will change again.
NOTE: This will result in a frame roll as the delay changes.
If both signals disappears
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DWC-HD Rev. 2
The picture will first freeze for a user specified time (Hold time in Video in), and then possibly
(See section “If video input disappears” above) go to a fallback generator. The output is now
referenced to the local clock source. However, this clock source will be kept within 1 ppm of
the last sync source.
3.6.2 Frame delay mode
In this mode a sync signal is not present. The delay set is then directly related to the
incoming video. 1 frame and 1 line delay means that the output will be 1 frame and 1 line
delayed version of the input.
If video signal disappears
The picture will first freeze for a user specified time (Hold time in Video in), and then possibly
(See section “If video input disappear” under Frame sync mode above) go to a fallback
generator. The output is now referenced to the local clock source. However, this clock source
will be kept within 1 ppm of the last video source.
If video signal reappears
The video output will reappear after a user specified time of locked video. This Lock time (in
Video in) defaults to 3 seconds. The delay will now be the same as before loosing input.
NOTE: This may cause a frame roll.
If a sync input appears
Given that a stable SDI input exists: If a sync signal appears the delay mode will change to
Frame Sync mode, see Chapter 3.6.1. Hence the internal clock will be locked to the sync
signal and the delay will once again change.
NOTE: This will result in a frame roll as the delay changes.
3.7 Video generator
The video generator can produce different simple signals: Color bar, Check field and flat
field.
The flat field option allows the user to specify any combination of luma and chroma values, or
to select a predefined color from the following list:
-Black
-White
-Yellow
-Cyan
-Green
-Magenta
-Red
-Blue
In normal operation (as a fallback generator), the video generator will take its video standard
setting from the last lockable video input seen by the board. To enable the board to act as a
standalone and user configurable video generator, the video generator must be either set as
the first priority input when Mode is auto, or selected manually by setting Mode to Video
generator. Both settings are done in Processed video out. This will override any video input
but the generator signal will still be locked to the sync or SDI inputs, if present. For true
standalone generator operation, the inputs should be removed. Available video standards
are 486/25i and 576/25i.
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DWC-HD Rev. 2
3.8 Video processing block
The video processing block consists of a gain and offset adjustment, and a video payload
legalizer.
3.8.1 Gain and offset
The gain and offset adjustment is done separately on the Y, Cb and Cr samples.
Range Gyda Resolution
Luma gain 0 – 32767 (0-4x) 15bit
Chroma gain 0 – 32767 (0-4x) 15bit
Luma offset (gain = 1) -4095 – 4095 13bit
Chroma offset (gain = 1) -2047 – 2047 12bit
3.8.2 Video payload legalizer
The legalizer hard clips the upper and lower limit of the video payload. With the legalizer
enabled the limits are:
Upper limit Luma: 3ACh
Chroma: 3C0h
Lower limit Luma: 040h
Chroma: 040h
With the legalizer disabled, the video processing block hard clips both luma and chroma to
3FBh and 004h.
3.9 EDH processing block
If enabled, the EDH processing block extracts the EDH package from the video, updates the
EDH flags according to SMPTE RP165 and inserts the EDH package into the ancillary data
of the video.
If disabled, The EDH processing block only reads, process and report the EDH package
without changing it in video stream.
3.10 Video output selection
The board has four digital outputs and group of three analog outputs. The four digital outputs
are organized as two pairs, each consisting of an inverting and a non-inverting output. Each
pair and the analog group can take their signal directly from the re-clocker or from the output
of the processing unit. In Gyda the direct paths are labeled Through and the processing
paths are labeled Processed.
3.11 Video DAC
The video DAC has three configurable outputs, with the following combinations available:
-CVBS/CVBS/CVBS
-CVBS/Y/C
-Y/Pb/Pr
-R/G/B
This setting only applies to SD video. When HD video is routed to the video DAC, the output
will always be YPbPr. For CVBS and S-Video the following modulations are available:
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DWC-HD Rev. 2
-PAL B/G
-NTSC
-PAL M
-PAL N
The board can handle 50Hz-based input signals as well as 60Hz-based with and without
pulldown, but can’t convert a 50Hz-based input to a 60Hz-based output and vice versa. The
modulation setting is therefore split in two, one to select between NTSC and PAL M output
for 60Hz-based sources, and one to select between PAL B/G and PAL N for 50Hz-based
sources.
It is also possible to turn black setup (“pedestal”) on or off. This setting only applies to NTSC.
PAL Wide Screen Signaling (WSS) is also supported, and while the HD input is always 16:9,
SD inputs can have value already embedded. The user can select to strip off any existing
WSS information by setting mode to Off, or to override the current WSS value by setting
mode to On and specifying a new value, or set the mode to Auto. When input is HD, the Auto
mode will insert WSS data according to the selected aspect ratio in the scaler block. When
the input is SD, the Auto mode will signal 4:3 or 16:9 based on the aspect ratio bit in SMPTE
352M byte 3, or turn WSS off if no SMPTE 352M packages are available.
When specifying WSS values, the user should observe that the WSS value is really a 14-bit
number with other information besides just aspect ratio. Aspect ratio is contained in the lower
4 bits, and the table below covers only those bits.
WSS value Aspect ratio Picture placement Active lines
0+8=8 4:3 Full 576
1+0=1 14:9 Letterbox centre 504
2+0=2 14:9 Letterbox top 504
3+8=11 16:9 Letterbox centre 430
4+0=4 16:9 Letterbox top 430
5+8=13 >16:9 Letterbox deeper than 16:9 undefined
6+8=14 14:9 Full-height 4:3, framed to be “14:9-safe” 576
7+0=7 16:9 Full-height 16:9 (anamorphic) 576
Note the occasional “+8” in the first column above. It stems from the fourth aspect ratio bit, a
parity bit over the first three.
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DWC-HD Rev. 2
3.12 Audio overview
Figure 4: Audio function block
3.13 Audio de-embedder
The Audio de-embedder extracts all audio embedded in the video stream. The de-embedder
is always enabled when the input is HD. When the input is SD and the board operates as an
SD frame synchronizer, embedding can be globally disabled. The effect is to leave the SDI
stream unaltered, except for repeated or removed video frames.
3.14 Audio delay
An audio delay can be specified relative to the video output. It is situated before the audio
cross point matrix and is common for all de-embedded channels. The audio delay is
specified in terms of 48 kHz audio samples, and can be set to positive or negative values.
NOTE: As the audio delay is relative to the video output it is possible to specify an audio
delay that will actually be a negative delay, i.e. ask that the sound is sent from the card
before it is received. This will obviously cause audio errors.
3.15 Audio cross point matrix
The audio cross point matrix is a 10x10 cross point with inputs and outputs as shown in
Figure 4. The 8 de-embedded channels, a 1 kHz sine and “black sound” are selectable
inputs. “Black sound” is explained in chapter 3.1. The outputs of the cross points are 8 stereo
channels for re-embedding, one analog audio output and one AES output.
3.16 Audio fallback options
The 10 output channels from the cross point matrix have configurable fallbacks, used when
their corresponding matrix inputs are missing. A common fallback setting is used for all eight
re-embedder channels, whereas the audio DAC channel and AES out have their own
independent fallback settings. The priorities can be selected between matrix (being the
selected channel in the cross point matrix) or the internally generated sine or black sound.
3.17 Audio generator
The stereo audio generator is available as an input to the audio cross point matrix, and as a
fallback option. There are therefore three slightly different ways to select the generator:
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DWC-HD Rev. 2
select it in the matrix directly, select it as the first priority under audio fallback, or to set it as
second priority behind a missing input.
The generator signal is a high purity 1 kHz sine wave with a 250ms interruption on the left
channel every 3 seconds. The audio level may be set to one of two standards. The two
levels are -18 dBFS and -20 dBFS. These two levels correspond to EBU R68 and SMPTE
RP155.
3.18 Audio processing block
The output of each stereo signal from the audio cross point matrix may be manipulated in the
audio processing block (LL, RR, LR, RL ØLR, LØR, L+R/2, MS).
The stereo signals may be output in one of the following ways:
-LR, Left / Right Normal operation, no change.
-RL, Right/ Left Channels are swapped with each other.
-LL, Left/ Left Left channel is copied into the right channel.
-RR, Right/ Right Right channel is copied into the left channel.
-nLR, ØLeft/ Right The left channel is phase inverted.
-LnR, Left/ ØRight The right channel is phase inverted.
-MM, (Left + Right)/2 Both channels replaced with the mean of left and right.
-MS, MS/AB Conversion from AB stereo to MS stereo.
3.19 Audio embedder
The audio embedder can be enabled/disabled per group. When a group to be embedded is
disabled the audio inside that group is removed.
A 24-bit audio signal uses the Extended Audio Data Packet for the 4 least significant bits. Not
all equipment can handle Extended Audio Data Packets correctly, so the option exists to
truncate all audio data to 20 bits. This setting is common for all embedder channels.
The insertion of Audio Control Packages can also be switched on and off. This setting is
also common for all embedder channels.
For SD input (i.e. operation as a frame synchronizer) the audio embedder can also be
switched off all together. In this state all audio embedded on the input signal is left
unchanged.
3.20 Analog audio output
The level of the analog audio output can be adjusted in GYDA. The minimum step is 0.5dB
(input will be rounded to nearest 0.5dB) and the range is from -95.5dBu to 24dBu. It is also
possible to mute the output completely.
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DWC-HD Rev. 2
4 Configuration
4.1 DIP switch functions th
The two sets of DIP switches are labeled with a number running from 1 to 15. The 16 DIP is
labeled OVR. Note that the left DIP switch of the horizontal DIP package is number 1.The
top DIP switch of the vertical DIP package is number 9. Default settings as delivered from
factory should be all DIPs in the Off position. The module will then be under Gyda control,
see description for DIP switch 16 below.
Table 1: DIP SWITCH FUNCTIONS
Switch # Function name Function DIPs Comment
1 SDI OUT 1 Off: processed mode In through mode the
video goes through a
re-clocker only, and
the video DAC
output will also be
HD (always YPbPr).
+ On: through mode
Video DAC out
2 SDI OUT 2 Off: processed mode In through mode the
video goes through a
re-clocker only.
On: through mode
These 2 DIPs
choose aspect ratio
for down-converted
video.
3 - 4 Aspect ratio DIP[3 4] = [Off Off] => 16:9
DIP[3 4] = [Off On] => 4:3
DIP[3 4] = [On Off] => 16:9 LB
DIP[3 4] = [On On] => Previous
setting preserved “Previous setting
preserved”: With
DIPs in this position
before the module is
booted into manual
mode; the module
will keep the
previous value set by
Gyda.
These two DIPs
choose video DAC
output format for SD
output. Analog HD is
always YPbPr.
5 - 6 SD video DAC
format DIP[5 6] = [Off Off] => CVBS
DIP[5 6] = [Off On] => YPbPr
DIP[5 6] = [On Off] => SVideo
DIP[5 6] = [On On] => RGB
7 SD video DAC
modulation Off: PAL B/G + NTSC Selection between PAL B/G and NTSC
or PAL M and PAL N
is automatic, based
on video input.
On: PAL N + PAL M
8 Black setup
disable Off: Black setup for NTSC For NTSC only.
On: No black setup
9 Input priority Off: Optical input has priority This switch has no
effect for boards
without the optical
input (-R option).
On: Electrical input has priority
The 2 first of these 4
DIPS select one of
the de-embedded
groups. The next two
10 - 11 Audio DAC and
AES group DIP[10 11] = [Off Off] => Gr1
DIP[10 11] = [Off On] => Gr2
DIP[10 11] = [On Off] => Gr3
DIP[10 11] = [On On] => Gr4
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DWC-HD Rev. 2
Switch # Function name Function DIPs Comment
12 Audio DAC
channel Off: Ch1
On: Ch2
(from selected group)
13 AES channel Off: Ch1
On: Ch2
(from selected group)
14 AES/Dlink Off: AES3 out on AES output The two slide
switches on the
bottom side of the
board must also be
switched.
On: Data link out on AES output
See ch. 4.2.2below.
15 RESET Off: Use values preset by GYDA This DIP is only read
during boot. The
board will not start
when DIP 16 and
this DIP are both set
to On. After returning
the DIP to normal
position, the card
must be restarted
and kept powered for
a minimum of 10s to
complete the reset.
On: RESET to factory defaults
The reset will only
affect settings not
pertaining to DIPs
and the rotary
switch.
16 OVR Off: GYDA mode This DIP is only read
at power up.
On: Manual mode OVR is short term for
GYDA override.
4.2 FACTORY reset function
A factory reset is a 3 step process:
-Set DIP 15 to ‘on’ and boot the card.
-Remove power and set the reset switch back to normal position (‘off’)
-Power up card once again. The operation of the card will immediately reflect the freshly
loaded default settings. However, the card must be kept powered for at least 10
seconds to ensure that these settings are stored locally to be retrieved again at the
next start-up. The cards operational environment must also be kept static during those
10 seconds (i.e. no change in incoming video standard, no commands issued). Failing
to meet this requirement could result in an incomplete reset and require the user to
restart the factory reset sequence.
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