Novatek NT6862-5 Series User manual

NT6862-5xxxx
8-Bit Microcontroller for Monitor
1V2.2
Features
nOperating voltage range: 4.5V to 5.5V
nCMOS technology for low power consumption
n6502 8-bit CMOS CPU core
n8 MHz operation frequency
n32K/24K/16K bytes of ROM
n512 bytes of RAM
nOne 8-bit base timer
n13 channels of 8-bit PWM outputs with 5V open drain
n4 channel A/D converters with 6-bit resolution
n25 bi-directional I/O port pins (8 dedicated I/O pins)
nHsync/Vsync signals processor for separate &
composite signals which includes hardware sync
signals polarity detection and frequency counters with
2 sets of Hsync counting intervals
nHsync/Vsync polarity controlled output, 5 selectable
free run output signals and self-test patterns, auto-
mute function, half freq. I/O function
nAdd a jitter filter at the front end of Hsync input path,
reduce the jitter interference of Hysync input
nTwo built-in I
2C bus interfaces support VESA
DDC1/2B+
nTwo layers of interrupt management
NMI interrupt sources
- INTE0 (External INT with selectable edge trigger)
- INTMUTE (Auto Mute Activated)
IRQ interrupt sources
- INTS0/1 (SCL Go-low INT)
- INTA0/1 (Slave Address Matched INT)
- INTTX0/1 (Shift Register INT)
- INTRX0/1 (Shift Register INT)
- INTNAK0/1 (No Acknowledge)
- INTSTOP0/1 (Stop Condition Occurred INT)
- INTE1 (External INT with Selectable Edge Trigger)
- INTV (VSYNC INT)
- INTMR (Base Timer INT)
- INTADC (AD Conversion Done INT)
nHardware Watch-dog timer function
n40-pin P-DIP and 42-pin S-DIP packages
General Description
The NT6862 is a new generation monitor µC for auto-sync
and digital control applications. Particularly, this chip
supports various and efficient functions to allow users to
easily develop USB monitors. It contains the 6502 8-bit
CPU core, 512 bytes of RAM used as working RAM and
stack area, 32K bytes of OTP ROM, 13-channels of 8-bit
PWM D/A converters, 4-channel A/D converters for key
detection which save I/O pins, one 8-bit pre-loadable base
timer, internal Hsync and Vsync signals processor, a
Watch-dog timer which prevents the system from abnormal
operation, and two I2C bus interfaces. The user can store
EDID data in the 128 bytes of RAM for DDC1/2B, so that
user can reduce a dedicated EEPROM for EDID. A Half
frequency output function can save external one-shot
circuit. These designs are committed to reduce component
cost. The 42 pin S-DIP IC provides two additional I/O pins –
port40 & port41, Part number NT6862U represents the S-
DIP IC. For future reference, port40 & port42 are only
available for the 42 pin S-DIP IC.

NT6862-5xxxx
2
Pin Configurations
40-Pin P-DIP
[PGM] DAC2
DAC1/ADC3
[OE] DAC0/ADC2
[DB7] P27
[VPP] RESET
V DD
GND
OSCO
OSCI
[CE] P14/PATTERN
[A10] P12/HALFO
[A9] P11/ADC1
[A8] P10/ADC0
P20 [DB0]
P07/HSYNCO [A7]
P31/SCL0 [A13]
DAC4/SCL1 [MODE1]
DAC3 [MODE0]
HSYNCI
VSYNCI/INTV [A14]
NT6862
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P15/INTE0
[A11] P13/HALFI
P16/INTE1
17
18
19
20
24
23
22
21
DAC5/SDA1 [MODE2]
DAC6 [RESET]
CREG
P21 [DB1]
P22 [DB2]
P06/VSYNCO [A6]
P05/DAC12 [A5]
P04/DAC11 [A4]
P03/DAC10 [A3]
P02/DAC9 [A2]
P01/DAC8 [A1]
P00/DAC7 [A0]
P30/SDA0 [A12]
[DB6] P26
[DB5] P25
[DB4] P24
[DB3] P23
* [ ]: OTP Mode
42-Pin S-DIP
[PGM] DAC2
DAC1/ADC3
[OE] DAC0/ADC2
[VPP] RESET
V DD
P40
GND
OSCO
OSCI
P15/INTE0
[A11] P13/HALFI
[A9] P11/ADC1
[A8] P10/ADC0 P00/DAC7 [A0]P16/INTE1 P01/DAC8 [A1]
P02/DAC9 [A2]
P03/DAC10 [A3]
P04/DAC11 [A4]
P06/VSYNCO [A6]
P07/HSYNCO [A7]
DAC6 [RESET]
P41
DAC5/SDA1 [MODE2]
DAC4/SCL1 [MODE1]
DAC3 [MODE0]
HSYNCI
VSYNCI/INTV [A14]
CREG
NT6862U
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
[CE] P14/PATTERN
[A10] P12/HALFO
[DB7] P27
[DB6] P26
[DB5] P25
[DB4] P24
[DB3] P23
17
18
19
20
21
P05/DAC12 [A5]
P31/SCL0 [A13]
P30/SDA0 [A12]
P20 [DB0]
P21 [DB1]
P22 [DB2]
26
25
24
23
22
* [ ]: OTP Mode
Block Diagram
Timing Generator
CPU core
6502
Interrupt
Controller
H/V Sync Signals
Processor
SRAM + STACK
512 Bytes
Watch Dog Timer
PWM DACs
I/O Ports
OSCI
OSCO
VDD
GND
HSYNCI
INTE0/1
SCL0
SDA0
DAC0 - DAC7
P00 - P07
P10 - P16
P30 - P31
VSYNCO
A/D Converter ADC0 - ADC3
8-Bit Base Timer
P40 - P41
IIC BUS
P20 - P27
HSYNCO
HALFI
HALFO
DAC8 - DAC12
VSYNCI/INTV
OTP Program ROM
32K Bytes
PATTERN
SCL1
SDA1
Voltage
Regulator
CREG

NT6862-5xxxx
3
Pin Description
Pin No.
40 Pin 42 Pin Designation Reset Init. I/O Description
1 1 DAC2
[PGM ]
O
[ I ]
Open drain 5V, D/A converter output 2
[OTP ROM program control]
2 2 DAC1/ADC3 DAC1 OOpen drain 5V, D/A converter output 1, shared with A/D
converter channel 3 input
3 3 DAC0/ADC2
[OE ]
DAC0 OOpen drain 5V, D/A converter output 0, shared with A/D
converter channel 2 input
[OTP ROM program output enable]
4 4 RESET
[ VPP ]
I
[ P ]
Schmitt Trigger input pin, low active reset with internal
pulled down 50KΩregister *
[OTP ROM program supply voltage]
5 5 VDD PPower
6 7 GND PGround
7 8 OSCO OCrystal OSC output
8 9 OSCI ICrystal OSC input
9 10 P15/INTE0 I/O Bi-directional I/O pin with internally pulled up 22KΩ
register, shared with input pin of external interrupt source0
(NMI), with Schmitt Trigger, selectable triggered, and
internally pulled up 22KΩregister
10 11 P14/PATTERN
[ A15/CE ]
I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22KΩ
register, shared with the output of self test pattern
[ OTP ROM program address buffer & chip enable ]
11 12 P13/HALFI
[ A11 ]
P13 I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22KΩ
register, shared with half Hsync input.
[ OTPROM program address buffer ]
12 13 P12/HALFO
[ A10 ]
P12 I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22KΩ
register, shared with half Hsync output
[ OTPROM program address buffer ]
13 14 P11/ADC1
[ A9 ]
P11 I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22KΩregister,
shared with A/D converter channel 1 input
[ OTPROM program address buffer ]
14 15 P10/ADC0
[ A8 ]
P10 I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22KΩregister,
shared with A/D converter channel 0 input
[ OTPROM program address buffer ]
15 16 P16/INTE1 P16 I/O Bi-directional I/O pin with internally pulled up 22KΩregister,
shared with input pin of external interrupt source1, with
Schmitt Trigger, selectable triggered, and an internal pulled
up 22KΩregister

NT6862-5xxxx
4
Pin Description (continued)
Pin No.
40 Pin 42 Pin Designation Reset Init. I/O Description
16 - 23 17 - 24 P27 –P20
[ DB7] –[ DB0]
I/O
[ I/O ]
Bi-directional I/O pin, push-pull structure with high current
drive/sink capability
[ OTP ROM program data buffer ]
24 25 P30/SDA0
[ A12 ]
P30 I/O
[ I ]
Open drain 5V bi-directional I/O pin P30, shared with
SDA0 pin of I2C bus Schmitt Trigger buffer
[ OTPROM program address buffer ]
25 26 P31/SCL0
[ A13 ]
P31 I/O
[ I ]
Open drain 5V bi-directional I/O pin P31, shared with
SCL0 pin of I2c bus Schmitt Trigger buffer
[ OTPROM program address buffer ]
26 27 P00/DAC7
[ A0 ]
P00 I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22KΩ
register, shared with open drain 5V D/A converter output
8
[ OTPROM program address buffer ]
27 28 P01/DAC8
[ A1 ]
P01 I/O
[ I ]
Bi-directional I/O pin withinternallypulled up 22KΩ
register, shared with open drain 5V D/A converter output
9
[ OTPROM program address buffer ]
28 29 P02/DAC9
[ A2 ]
P02 I/O
[ I ]
Bi-directional I/O pin withinternallypulled up 22KΩ
register, shared with open drain 5V D/A converter output
10
[ OTPROM program address buffer ]
29 30 P03/DAC10
[ A3 ]
P03 I/O
[ I ]
Bi-directional I/O pin withinternallypulled up 22KΩ
register, shared with open drain 5V D/A converter output
11
[ OTPROM program address buffer ]
30 31 P04/DAC11
[ A4 ]
P04 I/O
[ I ]
Bi-directional I/O pin withinternallypulled up 22KΩ
register, shared with open drain 5V D/A converter output
12
[ OTPROM program address buffer ]
31 32 P05/DAC12
[ A5 ]
P05 I/O
[ I ]
Bi-directional I/O pin withinternallypulled up 22KΩ
register, shared with open drain 5V D/A converter output
13
[ OTPROM program address buffer ]
32 33 P06/VSYNCO
[ A6 ]
P06 I/O
[ I ]
Bi-directional I/O pin withinternallypulled up 22KΩ
register, shared with vsync out
[ OTPROM program address buffer ]
33 34 P07/HSYNCO
[ A7 ]
P07 I/O
[ I ]
Bi-directional I/O pin withinternallypulled up 22KΩ
register, shared with hsync out
[ OTPROM program address buffer ]
34 35 CREG OOn chip voltage regulator output. [Connect external
regulating cap. (10µF - 100µF) here]
35 36 DAC6
[RESET]O
[ I ] Open drain 5V, D/A converter output 6
[ OTPROM reset ]

NT6862-5xxxx
5
Pin Description (continued)
Pin No. Designation Reset Init. I/O Description
40 Pin 42 Pin
36 38 DAC5/SDA1
[ MODE2 ]
O
[ I ]
Open drain 5V, D/A converter output 5, shared with open
drain SDA1 line of I2C bus, Schmitt Trigger buffer
[ OTPROM modeselect]
37 39 DAC4/SCL1
[ MODE1 ]
O
[ I ]
Open drain 5V, D/A converter output 4, shared with open
drain SCL1 line of I2C bus, Schmitt Trigger buffer
[ OTPROM modeselect]
38 40 DAC3
[ MODE0 ]
O
[ I ]
Open drain 5V, D/A converter output 3
[ OTPROM modeselect]
39 41 HSYNCI IDebouncing & Schmitt Trigger input pin for video
horizontal sync signal internally pulled high, shared with
composite sync input. A jitter filter is added at the front
end, it could effectually reduce the jitter interference of
external noisy Hsync input.
40 42 VSYNCI/INTV
[ A14 ]
VSYNCI I
[ I ]
Debouncing & Schmitt Trigger input pin for video vertical
sync signal, internal pull high, shared with input pin of
external interrupt source intv with Schmitt Trigger,
selectable triggered, and internal pulled up 22KΩregister
[ OTPROM program address buffer ]
-6P40 I/O Bi-directional I/O pin with internal pulled up 22KΩ
register, only 42 pinS-DIP available
-37 P41 I/O Bi-directional I/O pin with internal pulled up 22KΩ
register, only 42 pinS-DIP available
*This RESET pin must be pulled high by an external pulled-up register (5KΩsuggestion), or it will remain in low voltage
and continually keep the system in a rest state..

NT6862-5xxxx
6
Functional Description
1. 6502 CPU
The 6502 is an 8-bit CPU that provides 56 instructions, decimal and binary arithmetic, thirteen addressing modes, true
indexing capability, programmable stack pointer and variable length stack, a wide selection of addressable memory ranges,
and interrupt input options.
The CPU clock cycle is 4MHz (8MHz system clock divided by 2). Please refer to the 6502 data sheet for more detailed
information.
Accumulator A
Index Register Y
07
7
Index Register X
7 0
0
Stack Pointer SP 0
Status Register P
07
Carry
Zero
IRQ Disable
Decimal Mode
BRK Command
Overflow
Negative
Figure 1.1. The 6502 CPU Registers and Status Flags
7
Program Counter PCH 815
7 0
PCL
1=TRUE
1=Result ZERO
1=DISABLE
1=TRUE
1=NEG
1=TRUE
1=BRK
NVC ZID
B

NT6862-5xxxx
7
2. Instruction Set List
Instruction Code Meaning Operation
ADC Add with carry A + M + C→A, C
AND Logical AND A•M →A
ASL Shift left one bit C ←M7 …M0 ←0
BCC Branch if carry clears Branch on C＝0
BCS Branch if carry sets Branch on C＝1
BEQ Branch if equal to zero Branch on Z ＝1
BIT Bit test A•M, M7→N, M6→V
BMI Branch if minus Branch on N＝1
BNE Branch if not equal to zero Branch on Z ＝0
BPL Branch if plus Branch on N＝0
BRK Break Forced Interrupt PC+2↓PC↓
BVC Branch if overflow clears Branch on V ＝0
BVS Branch if overflow sets Branch on V ＝1
CLC Clear carry 0 →C
CLD Clear decimal mode 0 →D
CLI Clear interrupt disable bit 0 →I
CLV Clear overflow 0 →V
CMP Compare Accumulator to memory A －M
CPX Compare with index register X X －M
CPY Compare with index register Y Y －M
DEC Decrement memory by one M －1→M
DEX Decrement index X by one X －1→X
DEY Decrement index Y by one Y －1→Y
EOR Logical exclusive-OR A ⊕M→A
INC Increment memory by one M + 1→M
INX Increment index X by one X + 1→X
INY Increment index Y by one Y + 1→Y

NT6862-5xxxx
8
Instruction Set List (continued)
Instruction Code Meaning Operation
JMP Jump to new location (PC+1)→PCL, (PC+2)→PCH
JSR Jump to subroutine PC+2↓, (PC+1)→PCL, (PC+2)→PCH
LDA Load accumulator with memory M →A
LDX Load index register X with memory M →X
LDY Load index register Y with memory M →Y
LSR Shift right one bit 0 →M7 …M0 →C
NOP No operation No operation (2 cycles)
ORA Logical OR A + M →A
PHA Push accumulator on stack A ↓
PHP Push status register on stack P ↓
PLA Pull accumulator from stack A ↑
PLP Pullstatusregisterfromstack P ↑
ROL Rotate left through carry C ←M7 …M0 ←C
ROR Rotate right through carry C →M7 …M0 →C
RTI Return from interrupt P ↑, PC↑
RTS Return from subroutine PC ↑, PC+1→PC
SBC Subtract with borrow A －M －C→A, C
SEC Set carry 1 →C
SED Setdecimalmode 1 →D
SEI Set interrupt disable status 1 →I
STA Store accumulator in memory A →M
STX Store index register X in memory X →M
STY Store index register Y in memory Y →M
TAX Transfer accumulator to index X A →X
TAY Transfer accumulator to index Y A →Y
TSX Transfer stack pointer to index X S →X
TXA Transfer index X to accumulator X →A
TXS Transfer index X to stack pointer X →S
TYA Transfer index Y to accumulator Y →A
* Refer to 6502 programming data book for more details.

NT6862-5xxxx
9
3. RAM: 512 X 8 bits
The built-in 512X8-bit SRAM is used for data memory and stack area. The RAM addressing range is from $0080 to $027F.
The contents of RAM are undetermined at power-up and are not affected by system reset. Software programmers can
allocate stack area in the RAM by setting stack pointer register (S). Because the 6502 default stack pointer is $01FF,
programmers must set S register to FFH when starting the program.
as; LDX #$FF
TXS
RAM
Unused
ROM
$0000
$0080
$8000
$FFFF
stack pointer
$FFFE
$FFFD
$FFFC RST-L
RST-H
IRQ-L
IRQ-H
RESET vector
IRQ vector
$027F
$0280
( 32 K Bytes )
$003D System Registers
Unused
$7FFF
( 512 Bytes )
$FFFB
$FFFA NMI-L
NMI-H NMI vector
$01FF
4. ROM: 32K X 8bits
NT6862 provides maximum 32K ROM space for code. The ROM space is located from $8000 to $FFFF.
The addresses, from $FFFA to $FFFF, are reserved for the 6502 CPU vectors, thus users must arrange them sepately.

NT6862-5xxxx
10
5. System Registers
Addr. Register INIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W
Control Registers for I/O Port0 & Port1
$0000 PT0 FFH P07 P06 P05 P04 P03 P02 P01 P00 RW
$0001 PT1 7FH -P16 P15 P14 P13 P12 P11 P10 RW
Control Register to Control Port2 I/O Direction
$0002 PT2DIR FFH P27OE P26OE P25OE P24OE P23OE P22OE P21OE P20OE W
Control Registers for I/O Port2 - 4
$0003 PT2 FFH P27 P26 P25 P24 P23 P22 P21 P20 RW
$0004 PT3 03H - - - - - - P31 P30 RW
$0005 PT4 03H Only available for the 42 Pin SDIP version -P41 P40 RW
Control Registers for Synprocessor
FFH - - - -
INSEN
-HSEL S/CR$0006 SYNCON
FFH - - - -
INSEN
ENHSEL HSEL S/CW
FFH - - HSYNCI VSYNCI HPOLI VPOLI HPOLO VPOLO R$0007 HV CON
FFH
ENHOUT
ENHOUT
- - - - HPOLO VPOLO W
$0008 HCNT L 00H HCL7 HCL6 HCL5 HCL4 HCL3 HCL2 HCL1 HCL0 R
HCNTOV - - - HCH3 HCH2 HCH1 HCH0 R$0009 HCNT H 00H
CLRHOV - - - - - - - W
$000A VCNT L 00H VCL7 VCL6 VCL5 VCL4 VCL3 VCL2 VCL1 VCL0 R
VCNTOV -VCH5 VCH4 VCH3 VCH2 VCH1 VCH0 R$000B VCNT H 00H
CLRVOV - - - - - - - W
$000C FREECON FFH ENPAT PAT1 - - - FREQ2 FREQ1 FREQ0 W
$000D HALFCON FFH ENHALF NOHALF HALFPOL - - - - - W
$000E AUTOMUTE FFH
ENHDIFF
ENPOL ENOVER -HDIFFVL3 HDIFFVL2 HDIFFVL1 HDIFFVL0 W
Control Registers to Enable PWM 7 - 12 Channels
$000F ENDAC FFH - - ENDK12 ENDK11 ENDK10 ENDK9 ENDK8 ENDK7 W
Control Registers for ADC 0 - 3 Channels
$0010 ENADC FFH CSTA - - - ENADC3 ENADC2 ENADC1 ENADC0 W
$0011 AD0 REG C0H - - AD05 AD04 AD03 AD02 AD01 AD00 R
$0012 AD1 REG 00H - - AD15 AD14 AD13 AD12 AD11 AD10 R
$0013 AD2 REG 00H - - AD25 AD24 AD23 AD22 AD21 AD20 R
$0014 AD3 REG 00H - - AD35 AD34 AD33 AD32 AD31 AD30 R