Nuvoton NuMicro MS51 Series Product manual

MS51
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MS51 SERIES TECHNICAL REFERENCE MANUAL
1T 8051
8-bit Microcontroller
NuMicro®Family
MS51 Series
MS51FB9AE
MS51XB9AE
MS51XB9BE
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com

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TABLE OF CONTENTS
1GENERAL DESCRIPTION ..............................................................................8
2FEATURES......................................................................................................9
3PARTS INFORMATION.................................................................................12
3.1 Package Type .............................................................................................................. 12
3.2 MS51 Series Selection Guide.................................................................................... 12
3.3 MS51 Series Selection Code..................................................................................... 13
4PIN CONFIGURATION ..................................................................................14
4.1 MS51 16KB Series Multi Function Pin Diagram ..................................................... 14
4.1.1 TSSOP 20-pin Package Pin Diagram ........................................................................14
4.1.2 QFN 20-pin Package Pin Diagram .............................................................................15
4.2 MS51 16KB Series Pin Description .......................................................................... 17
5BLOCK DIAGRAM.........................................................................................19
5.1 MS51 16KB Series Block Diagram........................................................................... 20
6FUNCTION DESCRIPTION ...........................................................................21
6.1 Memory Organization.................................................................................................. 21
6.1.1 Program Memory............................................................................................................21
6.1.2 Data Flash .......................................................................................................................23
6.1.3 Security Protection Memory (SPROM) .......................................................................23
6.1.4 Config Bytes....................................................................................................................23
6.1.5 Data Memory...................................................................................................................28
6.1.6 Special Function Register (SFR)..................................................................................30
6.2 System Manager........................................................................................................ 153
6.2.1 Clock System ................................................................................................................153
6.2.2 Power Management.....................................................................................................158
6.2.3 Power Monitoring And Reset ......................................................................................160
6.2.4 Power-On Reset and Low Voltage Reset .................................................................160
6.2.5 Brown-Out Detect and Reset......................................................................................160
6.2.6 External Reset and Hard Fault Reset........................................................................161
6.2.7 Watchdog Timer Reset ................................................................................................162
6.2.8 Software Reset .............................................................................................................163
6.2.9 Boot Select ....................................................................................................................164
6.2.10Reset State....................................................................................................................165
6.2.11 Interrupt System ...........................................................................................................165
6.2.12Enabling Interrupts .......................................................................................................166
6.2.13Interrupt Priorities .........................................................................................................167
6.2.14Interrupt Service ...........................................................................................................168
6.2.15Interrupt Latency...........................................................................................................169

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6.2.16External Interrupt Pins .................................................................................................169
6.3 Flash Memory Contorl .............................................................................................. 180
6.3.1 In-Application-Programming (IAP) .............................................................................180
6.3.2 In-Circuit-Programming (ICP).....................................................................................190
6.3.3 ON-CHIP-DEBUGGER (OCD)...................................................................................190
6.3.4 96-Bit Unique Code......................................................................................................192
6.4 General Purpose IO (GPIO) .................................................................................... 193
6.4.1 GPIO Mode ...................................................................................................................193
6.4.2 Control Registers of GPIO ..........................................................................................195
6.4.3 Read-Modify-Write Instructions..................................................................................198
6.4.4 Pin Interrupt...................................................................................................................199
6.5 Timer............................................................................................................................ 205
6.5.1 Timer/Counter 0 And 1.................................................................................................205
6.5.2 Timer2 And Input Capture ...........................................................................................210
6.5.3 Timer3 ............................................................................................................................225
6.6 Watchdog Timer (WDT) ............................................................................................ 228
6.6.1 Time-Out Reset Timer..................................................................................................229
6.6.2 General Purpose Timer ...............................................................................................229
6.7 Self Wake-Up Timer (WKT)...................................................................................... 232
6.8 Serial Port (UART0 & UART1) ................................................................................ 235
6.8.1 Operating Mode............................................................................................................235
6.8.2 Baud Rate......................................................................................................................237
6.8.3 Framing Error Detection ..............................................................................................240
6.8.4 Multiprocessor Communication..................................................................................241
6.8.5 Automatic Address Recognition .................................................................................241
6.8.6 Control Register of UART............................................................................................243
6.9 Serial Peripheral Interface (SPI) ............................................................................. 255
6.9.1 Operating Modes..........................................................................................................257
6.9.2 Clock Formats and Data Transfer ..............................................................................257
6.9.3 Slave Select Pin Configuration...................................................................................260
6.9.4 Mode Fault Detection...................................................................................................260
6.9.5 Write Collision Error .....................................................................................................260
6.9.6 Overrun Error ................................................................................................................260
6.9.7 SPI Interrupt ..................................................................................................................261
6.9.8 Control Register............................................................................................................261
6.10 Inter-Integrated Circuit (I2C) ............................................................................... 265
6.10.1Functional Description .................................................................................................265
6.10.2Operation Modes ..........................................................................................................269
6.10.3Miscellaneous States...................................................................................................274
6.10.4I2C Time-Out..................................................................................................................274

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6.10.5I2C Interrupt ...................................................................................................................275
6.10.6Control Registers..........................................................................................................275
6.10.7Typical Structure of I2C Interrupt Service Routine...................................................279
6.11 Pulse Width Modulated (PWM) ......................................................................... 283
6.11.1 PWM Generator............................................................................................................283
6.11.2 PWM Types ...................................................................................................................286
6.11.3 Operation Modes..........................................................................................................287
6.11.4 Mask Output Control....................................................................................................288
6.11.5 Fault Brake ....................................................................................................................288
6.11.6 Polarity Control .............................................................................................................288
6.11.7 PWM Interrupt...............................................................................................................289
6.11.8 Control Regsiter............................................................................................................289
6.12 12-Bit Analog-To -Digital Converter (ADC) ....................................................... 297
6.12.1ADC Operation..............................................................................................................298
6.12.2ADC Conversion Triggered by External Source ......................................................298
6.12.3ADC Conversion Result Comparator ........................................................................299
6.12.4Internal Band-gap.........................................................................................................299
6.12.5Control Registers..........................................................................................................300
6.13 Auxiliary Features................................................................................................ 305
6.13.1Dual DPTRs ..................................................................................................................305
7PACKAGE DIMENSIONS............................................................................307
7.1 TSSOP 20-pin (4.4 x 6.5 x 0.9 mm) ...................................................................... 307
7.2 QFN 20-pin (3.0 x 3.0 x 0.8 mm) for MS51XB9AE .............................................. 309
7.3 QFN 20-pin (3.0 x 3.0 x 0.6mm) for MS51XB9BE ............................................... 310
8INSTRUCTION SET.....................................................................................311
8.1 Instruction Set and Address Mode.......................................................................... 311
8.2 Instruction Set ............................................................................................................ 312
9REVISION HISTORY ...................................................................................315

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LIST OF FIGURES
Figure 4.1-1 Pin Assignment of TSSOP-20 Package.................................................................... 14
Figure 4.1-2 Pin Assignment of QFN-20 Package......................................................................... 15
Figure 4.1-3 Pin Assignment of QFN-20 Package......................................................................... 16
Figure 5.1-1 Functional Block Diagram.......................................................................................... 20
Figure 6.1-1 MS51 Program Memory Map and Boot Select.......................................................... 22
Figure 6.1-2 SPROM Memory Mapping And SPROM Security Mode........................................... 23
Figure 6.1-3 CONFIG0 Any Reset Reloading................................................................................ 24
Figure 6.1-4 CONFIG2 Power-On Reset Reloading...................................................................... 26
Figure 6.1-5 Data Memory Map..................................................................................................... 28
Figure 6.1-6 Internal 256 Bytes RAM Addressing.......................................................................... 29
Figure 6.2-1 Clock System Block Diagram .................................................................................. 153
Figure 6.2-2 Boot Selecting Diagram........................................................................................... 164
Figure 6.4-1 Quasi-Bidirectional Mode Structure......................................................................... 194
Figure 6.4-2 Push-Pull Mode Structure........................................................................................ 194
Figure 6.4-3 Input-Only Mode Structure ...................................................................................... 194
Figure 6.4-4 Open-Drain Mode Structure .................................................................................... 195
Figure 6.4-5 Pin Interface Block Diagram.................................................................................... 200
Figure 6.5-1 Timer/Counters 0 and 1 in Mode 0.......................................................................... 205
Figure 6.5-2 Timer/Counters 0 and 1 in Mode 1.......................................................................... 206
Figure 6.5-3 Timer/Counters 0 and 1 in Mode 2.......................................................................... 206
Figure 6.5-4 Timer/Counter 0 in Mode 3...................................................................................... 207
Figure 6.5-5 Timer 2 Full Function Block Diagram ...................................................................... 211
Figure 6.5-6 Timer 2 Auto-Reload Mode Block Diagram............................................................. 212
Figure 6.5-7 Timer 2 Compare Mode Block Diagram.................................................................. 213
Figure 6.5-8 Timer 3 Block Diagram............................................................................................ 225
Figure 6.6-1 WDT as A Time-Out Reset Timer............................................................................ 229
Figure 6.6-2 Watchdog Timer Block Diagram.............................................................................. 229
Figure 6.7-1 Self Wake-Up Timer Block Diagram........................................................................ 232
Figure 6.8-1 Serial Port Mode 0 Timing Diagram ........................................................................ 235
Figure 6.8-2 Serial Port Mode 1 Timing Diagram ........................................................................ 236
Figure 6.8-3 Serial Port Mode 2 and 3 Timing Diagram.............................................................. 237
Figure 6.9-1 SPI Block Diagram................................................................................................... 255
Figure 6.9-2 SPI Multi-Master, Multi-Slave Interconnection ........................................................ 256
Figure 6.9-3 SPI Single-Master, Single-Slave Interconnection.................................................... 256
Figure 6.9-4 SPI Clock Formats................................................................................................... 258
Figure 6.9-5 SPI Clock and Data Format with CPHA = 0............................................................ 259

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Figure 6.9-6 SPI Clock and Data Format with CPHA = 1............................................................ 259
Figure 6.9-7 SPI Overrun Waveform............................................................................................ 261
Figure 6.9-8 SPI Interrupt Request.............................................................................................. 261
Figure 6.10-1 I2C Bus Interconnection......................................................................................... 265
Figure 6.10-2 I2C Bus Protocol .................................................................................................... 266
Figure 6.10-3 START, Repeated START, and STOP Conditions ............................................... 266
Figure 6.10-4 Master Transmits Data to Slave by 7-bit ............................................................... 267
Figure 6.10-5 Master Reads Data from Slave by 7-bit................................................................. 267
Figure 6.10-6 Data Format of One I2C Transfer........................................................................... 267
Figure 6.10-7 Acknowledge Bit.................................................................................................... 268
Figure 6.10-8 Arbitration Procedure of Two Masters................................................................... 268
Figure 6.10-9 Control I2C Bus according to the Current I2C Status............................................. 269
Figure 6.10-10 Flow and Status of Master Transmitter Mode ..................................................... 270
Figure 6.10-11 Flow and Status of Master Receiver Mode ......................................................... 271
Figure 6.10-12 Flow and Status of Slave Receiver Mode............................................................ 272
Figure 6.10-13 Flow and Status of General Call Mode................................................................ 273
Figure 6.10-14 I2C Time-Out Counter.......................................................................................... 275
Figure 6.10-15 Hold Time extend enable..................................................................................... 276
Figure 6.11-1 PWM Block Diagram.............................................................................................. 284
Figure 6.11-2 PWM and Fault Brake Output Control Block Diagram .......................................... 285
Figure 6.11-3 PWM Edge-aligned Type Waveform..................................................................... 286
Figure 6.11-4 PWM Center-aligned Type Waveform................................................................... 287
Figure 6.11-5 PWM Complementary Mode with Dead-time Insertion ......................................... 288
Figure 6.11-6 Fault Brake Function Block Diagram..................................................................... 288
Figure 6.11-7 PWM Interrupt Type............................................................................................... 289
Figure 6.12-112-bit ADC Block Diagram..................................................................................... 297
Figure 6.12-2 External Triggering ADC Circuit ............................................................................ 299
Figure 6.12-3 ADC Result Comparator........................................................................................ 299
Figure 7.1-1 TSSOP-20 Package Dimension.............................................................................. 307
Figure 7.2-1 QFN-20 Package Dimension for MS51XB9AE ....................................................... 309
Figure 7.3-1 QFN-20 Package Dimension for MS51XB9BE ....................................................... 310

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List of Tables
Table 6.1-1 Special Function Register Memory Map..................................................................... 34
Table 6.1-2 SFR Definitions and Reset Values ............................................................................. 38
Table 6.2-1 Interrupt Vectors ....................................................................................................... 166
Table 6.2-2 Interrupt Priority Level Setting .................................................................................. 167
Table 6.2-3 Characteristics of Each Interrupt Source.................................................................. 168
Table 6.3-1 IAP Modes and Command Codes............................................................................ 181
Table 6.4-1 Configuration for Different I/O Modes....................................................................... 193
Table 6.6-1 Watchdog Timer-out Interval Under Different Pre-scalars........................................ 228
Table 6.8-1 Serial Port UART0 Mode / baudrate Description...................................................... 238
Table 6.8-2 Serial Port UART1 Mode / baudrate Description...................................................... 239
Table 6.9-1 Slave Select Pin Configurations ............................................................................... 257
Table 8.1-1 Instructions That Affect Flag Settings....................................................................... 311
Table 8.2-1 Instruction Set........................................................................................................... 314

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1 GENERAL DESCRIPTION
The MS51 16KB series are embedded flash type, 8-bit high performance 1T 8051-based
microcontroller. The instruction set is fully compatible with the standard 80C51 and performance
enhanced.
The MS51 16KB series contains a up of main Flash called APROM, in which the contents of User
Code resides. The MS51 Flash supports In-Application-Programming (IAP) function, which enables
on-chip firmware updates. IAP also makes it possible to configure any block of User Code array to be
used as non-volatile data storage, which is written by IAP and read by IAP or MOVC instruction, this
function means whole 16K Bytes area all can be use as Data Flash through IAP command. MS51
support an function of configurationable Flash from APROM called LDROM, in which the Boot Code
normally resides for carrying out In-System-Programming (ISP). The LDROM size is configurable with
a maximum of 4K Bytes by CONFIG define. There is an additional include special 128 bytes security
protection memory (SPROM) to enhance the security and protection of customer application. To
facilitate programming and verification, the Flash allows to be programmed and read electronically by
parallel Writer or In-Circuit-Programming (ICP). Once the code is confirmed, user can lock the code for
security.
The MS51 16KB series provides rich peripherals including 256 Bytes of SRAM, 1K Bytes of auxiliary
RAM (XRAM), Up to 18 general purpose I/O, two 16-bit Timers/Counters 0/1, one 16-bit Timer2 with
three-channel input capture module, one Watchdog Timer (WDT), one Self Wake-up Timer (WKT),
one 16-bit auto-reload Timer3 for general purpose or baud rate generator, two UARTs with frame error
detection and automatic address recognition, one SPI, one I2C, five enhanced PWM output channels,
eight-channel shared pin interrupt for all I/O, and one 12-bit ADC. The peripherals are equipped with
18 sources with 4-level-priority interrupts capability.
The MS51 16KB series is equipped with three clock sources and supports switching on-the-fly via
software. The three clock sources include external clock input, 10 kHz internal oscillator, and one 16
MHz internal precise oscillator that is factory trimmed to ±1% at room temperature. The MS51
provides additional power monitoring detection such as power-on reset and 4-level brown-out
detection, which stabilizes the power-on/off sequence for a high reliability system design.
The MS51 16KB series microcontroller operation consumes a very low power with two economic
power modes to reduce power consumption －Idle and Power-down mode, which are software
selectable. Idle mode turns off the CPU clock but allows continuing peripheral operation. Power-down
mode stops the whole system clock for minimum power consumption. The system clock of the MS51
can also be slowed down by software clock divider, which allows for a flexibility between execution
performance and power consumption.
With high performance CPU core and rich well-designed peripherals, the MS51 benefits to meet a
general purpose, home appliances, or motor control system accomplishment.

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2 FEATURES
Core and System
8051
Fully static design 8-bit high performance 1T 8051-based
CMOS microcontroller.
Instruction set fully compatible with MCS-51.
4-priority-level interrupts capability.
Dual Data Pointers (DPTRs).
Power On Reset (POR)
POR with 1.15V threshold voltage level
Brown-out Detector (BOD)
4-level selection, with brown-out interrupt and reset option.
(4.4V / 3.7V / 2.7V / 2.2V)
Low Voltage Reset (LVR)
LVR with 2.0V threshold voltage level
Security
96-bit Unique ID (UID)
128-bit Unique Customer ID (UCID)
128-bytes security protection memory SPROM
Memories
Flash
16 KBytes of APROM for User Code.
4/3/2/1 Kbytes of Flash for loader (LDROM) configure from
APROM for In-System-Programmable (ISP)
Flash Memory accumulated with pages of 128 Bytes from
APROM by In-Application-Programmable (IAP) means whole
APROM can be use as Data Flash
An additional 128 bytes security protection memory SPROM
Code lock for security by CONFIG
SRAM
256 Bytes on-chip RAM.
Additional 1 KBytes on-chip auxiliary RAM (XRAM) accessed
by MOVX instruction.
Clocks
Internal Clock Source
Default 16 MHz high-speed internal oscillator (HIRC) trimmed
to ±1% (accuracy at 25 °C, 3.3 V), ±2% in -20~105°C.
Selectable 24 MHz high-speed internal oscillator (HIRC).
10 kHz low-speed internal oscillator (LIRC) calibrating to ±1%
by software from high-speed internal oscillator
Timers

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16-bit Timer
Two 16-bit Timers/Counters 0 and 1 compatible with standard
8051.
One 16-bit Timer2 with three-channel input capture module
and 9 input pin can be selected.
One 16-bit auto-reload Timer3, which can be the baud rate
clock source of UART0 and UART1.
Watchdog
6-bit free running up counter for WDT time-out interval.
Selectable time-out interval is 6.40 ms ~ 1.638s since
WDT_CLK = 10 kHz (LIRC).
Able to wake up from Power-down or Idle mode
Interrupt or reset selectable on watchdog time-out
Wake-up Timer
16-bit free running up counter for time-out interval.
Clock sources from LIRC
Able self Wake-up wake up from Power-down or Idle mode,
and auto reload count value.
Supports Interrupt
PWM
Up To 6 output pins can be selected
Supports maximum clock source frequency up to 24 MHz
Supports independent mode for PWM output
Supports complementary mode for 3 complementary paired
PWM output channels
Supports 16-bit resolution PWM counter
Supports mask function and tri-state enable for each PWM pin
PWM0 module support Dead-time insertion with 8-bit
resolution
PWM0 module Supports brake function
PWM0 module Supports trigger ADC on the following events
Analog Interfaces
Analog-to-Digital
Converter (ADC)
Analog input voltage range: 0 ~ AVDD.
12-bit resolution and 10-bit accuracy is guaranteed.
Up to 8 single-end analog input channels
1 internal channels, they are band-gap voltage (VBG).
Up to 500 KSPS sampling rate.
Software Write 1 to ADCS bit.
External pin (STADC) trigger
PWM trigger.
Communication Interfaces

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UART
Supports up to 2 UARTs: UART0 & UART1
Full-duplex asynchronous communications
Programmable 9th bit.
TXD and RXD of UART0 pins exchangeable via software.
I2C
1 sets of I2C devices
Master/Slave mode
Bidirectional data transfer between masters and slaves
7-bit addressing mode
Standard mode (100 kbps) and Fast mode (400 kbps).
Supports 8-bit time-out counter requesting the I2C interrupt if
the I2C bus hangs up and timer-out counter overflows
Supports hold time programmable
SPI
1 sets of SPI devices
Supports Master or Slave mode operation
Supports MSB first or LSB first transfer sequence
slave mode up to 12 MHz
GPIO
Four I/O modes:
–Quasi-bidirectional mode
–Push-Pull Output mode
–Open-Drain Output mode
–Input only with high impendence mode
Schmitt trigger input / TTL mode selectable.
Each I/O pin configured as interrupt source with edge/level
trigger setting
Standard interrupt pins INT0 and INT1.
Supports high drive and high sink current I/O
I/O pin internal pull-up or pull-down resistor enabled in input
mode.
Maximum I/O Speed is 24 MHz
Each GPIO enabling the pin interrupt function will also enable
the wake-up function
ESD & EFT
ESD
HBM pass 8 kV
EFT
> ± 4.4 kV
Latch-up
150 mA pass

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3 PARTS INFORMATION
3.1 Package Type
MSOP10
TSSOP14
TSSOP20
QFN20
TSSOP28
LQFP32
QFN33
Part
No.
MS51BA9AE
MS51DA9AE
MS51FB9AE
MS51FC0AE
MS51XB9AE
MS51XB9BE
MS51XC0BE
MS51EC0AE
MS51PC0AE
MS51TC0AE
3.2 MS51 Series Selection Guide
Part Number
Flash (KB)
SRAM (KB)
ISP ROM (KB) [1]
I/O
Timer/
PWM
Connectivity
ADC(12-Bit)
Package
ISO-7816 [2]
UART
SPI
I2C
MS51BA9AE
8
1
4
8
4
5
-
2
-
1
5-ch
MSOP10
MS51DA9AE
8
1
4
12
4
5
-
2
1
1
7-ch
TSSOP14
MS51XB9AE
16
1
4
18
4
6
-
2
1
1
8-ch
QFN20[3]
MS51XB9BE
16
1
4
18
4
6
-
2
1
1
8-ch
QFN20[3]
MS51FB9AE
16
1
4
18
4
6
-
2
1
1
8-ch
TSSOP20
MS51FC0AE
32
2
4
18
4
8
2
2
1
1
10-ch
TSSOP20
MS51XC0BE
32
2
4
18
4
8
2
2
1
1
10-ch
QFN20
MS51EC0AE
32
2
4
26
4
10
3
2
1
1
15-ch
TSSOP28
MS51PC0AE
32
2
4
30
4
12
3
2
2
1
15-ch
LQFP32
MS51TC0AE
32
2
4
30
4
12
3
2
2
1
15-ch
QFN33
Note:
1. ISP ROM programmable 1K/2K/3K/4KB Flash for user program loader (LDROM) share from ARPOM.
2. ISO-7816 configurable as UART2.
3. Detailed package information please refer to Chapter 7
4. This TRM only for 16KB flash size part number product

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3.3 MS51 Series Selection Code
MS
51
F
B
9
A
E
Core
Line
Package
Flash
SRAM
Reserve
Temperature
1T 8051
Industry
51: Base
B: MSOP10 (3x3 mm)
D: TSSOP14 (4.4x5.0 mm)
E: TSSOP28 (4.4x9.7 mm)
F: TSSOP20 (4.4x6.5 mm)
I: SOP8 (4x5 mm)
O: SOP20 (300 mil)
P: LQFP32 (7x7 mm)
T: QFN33 (4x4 mm)
U: SOP28 (300 mil)
X: QFN20 (3x3mm)
A: 8 KB
B: 16 KB
C: 32 KB
0: 2 KB
1: 4 KB
2: 8/12 KB
3: 16 KB
6: 32 KB
8: 64 KB
9: 1 KB
A: 96 KB
E:-40 ~ 105°C

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4 PIN CONFIGURATION
Users can find pin configuaration informations by using NuTool - PinConfigure. The NuTool -
PinConfigure contains all Nuvoton NuMicro®Family chip series with all part number, and helps users
configure GPIO multi-function correctly and handily.
4.1 MS51 16KB Series Multi Function Pin Diagram
4.1.1 TSSOP 20-pin Package Pin Diagram
Corresponding Part Number: MS51FB9AE
10
9
2
1
4
3
6
5
8
7
nRESET / P2.0
VSS
18
19
16
17
14
15
12
13
11
20
VDD
MS51FB9AE
[I2C0_SDA] / UART1_TXD / ICE_DAT / P1.6
P1.3 / I2C0_SCL / [STADC]
P1.4 / I2C0_SDA / PWM0_BRAKE / PWM0_CH1
P1.1 / ADC_CH7 / PWM0_CH1/ IC1 / CLKO
P1.0 / PWM0_CH2 / IC2 / SPI0_CLK
P0.0 / PWM0_CH3 / IC3 / SPI0_MOSI / T1
P0.1 / PWM0_CH4 / IC4 / SPI0_MISO
P0.3 / ADC_CH6 / PWM0_CH5 / IC5 /
P0.4 / ADC_CH5 / PWM0_CH3 / IC3 / STADC
UART0_TXD / ADC_CH3 / P0.6
UART0_RXD / ADC_CH2 / P0.7
INT0 / OSCIN / ADC_CH1 / P3.0
IC7 / SPI0_SS / PWM0_CH5 / P1.5
P0.2 / ICE_CLK / UART1_RXD / [I2C0_SCL]
INT1 / ADC_CH0 / P1.7
IC6 / T0 / PWM0_CH2 / ADC_CH4 / P0.5
P1.2 / PWM0_CH0 / IC0
[ ] alternate function remapping , if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function.
Figure 4.1-1 Pin Assignment of TSSOP-20 Package

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MS51 SERIES TECHNICAL REFERENCE MANUAL
4.1.2 QFN 20-pin Package Pin Diagram
MS51XB9AE Pin Diagram
4.1.2.1
Corresponding Part Number: MS51XB9AE
MS51XB9AE
15 14 13 12 11
10
9
8
7
6
21 3 4 5
16
17
18
19
20
VSS
VDD
[ ] alternate function remapping , if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function.
PWM0_CH2 / IC6 / T0 / ADC_CH4 / P0.5
UART0_TXD / ADC_CH3 / P0.6
nRESET / P2.0
INT0 / OSCIN / ADC_CH1 / P3.0
ADC_CH5 / STADC / PWM0_CH3 / IC3 / P0.4
P0.3 / PWM0_CH5 / IC5 / ADC_CH6 P0.2 / ICE_CLK / UART1_RXD/[SCL] P0.1 / PWM0_CH4 / IC4 / SPI0_MISO P0.0 / PWM0_CH3 / IC3 / SPI0_MOSI / T1
P1.3 / I2C0_SCL / [STADC]
P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE
P1.2 / PWM0_CH0 / IC0
P1.1 / PWM0_CH1 / IC1 / ADC_CH7 /CLKO
P1.0 / PWM0_CH2 / IC2 / SPI0_CLK
P1.5 / PWM0_CH5 / IC7 / SPI0_SS
[SDA] / UART1_TXD / ICE_DAT / P1.6
INT1 / ADC_CH0 / P1.7
UART0_RXD / ADC_CH2 / P0.7
Figure 4.1-2 Pin Assignment of QFN-20 Package

MS51
Dec. 17, 2019 Page 16 of 316 Rev 1.01
MS51 SERIES TECHNICAL REFERENCE MANUAL
MS51XB9BE Pin Diagram4.1.2.2
Corresponding Part Number: MS51XB9BE
MS51XB9BE
15 14 13 12 11
10
9
8
7
6
21 3 4 5
16
17
18
19
20
VSS
VDD
[ ] alternate function remapping , if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function.
P1.2 / PWM0_CH0 / IC0
P1.3 / I2C0_SCL / [STADC]
P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE
P1.5 / PWM0_CH5 / IC7 / SPI0_SS
P1.1 / PWM0_CH1 / IC1 / ADC_CH7 / CLKO P1.0 / PWM0_CH2 / IC2 / SPI0_CLK P0.0 / PWM0_CH3 / IC3 / SPI0_MOSI / T1 P0.1 / PWM0_CH4 / IC4 / SPI0_MISO
P0.2 / ICE_CLK / UART1_RXD/[SCL]
PWM0_CH5 / IC5 / ADC_CH6 / P0.3
ADC_CH5 / STADC / PWM0_CH3 / IC3 / P0.4
PWM0_CH2 / IC6 / T0 / ADC_CH4 / P0.5
UART0_TXD / ADC_CH3 / P0.6
UART0_RXD / ADC_CH2 / P0.7
nRESET / P2.0
INT0 / OSCIN / ADC_CH1 / P3.0
INT1 / ADC_CH0 / P1.7
[SDA] / UART1_TXD / ICE_DAT / P1.6
Figure 4.1-3 Pin Assignment of QFN-20 Package

MS51
Dec. 17, 2019 Page 17 of 316 Rev 1.01
MS51 SERIES TECHNICAL REFERENCE MANUAL
4.2 MS51 16KB Series Pin Description
Pin Number
Symbol
Multi-Function Description[1]
MS51FB9AE
MS51XB9AE
MS51XB9BE
9
5
6
VDD
POWER SUPPLY: Supply voltage VDD for operation.
7
3
4
VSS
GROUND: Ground potential.
16
12
13
P0.0
Port 0 bit 0.
PWM0_CH3
PWM0 output channel 3.
SPI0_MOSI
SPI master output/slave input.
IC3
Input capture channel 3.
T1
External count input to Timer/Counter 1 or its toggle output.
17
13
14
P0.1
Port 0 bit 1.
PWM0_CH4
PWM0 output channel 4.
IC4
Input capture channel 4.
SPI0_MISO
SPI master input/slave output.
18
14
15
P0.2
Port 0 bit 2.
ICE_CLK
ICP / OCD clock input.
UART1_RXD
Serial port 1 receive input.
[I2C0_SCL] [3]
I2C clock.
19
15
16
P0.3
Port 0 bit 3.
ADC_CH6
ADC input channel 6.
PWM0_CH5
PWM0 output channel
IC5
Input capture channel 5.
20
16
17
P0.4
Port 0 bit 4.
PWM0_CH3
PWM0 output channel 3.
IC3
Input capture channel 3.
ADC_CH5
ADC input channel 5.
STADC
External start ADC trigger
1
20
18
P0.5
Port 0 bit 5.
PWM0_CH2
PWM0 output channel 2.
IC6
Input capture channel 6.
T0
External count input to Timer/Counter 0 or its toggle output.
ADC_CH4
ADC input channel 5.
2
19
19
P0.6
Port 0 bit 6.
UART0_TXD [2]
Serial port 0 transmit data output.

MS51
Dec. 17, 2019 Page 18 of 316 Rev 1.01
MS51 SERIES TECHNICAL REFERENCE MANUAL
Pin Number
Symbol
Multi-Function Description[1]
MS51FB9AE
MS51XB9AE
MS51XB9BE
ADC_CH3
ADC input channel 3.
3
1
20
P0.7
Port 0 bit 7.
UART0_RXD
Serial port 0 receive input.
ADC_CH2
ADC input channel 2.
15
7
12
P1.0
Port 1 bit 0.
PWM0_CH2
PWM0 output channel 2.
IC2
Input capture channel 2.
SPI0_CLK
SPI clock.
14
8
11
P1.1
Port 1 bit 1
PWM0_CH1
PWM0_CH1: PWM0 output channel 1.
IC1
Input capture channel 1.
ADC_CH7
ADC input channel 7.
CLKO
System clock output.
13
9
10
P1.2
Port 1 bit 2.
PWM0_CH0
PWM0 output channel 0.
IC0
Input capture channel 0.
12
11
9
P1.3
Port 1 bit 3.
I2C0_SCL
I2C clock.
[STADC][4]
External start ADC trigger
11
10
8
P1.4
Port 1 bit 4.
PWM0_CH1
PWM0 output channel 1.
I2C0_SDA
I2C data.
PWM0_BRAKE
Fault Brake input.
10
6
7
P1.5
Port 1 bit 5.
PWM0_CH5
PWM0 output channel 5.
IC7
Input capture channel 7.
SPI0_SS
SPI slave select input.
8
4
5
P1.6
P1.6: Port 1 bit 6.
ICE_DAT
ICP / OCD data input or output.
UART1_TXD/
Serial port 1 transmit data output.
[I2C0_SDA] [3]
I2C data.
6
2
3
P1.7
Port 1 bit 7.
INT1







External interrupt 1 input.

MS51
Dec. 17, 2019 Page 19 of 316 Rev 1.01
MS51 SERIES TECHNICAL REFERENCE MANUAL
Pin Number
Symbol
Multi-Function Description[1]
MS51FB9AE
MS51XB9AE
MS51XB9BE
ADC_CH0
ADC input channel 0.
4
18
1
P2.0/
Port 2 bit 0 input pin available when RPD (CONFIG0.2) is
programmed as 0.
nRESET
nRESET pin is a Schmitt trigger input pin for hardware device
reset. A low on this pin resets the device. nRESETpin has an
internal pull-up resistor allowing power-on reset by simply
connecting an external capacitor to GND.
5
17
12
P3.0
Port 3 bit 0 available when the internal oscillator is used as the
system clock.
ADC_CH1
ADC input channel 1.
INT0







External interrupt 0 input.
OSCIN
If the ECLK mode is enabled, Xin is the external clock input pin.
Note:
1. All I/O pins can be configured as a interrupt pin. This feature is not listed in multi-function description.
2. UART0_TXD and UART0_RXD pins are software exchangeable by UART0PX (AUXR1.2).
3. [I2C] alternate function remapping option. I2C pins is software switched by I2CPX (I2CON.0).
4. [STADC] alternate function remapping option. STADC pin is software switched by STADCPX(ADCCON1.6).
5. PIOx register decides which pins are PWM or GPIO.
表4.2-1 MS51 16KB Series Pin Description

MS51
Dec. 17, 2019 Page 20 of 316 Rev 1.01
MS51 SERIES TECHNICAL REFERENCE MANUAL
5 BLOCK DIAGRAM
5.1 MS51 16KB Series Block Diagram
Figure 5.1-1 Functional Block Diagram shows the MS51 functional block diagram and gives the outline
of the device. User can find all the peripheral functions of the device in the diagram.
1T High
Performance
8051 Core
256 Bytes
Internal RAM
1K Bytes
XRAM
(Auxiliary RAM)
P0
P1
P2
P3
PWM
Watchdog Timer
Clock Divider
Timer 0/1
Power-on Reset
and Brown-out
Detection
P0[7:0]
P1[7:0]
P20
P30
PWM0_CH0
~
PWM0_CH5
8-bit Internal Bus
T1 (P0.0)
T0 (P0.5)
VDD
GND
10 kHz
Internal RC Oscillator
(LIRC)
8
8
1
System Clock
6
Timer 2
with
Input Capture IC0~IC7
FB (P1.4)
12-bit ADC ADC_CH0 ~ADC_CH7
8
STADC (P1.3 or P0.4)
Self Wake-up
Timer
Timer 3
XIN
8
1
16KB
APROM Flash
Max. 4KB
LDROM Flash
Max. Bytes
Data Flash
(page: 128B)
128 Bytes
SPROM
16 MHz/ 24MHz
Internal RC Oscillator
(HIRC)
Memory
Access
GPIO
External Interrupt
Pin Interrupt
8
Same Port
any bit
INT0 (P3.0)
INT1 (P1.7)
Serial Ports
(UARTs)
I2C
UART0_RXD (P0.7 or P0.6)
UART0_TXD (P0.6 or P0.7)
I2C0_SDA (P1.4 or P1.6)
I2C0_SCL (P1.3 or P0.2)
UART1_RXD (P0.2)
UART1_TXD (P1.6)
SPI SPI0_MISO (P0.1)
SPI0_MOSI (P0.0)
SPI0_CLK (P1.0)
SPI0_SS (P1.5)
Digital
Peripheral
Analog
Peripheral
System Clock
Source
Power
Management
nRESET
Figure 5.1-1 Functional Block Diagram