SONIX SN8P2743 Series User manual

SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 1 Version 2.0
SN8P2743 Series
USER’S MANUAL
Version 2.0
SN8P2743
SN8P2742
SN8P27411
S
SO ON Ni iX X 8 8- -B Bi it t M Mi ic cr ro o- -C Co on nt tr ro ol ll le er r
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.

SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 2 Version 2.0
AMENDENT HISTORY
Version
Date
Description
VER 0.1
Oct. 2009
First issue.
VER 0.2
Mar. 2010
1. Fix typing errors of feature table.
2. Fix typing errors of bit definition of system registers.
3. Fix typing errors of I/O shared pin table.
4. Add P0 application notices.
5. Modify P0.1 to write only type.
6. Modify TC0 pulse width table.
7. Add TC0ENB control notice in comparator 1 special function.
8. Modify OP-amp pin definition.
9. Add development tools description.
10. Modify electrical characteristic section.
VER 0.3
Apr. 2010
1. Modify the pin assignments of SN8P2742P and SN8P2742S.
2. Modify PROGRAMMING PIN MAPPING table for SN8P2742P and SN8P2742S.
3. Modify DEVELOPMENT TOOL for SN8P2742.
VER 0.4
Jun. 2010
1. Modify EV-Kit version from “A”to “V1.0”.
2. Modify EV2740 EV-KIT schematic / outline.
3. Modify DEVELOPMENT TOOL chapter.
VER 1.0
May. 2011
1. Version update.
2. Modify “DEVELOPMENT TOOL” description
3. Modify “Chapter 16.3 CHARACTERISTIC GRAPHS”
VER 1.1
May. 2011
1. Modify “Chapter 10.4 COMPARATOR MODE REGISTER” CMDB0 register bit3
CM1D3 >> CM0D3.
2. Modify “Chapter 13.1 OVERVIEW” description : It is necessary to set P4 as input
mode with pull-up resistor by program >> It is necessary to set P4 as input mode
without pull-up resistor by program
VER 1.2
Sep. 2011
1. Add SN8P2741 pin assignment and modify some Chapters
VER 1.3
Dec. 2011
1. Delete SN8P2741 pin assignment and the others.
2. Add SN8P27411 pin assignment and the others.
VER 1.4
May. 2012
1. Modify SN8P27411 pin assignment.
VER 1.5
Oct. 2012
Modify SN8P27411 pin assignment.
VER 1.6
Nov. 2012
Modify “Electrical Characteristic”with “OP AMP CHARACTERISTIC”.
VER 1.7
Jun. 2013
Modify Package Information: SK-DIP24 content.
VER 1.8
Aug. 2013
1. Modify “Electrical Characteristic”with “OP AMP CHARACTERISTIC”with offset range.
2. Modify “ANALOG COMPARATOR 0~2”chapters description and others.
VER 1.9
Jul. 2015
Add “To support MUL / DAA instruction”description.
VER 2.0
Mar. 2016
Modify operating temperature from 0~70℃to -20~70℃and others.

SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 3 Version 2.0
Table of Content
AMENDENT HISTORY.................................................................................................................................................................2
1
1
1PRODUCT OVERVIEW .........................................................................................................................................................6
1.1 FEATURES.......................................................................................................................................................................6
1.2 SYSTEM BLOCK DIAGRAM .........................................................................................................................................7
1.3 PIN ASSIGNMENT ..........................................................................................................................................................7
1.4 PIN DESCRIPTIONS........................................................................................................................................................8
1.5 PIN CIRCUIT DIAGRAMS..............................................................................................................................................9
2
2
2CENTRAL PROCESSOR UNIT (CPU)...............................................................................................................................12
2.1 PROGRAM MEMORY (ROM) ......................................................................................................................................12
2.1.1 RESET VECTOR (0000H)....................................................................................................................................13
2.1.2 INTERRUPT VECTOR (0008H) ..........................................................................................................................14
2.1.3 LOOK-UP TABLE DESCRIPTION .....................................................................................................................16
2.1.4 JUMP TABLE DESCRIPTION.............................................................................................................................18
2.1.5 CHECKSUM CALCULATION ............................................................................................................................20
2.2 DATA MEMORY (RAM)...............................................................................................................................................21
2.2.1 SYSTEM REGISTER............................................................................................................................................21
2.2.1.1 SYSTEM REGISTER TABLE .........................................................................................................................21
2.2.1.2 SYSTEM REGISTER DESCRIPTION ............................................................................................................21
2.2.1.3 BIT DEFINITION of SYSTEM REGISTER....................................................................................................22
2.2.2 ACCUMULATOR.................................................................................................................................................24
2.2.3 PROGRAM FLAG ................................................................................................................................................25
2.2.4 PROGRAM COUNTER........................................................................................................................................26
2.2.5 H, L REGISTERS..................................................................................................................................................29
2.2.6 Y, Z REGISTERS..................................................................................................................................................30
2.2.7 R REGISTER.........................................................................................................................................................30
2.3 ADDRESSING MODE ...................................................................................................................................................31
2.3.1 IMMEDIATE ADDRESSING MODE..................................................................................................................31
2.3.2 DIRECTLY ADDRESSING MODE.....................................................................................................................31
2.3.3 INDIRECTLY ADDRESSING MODE.................................................................................................................31
2.4 STACK OPERATION.....................................................................................................................................................32
2.4.1 OVERVIEW ..........................................................................................................................................................32
2.4.2 STACK REGISTERS ............................................................................................................................................33
2.4.3 STACK OPERATION EXAMPLE .......................................................................................................................34
2.5 CODE OPTION TABLE .................................................................................................................................................35
2.5.1 Fcpu code option....................................................................................................................................................35
2.5.2 Reset_Pin code option............................................................................................................................................35
2.5.3 Security code option...............................................................................................................................................35
3
3
3RESET......................................................................................................................................................................................36
3.1 OVERVIEW....................................................................................................................................................................36
3.2 POWER ON RESET........................................................................................................................................................37
3.3 WATCHDOG RESET.....................................................................................................................................................37
3.4 BROWN OUT RESET ....................................................................................................................................................37
3.5 THE SYSTEM OPERATING VOLTAGE......................................................................................................................38
3.6 LOW VOLTAGE DETECTOR (LVD) ...........................................................................................................................38
3.7 BROWN OUT RESET IMPROVEMENT ......................................................................................................................40
3.8 EXTERNAL RESET .......................................................................................................................................................41
3.9 EXTERNAL RESET CIRCUIT ......................................................................................................................................41
3.9.1 Simply RC Reset Circuit........................................................................................................................................41
3.9.2 Diode & RC Reset Circuit......................................................................................................................................42
3.9.3 Zener Diode Reset Circuit......................................................................................................................................42
3.9.4 Voltage Bias Reset Circuit.....................................................................................................................................43
3.9.5 External Reset IC ...................................................................................................................................................43
4
4
4SYSTEM CLOCK...................................................................................................................................................................44
4.1 OVERVIEW....................................................................................................................................................................44
4.2 FCPU (INSTRUCTION CYCLE).....................................................................................................................................44
4.3 SYSTEM HIGH-SPEED CLOCK...................................................................................................................................44
4.3.1 HIGH_CLK CODE OPTION ................................................................................................................................45
4.3.2 INTERNAL HIGH-SPEED OSCILLATOR RC TYPE (IHRC) ...........................................................................45

SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 4 Version 2.0
4.3.3 EXTERNAL HIGH-SPEED OSCILLATOR ........................................................................................................45
4.3.4 EXTERNAL OSCILLATOR APPLICATION CIRCUIT.....................................................................................45
4.4 SYSTEM LOW-SPEED CLOCK....................................................................................................................................46
4.5 OSCM REGISTER..........................................................................................................................................................47
4.6 SYSTEM CLOCK MEASUREMENT............................................................................................................................47
4.7 SYSTEM CLOCK TIMING............................................................................................................................................48
5
5
5SYSTEM OPERATION MODE............................................................................................................................................51
5.1 OVERVIEW....................................................................................................................................................................51
5.2 NORMAL MODE ...........................................................................................................................................................52
5.3 SLOW MODE .................................................................................................................................................................52
5.4 POWER DOWN MODE .................................................................................................................................................52
5.5 GREEN MODE ...............................................................................................................................................................53
5.6 OPERATING MODE CONTROL MACRO...................................................................................................................54
5.7 WAKEUP........................................................................................................................................................................55
5.7.1 OVERVIEW ..........................................................................................................................................................55
5.7.2 WAKEUP TIME....................................................................................................................................................55
5.7.3 P1W WAKEUP CONTROL REGISTER..............................................................................................................56
6
6
6INTERRUPT...........................................................................................................................................................................57
6.1 OVERVIEW....................................................................................................................................................................57
6.2 INTEN INTERRUPT ENABLE REGISTER ..................................................................................................................58
6.3 INTRQ INTERRUPT REQUEST REGISTER................................................................................................................59
6.4 GIE GLOBAL INTERRUPT OPERATION....................................................................................................................60
6.5 PUSH, POP ROUTINE....................................................................................................................................................61
6.6 EXTERNAL INTERRUPT OPERATION (INT0)..........................................................................................................62
6.7 T0 INTERRUPT OPERATION.......................................................................................................................................63
6.8 TC0 INTERRUPT OPERATION....................................................................................................................................64
6.9 ADC INTERRUPT OPERATION...................................................................................................................................65
6.10 COMPARATOR INTERRUPT OPERATION (CMP0~CMP2) .....................................................................................66
6.11 MULTI-INTERRUPT OPERATION..............................................................................................................................67
7
7
7I/O PORT.................................................................................................................................................................................68
7.1 OVERVIEW....................................................................................................................................................................68
7.2 I/O PORT MODE ............................................................................................................................................................69
7.3 I/O PULL UP REGISTER ...............................................................................................................................................70
7.4 I/O PORT DATA REGISTER.........................................................................................................................................71
7.5 PORT 4ADC SHARE PIN..............................................................................................................................................72
8
8
8TIMERS...................................................................................................................................................................................75
8.1 WATCHDOG TIMER.....................................................................................................................................................75
8.2 T0 8-BIT BASIC TIMER ................................................................................................................................................77
8.2.1 OVERVIEW ..........................................................................................................................................................77
8.2.2 T0 TIMER OPERATION ......................................................................................................................................77
8.2.3 T0M MODE REGISTER.......................................................................................................................................78
8.2.4 T0C COUNTING REGISTER...............................................................................................................................78
8.2.5 T0 TIMER OPERATION EXPLAME...................................................................................................................79
8.3 TC0 8-BIT TIMER/COUNTER ......................................................................................................................................80
8.3.1 OVERVIEW ..........................................................................................................................................................80
8.3.2 TC0 TIMER OPERATION....................................................................................................................................81
8.3.3 PULSE WIDTH MODULATION (PWM) ............................................................................................................82
8.3.4 TC0 Pulse Generator Function...............................................................................................................................83
8.3.5 TC0M MODE REGISTER....................................................................................................................................85
8.3.6 TC0C COUNTING REGISTER............................................................................................................................85
8.3.7 TC0R AUTO-RELOAD REGISTER ....................................................................................................................86
8.3.8 TC0D PWM DUTY REGISTER...........................................................................................................................86
8.3.9 TC0 TIMER OPERATION EXPLAME................................................................................................................87
9
9
9ANALOG COMPARAOTR 0................................................................................................................................................89
9.1 OVERVIEW....................................................................................................................................................................89
9.2 NORMAL COMPARATOR MODE...............................................................................................................................90
9.3 COMPARATOR 0SPECIAL FUCNITON.....................................................................................................................92
9.4 COMPARATOR MODE REGISTER.............................................................................................................................93
9.5 COMPARATOR APPLICATION NOTICE ...................................................................................................................93
9.6 COMPARATOR 0OPERATION EXPLAME................................................................................................................94
1
1
10
0
0ANALOG COMPARAOTR 1...........................................................................................................................................95
10.1 OVERVIEW....................................................................................................................................................................95

SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 5 Version 2.0
10.2 NORMAL COMPARATOR MODE...............................................................................................................................96
10.3 COMPARATOR 1SPECIAL FUCNITON.....................................................................................................................98
10.4 COMPARATOR MODE REGISTER.............................................................................................................................99
10.5 COMPARATOR APPLICATION NOTICE .................................................................................................................100
10.6 COMPARATOR 1OPERATION EXPLAME..............................................................................................................100
1
1
11
1
1ANALOG COMPARAOTR 2.........................................................................................................................................101
11.1 OVERVIEW..................................................................................................................................................................101
11.2 NORMAL COMPARATOR MODE.............................................................................................................................102
11.3 COMPARATOR 2SPECIAL FUCNITON...................................................................................................................104
11.4 COMPARATOR MODE REGISTER...........................................................................................................................105
11.5 COMPARATOR APPLICATION NOTICE .................................................................................................................106
11.6 COMPARATOR 2OPERATION EXPLAME..............................................................................................................106
1
1
12
2
22K/4K BUZZER GENERATOR.....................................................................................................................................107
12.1 OVERVIEW..................................................................................................................................................................107
12.2 BZM REGISTER...........................................................................................................................................................107
1
1
13
3
38 CHANNEL ANALOG TO DIGITAL CONVERTER (ADC)...................................................................................108
13.1 OVERVIEW..................................................................................................................................................................108
13.2 ADC MODE REGISTER ..............................................................................................................................................109
13.3 ADC DATA BUFFER REGISTERS.............................................................................................................................110
13.4 ADC OPERATION DESCRIPTION AND NOTIC ......................................................................................................111
13.4.1 ADC SIGNAL FORMAT....................................................................................................................................111
13.4.2 ADC CONVERTING TIME................................................................................................................................111
13.4.3 ADC PIN CONFIGURATION ............................................................................................................................112
13.5 ADC OPERATION EXAMLPE....................................................................................................................................113
13.6 ADC APPLICATION CIRCUIT ........................................................................................................................................115
1
1
14
4
4RAIL TO RAIL OP AMPLIFER....................................................................................................................................116
14.1 OVERVIEW..................................................................................................................................................................116
14.2 OP AMP REGISTER.....................................................................................................................................................116
1
1
15
5
5INSTRUCTION TABLE .................................................................................................................................................117
1
1
16
6
6ELECTRICAL CHARACTERISTIC............................................................................................................................118
16.1 ABSOLUTE MAXIMUM RATING.............................................................................................................................118
16.2 ELECTRICAL CHARACTERISTIC............................................................................................................................118
16.3 CHARACTERISTIC GRAPHS.....................................................................................................................................120
1
1
17
7
7DEVELOPMENT TOOL................................................................................................................................................121
17.1 SN8P2740 EV-KIT .........................................................................................................................................................121
17.2 ICE AND EV-KIT APPLICATION NOTIC...................................................................................................................123
1
1
18
8
8OTP PROGRAMMING PIN...........................................................................................................................................125
18.1 WRITER TRANSITION BOARD SOCKET PIN ASSIGNMENT...............................................................................125
18.2 PROGRAMMING PIN MAPPING:..............................................................................................................................126
1
1
19
9
9MARKING DEFINITION...............................................................................................................................................127
19.1 INTRODUCTION.........................................................................................................................................................127
19.2 MARKING INDETIFICATION SYSTEM...................................................................................................................127
19.3 MARKING EXAMPLE.................................................................................................................................................128
19.4 DATECODE SYSTEM.................................................................................................................................................129
2
2
20
0
0PACKAGE INFORMATION .........................................................................................................................................130
20.1 SK-DIP 24 PIN ..............................................................................................................................................................130
20.2 SOP 24 PIN....................................................................................................................................................................131
20.3 P-DIP 20 PIN.................................................................................................................................................................132
20.4 SOP 20 PIN....................................................................................................................................................................133
20.5 P-DIP 16 PIN.................................................................................................................................................................134
20.6 SOP 16 PIN....................................................................................................................................................................135

SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 6 Version 2.0
1
1
1 PRODUCT OVERVIEW
1.1 FEATURES
Features Selection Table
CHIP
ROM
RAM
Stack
Timer
PWM
Pulse
Generator
Buzzer
Ext.
Int
I/O
ADC
OP-
amp
Comp-
arator
Package
T0
TC0
SN8P2743
4K*16
128*8
8
V
V
1
1
1
1
22
8-ch
1
3
SKDIP24
SOP24
SN8P2742
4K*16
128*8
8
V
V
1
1
1
-
18
6-ch
1
3
PDIP20
SOP20
SN8P27411
4K*16
128*8
8
V
V
1
1
1
-
14
6-ch
1
3
PDIP16
SOP16

Memory configuration

One 8-bit basic timer. (T0).
ROM size: 4K * 16 bits.

One 8-bit timer with PWM and pulse generator
RAM size: 128 * 8 bits.
(TC0).

One 2K/4K programmable buzzer output.

8 levels stack buffer.

8-channel 12-bit SAR ADC.

7 interrupt sources

1-set rail-to-rail OP-amp.
6 internal interrupts: T0, TC0, ADC, CM0, CM1, CM2

3-set comparators.
1 external interrupt: INT0

On chip watchdog timer and clock source is
Internal low clock RC type (16KHz @3V, 32KHz

I/O pin configuration
@5V).
Bi-directional: P0, P1, P4.
Wakeup: P0, P1 level change.

4 system clocks
Pull-up resisters: P0, P1, P4.
External high clock: RC type up to 10 MHz
Op-amp/Comparator pins: P1, P4.
External high clock: Crystal type up to 16 MHz
ADC input pin: P4.0~P4.7.
Internal high clock: RC type 16MHz
Internal low clock: RC type 16KHz(3V), 32KHz(5V)

Fcpu (Instruction cycle)
Fcpu = Fosc/4, Fosc/8, Fosc/16.

4 operating modes
Normal mode: Both high and low clock active

3-Level LVD
Slow mode: Low clock only.
2.0V/2.4V/3.6V
Sleep mode: Both high and low clock stop
Green mode: Periodical wakeup by timer

Powerful instructions
Instruction‟s length is one word.

Package (Chip form support)
Most of instructions are one cycle only.
SKDIP 24 pin
All ROM area JMP/CALL instruction.
PDIP 20 pin
All ROM area lookup table function (MOVC).
SOP 24 pin
To support MUL / DAA instruction
SOP 20 pin
PDIP 16 pin
SOP 16 pin

SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 7 Version 2.0
1.2 SYSTEM BLOCK DIAGRAM
INTERRUPT
CONTROL
EXTERNAL
HIGH OSC.
ACC
INTERNAL
LOW RC
TIMING GENERATOR
RAM
SYSTEM REGISTERS
3-Level LVD
(Low Voltage Detector)
WATCHDOG TIMER
TIMER & COUNTER
P0 P1
PWM & Pulse Output
ALU
PC
FLAGS
IR OTP
ROM
P4
INTERNAL HIGH
RC 16MHz
Comparator 0
Comparator 1
12-bit ADC AIN0~AIN7
Comparator 2
OPA
CM0N, CM0P, CM0O
OPN, OPP, OPO
PWM0
Buzzer BZ
CM2N, CM2P. CM2O
CM1N, CM1P, CM1O
1.3 PIN ASSIGNMENT
SN8P2743K (SKDIP 24 pin)
SN8P2743S (SOP 24 pin)
VSS
1
U
24
VDD
XIN/P0.6
2
23
P4.7/AIN7
XOUT/P0.5/BZ
3
22
P4.6/AIN6
RST/VPP/P0.4
4
21
P4.5/AIN5
P0.0/INT0
5
20
P4.4/AIN4
P0.1/PWM0
6
19
P4.3/AIN3/CM0O
P0.2/CM0P
7
18
P4.2/AIN2/CM1O
P0.3/CM0N
8
17
P4.1/AIN1/CM2O
P1.6/CM1P
9
16
P4.0/AIN0/AVREFH
P1.5/CM1N
10
15
P1.0/OPN
P1.4/CM2P
11
14
P1.1/OPP
P1.3/CM2N
12
13
P1.2/OPO
SN8P2742P (DIP 20 pin)
SN8P2742S (SOP 20 pin)
VSS
1
U
20
VDD
XIN/P0.6
2
19
P4.5/AIN5
XOUT/P0.5/BZ
3
18
P4.4/AIN4
RST/VPP/P0.4/ P0.1/PWM0
4
17
P4.3/AIN3/CM0O
P0.2/CM0P
5
16
P4.2/AIN2/CM1O
P0.3/CM0N
6
15
P4.1/AIN1/CM2O
P1.6/CM1P
7
14
P4.0/AIN0/AVREFH
P1.5/CM1N
8
13
P1.0/OPN
P1.4/CM2P
9
12
P1.1/OPP
P1.3/CM2N
10
11
P1.2/OPO

SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 8 Version 2.0
SN8P27411P (DIP 16 pin)
VDD
1
U
16
P4.7/AIN7
XOUT/P0.5/BZ
2
15
P4.6/AIN6
RST/VPP/P0.4/ P0.1/PWM0
3
14
P4.4/AIN4
P0.2/CM0P
4
13
VSS
P0.3/CM0N
5
12
P4.2/AIN2/CM1O
P1.5/CM1N
6
11
P4.1/AIN1/CM2O
P1.3/CM2N
7
10
P4.0/AIN0/AVREFH
P4.3/OPO
8
9
P1.0/OPN
OPP (OPA’s positive pin) pin connects to ground.
SN8P27411S (SOP 16 pin)
VDD
1
U
16
VSS
XOUT/P0.5/BZ
2
15
P4.7/AIN7
RST/VPP/P0.4/ P0.1/PWM0
3
14
P4.6/AIN6
P0.2/CM0P
4
13
P4.4/AIN4
P0.3/CM0N
5
12
P4.2/AIN2/CM1O
P1.5/CM1N
6
11
P4.1/AIN1/CM2O
P1.3/CM2N
7
10
P4.0/AIN0/AVREFH
P4.3/OPO
8
9
P1.0/OPN
OPP (OPA’s positive pin) pin connects to ground.
1.4 PIN DESCRIPTIONS
PIN NAME
TYPE
DESCRIPTION
VDD, VSS
P
Power supply input pins for digital and analog circuit.
P0.4/RST/VPP
I, P
RST: System external reset input pin. Schmitt trigger structure, active “low”, normal stay
to “high”.
VPP: OTP 12.3V power input pin in programming mode.
P0.4: Input only pin with Schmitt trigger structure and no pull-up resistor. Level change
wake-up.
XIN/P0.6
I/O
XIN: Oscillator input pin while external oscillator enable (crystal and RC).
P0.6: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Level change wake-up.
XOUT/P0.5/BZ
I/O
XOUT: Oscillator output pin while external crystal enable.
P0.5: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Level change wake-up.
BZ: 2K/4K programmable buzzer output pin.
P0.0/INT0
I/O
P0.0: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
INT0: External interrupt 0 input pin.
P0.1/PWM0
I/O
P0.1: Output pin with open-drain structure.
PWM0: PWM output pin and pulse output pin.
P0.2/CM0P
I/O
P0.2: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Level change wake-up.
CM0P: The positive input pin of comparator.
P0.2/CM0N
I/O
P0.3: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Level change wake-up.
CM0N: The negative input pin of comparator.
P1.0/OPN
I/O
P1.0: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Level change wake-up.
OPN: The negative input pin of OP amp.
P1.1/OPP
I/O
P1.1: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Level change wake-up.
OPP: The positive input pin of OP amp.
P1.2/OPO
I/O
P1.2: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Level change wake-up.
OPO: The output pin of OP amp.

SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 9 Version 2.0
P1.3/CM2N
I/O
P1.3: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Level change wake-up.
CM2N: The negative input pin of comparator.
P1.4/CM2P
I/O
P1.4: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Level change wake-up.
CM2P: The positive input pin of comparator.
P1.5/CM1N
I/O
P1.5: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Level change wake-up.
CM1N: The negative input pin of comparator.
P1.6/CM1P
I/O
P1.6: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Level change wake-up.
CM1P: The positive input pin of comparator.
P4.0/AIN0/AVREFH
I/O
P4.0: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
AIN0: ADC analog input pin.
AVREFH: ADC reference high voltage input pin.
P4.1/AIN1/CM2O
I/O
P4.1: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
AIN1: ADC analog input pin.
CM2O: The output pin of comparator.
P4.2/AIN2/CM1O
I/O
P4.2: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
AIN2: ADC analog input pin.
CM1O: The output pin of comparator.
P4.3/AIN3/CM0O
I/O
P4.3: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
AIN3: ADC analog input pin.
CM0O: The output pin of comparator.
P4.4/AIN4
I/O
P4.4: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
AIN4: ADC analog input pin.
P4.5/AIN5
I/O
P4.5: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
AIN5: ADC analog input pin.
P4.6/AIN6
I/O
P4.6: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
AIN6: ADC analog input pin.
P4.7/AIN7
I/O
P4.7: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
AIN7: ADC analog input pin. Refer to ADC section.
1.5 PIN CIRCUIT DIAGRAMS
Reset shared pin structure:
Pin
Ext. Reset
Code Option
I/O Input Bus
Reset
Oscillator shared pin structure:
Pull-Up
Resistor
Output
Latch
Pin
PnUR
PnM
I/O Input Bus
I/O Output Bus
PnM
High_Clk
Code Option
Oscillator Driver
GPIO structure:

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ADC, OP-amp, Comparator 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 10 Version 2.0
Pull-Up
Resistor
Output
Latch
Pin
PnUR
PnM
I/O Input Bus
I/O Output Bus
PnM
P0.1: Open-drain shared pin, output only I/O:
Pin Open-Drain
Control I/O Bus
R
VCC INSIDEOUTSIDE

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ADC, OP-amp, Comparator 8-Bit Micro-Controller
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ADC shared pin with reference high voltage structure:
AVREFH
AVREFH
Pin
GCHS
P4CON
ADC Input
Pull-Up
Resistor
Output
Latch
PnUR
PnM
I/O Input Bus
I/O Output Bus
PnM
ADENB
ADC shared pin structure:
Pin
ADENB,
GCHS
P4CON
ADC Input
Pull-Up
Resistor
Output
Latch
PnUR
PnM
I/O Input Bus
I/O Output Bus
PnM
OP-amp shared pins structure:
Pin
OPnEN
Op-amp Terminal
Pull-Up
Resistor
Output
Latch
PnUR
PnM
I/O Input Bus
I/O Output Bus
PnM
Comparator shared pins structure:
Comparator Negative Pin:
Pin
CMnEN
Comparator
Negative Input
Pull-Up
Resistor
Output
Latch
PnUR
PnM
I/O Input Bus
I/O Output Bus
PnM
Comparator Positive Pin:
Pin
CMnEN
Comparator
Positive Input
Pull-Up
Resistor
Output
Latch
PnUR
PnM
I/O Input Bus
I/O Output Bus
PnM
CMnREF
Comparator Output Pin:
Pin
CMnEN
Comparator
Output
Pull-Up
Resistor
Output
Latch
PnUR
PnM
I/O Input Bus
I/O Output Bus
PnM
CMnOEN

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2
2
2 CENTRAL PROCESSOR UNIT (CPU)
2.1 PROGRAM MEMORY (ROM)
4K words ROM
ROM
0000H
Reset vector
User reset vector
Jump to user start address
0001H
General purpose area
.
.
0007H
0008H
Interrupt vector
User interrupt vector
0009H
General purpose area
User program
.
.
000FH
0010H
0011H
.
.
.
.
.
0FFCH
End of user program
0FFDH
Reserved
0FFEH
0FFFH
The ROM includes Reset vector, Interrupt vector, General purpose area and Reserved area. The Reset vector is
program beginning address. The Interrupt vector is the head of interrupt service routine when any interrupt occurring.
The General purpose area is main program area including main loop, sub-routines and data table.

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2.1.1 RESET VECTOR (0000H)
A one-word vector address area is used to execute system reset.
Power On Reset (NT0=1, NPD=0).
Watchdog Reset (NT0=0, NPD=0).
External Reset (NT0=1, NPD=1).
After power on reset, external reset or watchdog timer overflow reset, then the chip will restart the program from
address 0000h and all system registers will be set as default values. It is easy to know reset status from NT0, NPD
flags of PFLAG register. The following example shows the way to define the reset vector in the program memory.
Example: Defining Reset Vector
ORG
0
; 0000H
JMP
START
; Jump to user program address.
…
ORG
10H
START:
; 0010H, The head of user program.
…
; User program
…
ENDP
; End of program

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2.1.2 INTERRUPT VECTOR (0008H)
A 1-word vector address area is used to execute interrupt request. If any interrupt service executes, the program
counter (PC) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt.
Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the
program memory.
Note: ”PUSH”, “POP”instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is a
unique buffer and only one level.
Example: Defining Interrupt Vector. The interrupt service routine is following ORG 8.
.CODE
ORG
0
; 0000H
JMP
START
; Jump to user program address.
…
ORG
8
; Interrupt vector.
PUSH
; Save ACC and PFLAG register to buffers.
…
…
POP
; Load ACC and PFLAG register from buffers.
RETI
; End of interrupt service routine
…
START:
; The head of user program.
…
; User program
…
JMP
START
; End of user program
…
ENDP
; End of program

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Example: Defining Interrupt Vector. The interrupt service routine is following user program.
.CODE
ORG
0
; 0000H
JMP
START
; Jump to user program address.
…
ORG
8
; Interrupt vector.
JMP
MY_IRQ
; 0008H, Jump to interrupt service routine address.
ORG
10H
START:
; 0010H, The head of user program.
…
; User program.
…
…
JMP
START
; End of user program.
…
MY_IRQ:
;The head of interrupt service routine.
PUSH
; Save ACC and PFLAG register to buffers.
…
…
POP
; Load ACC and PFLAG register from buffers.
RETI
; End of interrupt service routine.
…
ENDP
; End of program.
Note: It is easy to understand the rules of SONIX program from demo programs given above. These
points are as following:
1. The address 0000H is a “JMP”instruction to make the program starts from the beginning.
2. The address 0008H is interrupt vector.
3. User’s program is a loop routine for main purpose application.

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2.1.3 LOOK-UP TABLE DESCRIPTION
In the ROM‟s data lookup function, Y register is pointed to middle byte address (bit 8~bit 15) and Z register is pointed
to low byte address (bit 0~bit 7) of ROM. After MOVC instruction executed, the low-byte data will be stored in ACC and
high-byte data stored in R register.
Example: To look up the ROM data located “TABLE1”.
B0MOV
Y, #TABLE1$M
; To set lookup table1‟s middle address
B0MOV
Z, #TABLE1$L
; To set lookup table1‟s low address.
MOVC
; To lookup data, R = 00H, ACC = 35H
; Increment the index address for next address.
INCMS
Z
; Z+1
JMP
@F
; Z is not overflow.
INCMS
Y
; Z overflow (FFH 00), Y=Y+1
NOP
;
;
@@:
MOVC
; To lookup data, R = 51H, ACC = 05H.
…
;
TABLE1:
DW
0035H
; To define a word (16 bits) data.
DW
5105H
DW
2012H
…
Note: The Y register will not increase automatically when Z register crosses boundary from 0xFF to
0x00. Therefore, user must be take care such situation to avoid look-up table errors. If Z register is
overflow, Y register must be added one. The following INC_YZ macro shows a simple method to process
Y and Z registers automatically.
Example: INC_YZ macro.
INC_YZ
MACRO
INCMS
Z
; Z+1
JMP
@F
; Not overflow
INCMS
Y
; Y+1
NOP
; Not overflow
@@:
ENDM

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Example: Modify above example by “INC_YZ”macro.
B0MOV
Y, #TABLE1$M
; To set lookup table1‟s middle address
B0MOV
Z, #TABLE1$L
; To set lookup table1‟s low address.
MOVC
; To lookup data, R = 00H, ACC = 35H
INC_YZ
; Increment the index address for next address.
;
@@:
MOVC
; To lookup data, R = 51H, ACC = 05H.
…
;
TABLE1:
DW
0035H
; To define a word (16 bits) data.
DW
5105H
DW
2012H
…
The other example of look-up table is to add Y or Z index register by accumulator. Please be careful if “carry” happen.
Example: Increase Y and Z register by B0ADD/ADD instruction.
B0MOV
Y, #TABLE1$M
; To set lookup table‟s middle address.
B0MOV
Z, #TABLE1$L
; To set lookup table‟s low address.
B0MOV
A, BUF
; Z = Z + BUF.
B0ADD
Z, A
B0BTS1
FC
; Check the carry flag.
JMP
GETDATA
; FC = 0
INCMS
Y
; FC = 1. Y+1.
NOP
GETDATA:
;
MOVC
; To lookup data. If BUF = 0, data is 0x0035
; If BUF = 1, data is 0x5105
; If BUF = 2, data is 0x2012
…
TABLE1:
DW
0035H
; To define a word (16 bits) data.
DW
5105H
DW
2012H
…

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2.1.4 JUMP TABLE DESCRIPTION
The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC
value to get one new PCL. If PCL is overflow after PCL+ACC, PCH adds one automatically. The new program counter
(PC) points to a series jump instructions as a listing table. It is easy to make a multi-jump program depends on the
value of the accumulator (A).
Note: PCH only support PC up counting result and doesn’t support PC down counting. When PCL is
carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL–ACC, PCH keeps value and
not change.
Example: Jump table.
ORG
0X0100
; The jump table is from the head of the ROM boundary
B0ADD
PCL, A
; PCL = PCL + ACC, PCH + 1 when PCL overflow occurs.
JMP
A0POINT
; ACC = 0, jump to A0POINT
JMP
A1POINT
; ACC = 1, jump to A1POINT
JMP
A2POINT
; ACC = 2, jump to A2POINT
JMP
A3POINT
; ACC = 3, jump to A3POINT
SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump
table to the right position automatically. The side effect of this macro maybe wastes some ROM size.
Example: If “jump table” crosses over ROM boundary will cause errors.
@JMP_A
MACRO
VAL
IF
(($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00)
JMP
($ | 0XFF)
ORG
($ | 0XFF)
ENDIF
B0ADD
PCL, A
ENDM
Note: “VAL”is the number of the jump table listing number.
Example: “@JMP_A”application in SONIX macro file called “MACRO3.H”.
B0MOV
A, BUF0
; “BUF0”is from 0 to 4.
@JMP_A
5
; The number of the jump table listing is five.
JMP
A0POINT
; ACC = 0, jump to A0POINT
JMP
A1POINT
; ACC = 1, jump to A1POINT
JMP
A2POINT
; ACC = 2, jump to A2POINT
JMP
A3POINT
; ACC = 3, jump to A3POINT
JMP
A4POINT
; ACC = 4, jump to A4POINT

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If the jump table position is across a ROM boundary (0x00FF~0x0100), the “@JMP_A”macro will adjust the jump table
routine begin from next RAM boundary (0x0100).
Example: “@JMP_A”operation.
; Before compiling program.
ROM address
B0MOV
A, BUF0
; “BUF0”is from 0 to 4.
@JMP_A
5
; The number of the jump table listing is five.
0X00FD
JMP
A0POINT
; ACC = 0, jump to A0POINT
0X00FE
JMP
A1POINT
; ACC = 1, jump to A1POINT
0X00FF
JMP
A2POINT
; ACC = 2, jump to A2POINT
0X0100
JMP
A3POINT
; ACC = 3, jump to A3POINT
0X0101
JMP
A4POINT
; ACC = 4, jump to A4POINT
; After compiling program.
ROM address
B0MOV
A, BUF0
; “BUF0”is from 0 to 4.
@JMP_A
5
; The number of the jump table listing is five.
0X0100
JMP
A0POINT
; ACC = 0, jump to A0POINT
0X0101
JMP
A1POINT
; ACC = 1, jump to A1POINT
0X0102
JMP
A2POINT
; ACC = 2, jump to A2POINT
0X0103
JMP
A3POINT
; ACC = 3, jump to A3POINT
0X0104
JMP
A4POINT
; ACC = 4, jump to A4POINT

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2.1.5 CHECKSUM CALCULATION
The last ROM address are reserved area. User should avoid these addresses (last address) when calculate the
Checksum value.
Example: The demo program shows how to calculated Checksum from 00H to the end of user’s code.
MOV
A,#END_USER_CODE$L
B0MOV
END_ADDR1, A
; Save low end address to end_addr1
MOV
A,#END_USER_CODE$M
B0MOV
END_ADDR2, A
; Save middle end address to end_addr2
CLR
Y
; Set Y to 00H
CLR
Z
; Set Z to 00H
@@:
MOVC
B0BSET
FC
; Clear C flag
ADD
DATA1, A
; Add A to Data1
MOV
A, R
ADC
DATA2, A
; Add R to Data2
JMP
END_CHECK
; Check if the YZ address = the end of code
AAA:
INCMS
Z
; Z=Z+1
JMP
@B
; If Z != 00H calculate to next address
JMP
Y_ADD_1
; If Z = 00H increase Y
END_CHECK:
MOV
A, END_ADDR1
CMPRS
A, Z
; Check if Z = low end address
JMP
AAA
; If Not jump to checksum calculate
MOV
A, END_ADDR2
CMPRS
A, Y
; If Yes, check if Y = middle end address
JMP
AAA
; If Not jump to checksum calculate
JMP
CHECKSUM_END
; If Yes checksum calculated is done.
Y_ADD_1:
INCMS
Y
; Increase Y
NOP
JMP
@B
; Jump to checksum calculate
CHECKSUM_END:
…
…
END_USER_CODE:
; Label of program end