Abov A96G140 User manual

Global Top Smart MCU Innovator
www.abov.co.kr
A96G140/A96G148
User’s Manual
CMOS Single Chip 8-bit MCU with 12-bit ADC
General Purpose Microcontroller
Version 1.13
Introduction
This user’s manual targets application developers who use A96G140/A96G148 for their specific
needs. It provides complete information of how to use A96G140/A96G148 device. Standard functions
and blocks including corresponding register information of A96G140/A96G148 are introduced in each
chapter, while instruction set is in Appendix.
A96G140/A96G148 is based on M8051 core, and provides standard features of 8051 such as 8-bit
ALU, PC, 8-bit registers, timers and counters, serial data communication, PSW, DPTR, SP, 8-bit data
bus and 2x16-bit address bus, and 8/11/16-bit operations.
In addition, this device incorporates followings to offer highly flexible and cost effective solutions:
64Kbytes of FLASH, 256bytes of IRAM, 2304bytes of XRAM, general purpose I/O, basic interval timer,
watchdog timer, 8/16-bit timer/counter, 16-bit PPG output, 8-bit PWM output, 16-bit PWM output,
watch timer, buzzer driving port, USI, 12-bit A/D converter, on-chip POR, LVR, LVI, on-chip oscillator
and clock circuitry.
As a field proven best seller, A96G140/A96G148 has been sold more than 3 billion units up to now,
and introduces rich features such as excellent noise immunity, code optimization, cost effectiveness,
and so on.
Reference document
A96G140/A96G148 programming tools and manuals released by ABOV: They are available
at ABOV website, www.abov.co.kr/e_main.php.
SDK-51 User’s guide (System Design Kit) released by Intel in 1982: It contains all of
components of a single-board computer based on Intel’s 8051 single-chip microcomputer
Information on Mentor Graphics 8051 microcontroller: The technical document is provided at
Mentorwebsite: https://www.mentor.com/products/ip/peripheral/microcontroller/

Contents A96G140/A96G148 User’s manual
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Contents
1Description..................................................................................................................................................... 21
1.1 Device overview ......................................................................................................................... 21
1.2 A96G140/A96G148 block diagram.................................................................................... 22
2Pinouts and pin description................................................................................................................... 24
2.1 Pinouts............................................................................................................................................ 24
2.2 Pin description............................................................................................................................ 28
3Port structures.............................................................................................................................................. 33
4Memory organization................................................................................................................................ 35
4.1 Program memory ...................................................................................................................... 35
4.2 Data memory............................................................................................................................... 36
4.3 External data memory ............................................................................................................. 38
4.4 SFR map......................................................................................................................................... 39
4.4.1 SFR map summary.................................................................................................................... 39
4.4.2 SFR map......................................................................................................................................... 41
4.4.3 Compiler compatible SFR ...................................................................................................... 46
5I/O ports ......................................................................................................................................................... 48
5.1 Port register ................................................................................................................................. 48
5.1.1 Data register (Px)....................................................................................................................... 48
5.1.2 Direction register (PxIO)......................................................................................................... 48
5.1.3 Pull-up register selection register (PxPU)....................................................................... 48
5.1.4 Open-drain Selection Register (PxOD) ............................................................................ 48
5.1.5 De-bounce Enable Register (PxDB)................................................................................... 48
5.1.6 Port Function Selection Register (PxFSR) ....................................................................... 48
5.1.7 Register Map ............................................................................................................................... 50
5.2 P0 port............................................................................................................................................ 51

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5.2.1 P0 port description................................................................................................................... 51
5.2.2 Register description for P0 ................................................................................................... 51
5.3 P1 port............................................................................................................................................ 54
5.3.1 P1 port description................................................................................................................... 54
5.3.2 Register description for P1 ................................................................................................... 54
5.4 P2 port............................................................................................................................................ 58
5.4.1 P2 port description................................................................................................................... 58
5.4.2 Register description for P2 ................................................................................................... 58
5.5 P3 port............................................................................................................................................ 60
5.5.1 P3 port description................................................................................................................... 60
5.5.2 Register description for P3 ................................................................................................... 60
5.6 P4 port............................................................................................................................................ 62
5.6.1 P4 port description................................................................................................................... 62
5.6.2 Register description for P4 ................................................................................................... 62
5.7 P5 port............................................................................................................................................ 64
5.7.1 P5 port description................................................................................................................... 64
5.7.2 Register description for P5 ................................................................................................... 64
6Interrupt controller..................................................................................................................................... 66
6.1 External interrupt....................................................................................................................... 67
6.2 Block diagram ............................................................................................................................. 68
6.3 Interrupt vector table............................................................................................................... 70
6.4 Interrupt sequence.................................................................................................................... 71
6.5 Effective timing after controlling interrupt bit............................................................. 72
6.6 Multi-interrupt ............................................................................................................................ 73
6.7 Interrupt enable accept timing ........................................................................................... 74
6.8 Interrupt service routine address ....................................................................................... 75

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6.9 Saving/restore general purpose registers ...................................................................... 75
6.10 Interrupt timing.......................................................................................................................... 76
6.11 Interrupt register overview.................................................................................................... 76
6.11.1 Interrupt Enable Register (IE, IE1, IE2, and IE3) ........................................................... 76
6.11.2 Interrupt Priority Register (IP and IP1) ............................................................................ 76
6.11.3 External Interrupt Flag Register (EIFLAG0 and EIFLAG1) ......................................... 77
6.11.4 External Interrupt Polarity Register (EIPOL0L, EIPOL0H, and EIPOL1) ............... 77
6.11.5 Register map ............................................................................................................................... 77
6.11.6 Interrupt register description............................................................................................... 77
7Clock generator ........................................................................................................................................... 84
7.1 Clock generator block diagram .......................................................................................... 84
7.2 Register map ............................................................................................................................... 85
7.3 Register description.................................................................................................................. 85
8Basic interval timer..................................................................................................................................... 88
8.1 BIT block diagram ..................................................................................................................... 88
8.2 BIT register map......................................................................................................................... 88
8.3 BIT register description........................................................................................................... 89
9Watchdog timer........................................................................................................................................... 90
9.1 WDT interrupt timing waveform ........................................................................................ 90
9.2 WDT block diagram ................................................................................................................. 91
9.3 Register map ............................................................................................................................... 91
9.4 Register description.................................................................................................................. 91
10 Watch timer ................................................................................................................................. 93
10.1 WT block diagram..................................................................................................................... 93
10.2 Register map ............................................................................................................................... 93
10.3 Watch timer register description........................................................................................ 94

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11 Timer 0/1/2/3/4/5 ..................................................................................................................... 96
11.1 Timer 0 ........................................................................................................................................... 96
11.1.1 8-bit timer/counter mode ..................................................................................................... 96
11.1.2 8-bit PWM mode....................................................................................................................... 98
11.1.3 8-bit capture mode ................................................................................................................100
11.1.4 Timer 0 block diagram..........................................................................................................102
11.1.5 Register map .............................................................................................................................102
11.1.6 Register description................................................................................................................102
11.2 Timer 1 .........................................................................................................................................104
11.2.1 16-bit timer/counter mode.................................................................................................104
11.2.2 16-bit capture mode..............................................................................................................107
11.2.3 16-bit PPG mode.....................................................................................................................108
11.2.4 16-bit timer 1 block diagram.............................................................................................111
11.2.5 Register map .............................................................................................................................111
11.2.6 Register description................................................................................................................111
11.3 Timer 2 .........................................................................................................................................114
11.3.1 16-bit timer/counter mode.................................................................................................115
11.3.2 16-bit capture mode..............................................................................................................117
11.3.3 16-bit PPG mode.....................................................................................................................119
11.3.4 16-bit timer 2 block diagram.............................................................................................121
11.3.5 Register map .............................................................................................................................121
11.3.6 Register description................................................................................................................121
11.4 Timer 3 .........................................................................................................................................124
11.4.1 16-bit timer/counter mode.................................................................................................124
11.4.2 16-bit capture mode..............................................................................................................126
11.4.3 16-bit PPG mode.....................................................................................................................128

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11.4.4 16-bit timer 3 block diagram.............................................................................................130
11.4.5 Register map .............................................................................................................................130
11.4.6 Register description................................................................................................................130
11.5 Timer 4 .........................................................................................................................................133
11.5.1 16-bit timer/counter mode.................................................................................................134
11.5.2 16-bit capture mode..............................................................................................................136
11.5.3 16-bit PPG mode.....................................................................................................................138
11.5.4 16-bit timer 4 block diagram.............................................................................................140
11.5.5 Register map .............................................................................................................................140
11.5.6 Register description................................................................................................................140
11.6 Timer 5 .........................................................................................................................................143
11.6.1 16-bit timer/counter mode.................................................................................................143
11.6.2 16-bit capture mode..............................................................................................................145
11.6.3 16-bit PPG mode.....................................................................................................................147
11.6.4 16-bit timer 5 block diagram.............................................................................................149
11.6.5 Register map .............................................................................................................................149
11.6.6 Register description................................................................................................................149
12 Buzzer driver..............................................................................................................................152
12.1 Buzzer driver block diagram ..............................................................................................152
12.2 Register map .............................................................................................................................152
12.3 Register description................................................................................................................153
13 12-bit ADC..................................................................................................................................154
13.1 Conversion timing...................................................................................................................154
13.2 Block diagram ...........................................................................................................................154
13.3 ADC operation..........................................................................................................................156
13.4 Register map .............................................................................................................................157

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13.5 Register description................................................................................................................157
14 USI (USART + SPI + I2C)......................................................................................................160
14.1 USIn UART mode.....................................................................................................................160
14.2 USIn UART block diagram...................................................................................................161
14.3 USIn clock generation ...........................................................................................................162
14.4 USIn external clock (SCKn)..................................................................................................163
14.5 USIn synchronous mode operation ................................................................................163
14.6 USIn UART data format ........................................................................................................163
14.7 USIn UART parity bit..............................................................................................................164
14.8 USIn UART transmitter..........................................................................................................165
14.8.1 USIn UART sending TX data...............................................................................................165
14.8.2 USIn UART transmitter flag and interrupt....................................................................165
14.8.3 USIn UART parity generator...............................................................................................166
14.8.4 USIn UART disabling transmitter......................................................................................166
14.9 USIn UART receiver.................................................................................................................166
14.9.1 USIn UART receiver RX data...............................................................................................166
14.9.2 USIn UART receiver flag and interrupt ..........................................................................167
14.9.3 USIn UART parity checker....................................................................................................167
14.9.4 USIn UART disabling receiver ............................................................................................167
14.9.5 USIn Asynchronous data reception.................................................................................167
14.10 USIn SPI mode..........................................................................................................................169
14.11 USIn SPI clock formats and timing..................................................................................170
14.12 USIn SPI block diagram........................................................................................................172
14.13 USIn I2C mode .........................................................................................................................172
14.14 USIn I2C bit transfer...............................................................................................................173
14.15 USIn I2C start/ repeated start/ stop ...............................................................................173

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14.16 USIn I2C data transfer...........................................................................................................174
14.17 USIn I2C acknowledge ..........................................................................................................174
14.18 USIn I2C synchronization/ arbitration............................................................................175
14.19 USIn I2C operation .................................................................................................................176
14.19.1 USIn I2C master transmitter ......................................................................................177
14.19.2 USIn I2C master receiver.............................................................................................179
14.19.3 USIn I2C slave transmitter ..........................................................................................180
14.19.4 USIn I2C slave receiver.................................................................................................181
14.20 USIn I2C block diagram........................................................................................................183
14.21 Register map .............................................................................................................................183
14.22 USIn register description......................................................................................................184
14.23 Baud rate settings (example) .............................................................................................192
15 USART2 ........................................................................................................................................195
15.1 Block diagram ...........................................................................................................................196
15.2 Clock generation......................................................................................................................197
15.3 External clock (XCK)................................................................................................................198
15.4 Synchronous mode operation...........................................................................................198
15.5 Data format................................................................................................................................199
15.6 Parity bit ......................................................................................................................................200
15.7 USART2 transmitter ................................................................................................................200
15.7.1 Sending Tx data .......................................................................................................................200
15.7.2 Transmitter flag and interrupt...........................................................................................200
15.7.3 Parity generator........................................................................................................................201
15.7.4 Disabling transmitter..............................................................................................................201
15.8 USART2 receiver.......................................................................................................................201
15.8.1 Receiving Rx data....................................................................................................................201

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15.8.2 Receiver flag and interrupt .................................................................................................202
15.8.3 Parity checker............................................................................................................................202
15.8.4 Disabling receiver....................................................................................................................203
15.8.5 Asynchronous data reception............................................................................................203
15.9 SPI mode.....................................................................................................................................204
15.9.1 SPI clock formats and timing.............................................................................................205
15.10 Receiver time out (RTO).......................................................................................................208
15.11 Register map .............................................................................................................................209
15.12 Register description................................................................................................................209
15.13 Baud rate settings (example) .............................................................................................216
15.14 0% error baud rate.................................................................................................................217
16 Power down operation .........................................................................................................219
16.1 Peripheral operation in IDLE/ STOP mode ..................................................................219
16.2 IDLE mode ..................................................................................................................................220
16.3 STOP mode ................................................................................................................................220
16.4 Released operation of STOP mode.................................................................................221
16.5 Register map .............................................................................................................................222
16.6 Register description................................................................................................................222
17 Reset..............................................................................................................................................224
17.1 Reset block diagram ..............................................................................................................224
17.2 Power on reset .........................................................................................................................224
17.3 External resetb input..............................................................................................................227
17.4 Low voltage reset process...................................................................................................228
17.5 LVI block diagram ...................................................................................................................230
17.6 Register Map .............................................................................................................................231
17.7 Reset Operation Register Description............................................................................231

Contents A96G140/A96G148 User’s manual
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18 Memory programming..........................................................................................................234
18.1 Flash control and status registers....................................................................................234
18.1.1 Register map .............................................................................................................................234
18.1.2 Register description................................................................................................................234
18.2 Memory map.............................................................................................................................241
18.2.1 Flash memory map.................................................................................................................241
18.3 Serial in-system program mode.......................................................................................242
18.3.1 Flash operation.........................................................................................................................242
18.4 Mode entrance method of ISP mode............................................................................248
18.4.1 Mode entrance method for ISP........................................................................................248
18.5 Security.........................................................................................................................................249
18.6 Configure option .....................................................................................................................249
19 Electrical characteristics ........................................................................................................251
19.1 Absolute maximum ratings.................................................................................................251
19.2 Recommended operating conditions.............................................................................252
19.3 A/D converter characteristics .............................................................................................252
19.4 Power on reset characteristics...........................................................................................253
19.5 Low voltage reset and low voltage indicator characteristics...............................253
19.6 High internal RC oscillator characteristics....................................................................254
19.7 Low internal RC oscillator characteristics .....................................................................254
19.8 DC characteristics ....................................................................................................................255
19.9 AC characteristics ....................................................................................................................256
19.10 USART characteristics ............................................................................................................257
19.11 SPI0/1 characteristics .............................................................................................................258
19.12 UART0/1 characteristics........................................................................................................259
19.13 I2C0/1 characteristics.............................................................................................................260