Abov A96G140 User manual

Global Top Smart MCU Innovator
www.abov.co.kr
A96G140/A96G148
User’s Manual
CMOS Single Chip 8-bit MCU with 12-bit ADC
General Purpose Microcontroller
Version 1.13
Introduction
This user’s manual targets application developers who use A96G140/A96G148 for their specific
needs. It provides complete information of how to use A96G140/A96G148 device. Standard functions
and blocks including corresponding register information of A96G140/A96G148 are introduced in each
chapter, while instruction set is in Appendix.
A96G140/A96G148 is based on M8051 core, and provides standard features of 8051 such as 8-bit
ALU, PC, 8-bit registers, timers and counters, serial data communication, PSW, DPTR, SP, 8-bit data
bus and 2x16-bit address bus, and 8/11/16-bit operations.
In addition, this device incorporates followings to offer highly flexible and cost effective solutions:
64Kbytes of FLASH, 256bytes of IRAM, 2304bytes of XRAM, general purpose I/O, basic interval timer,
watchdog timer, 8/16-bit timer/counter, 16-bit PPG output, 8-bit PWM output, 16-bit PWM output,
watch timer, buzzer driving port, USI, 12-bit A/D converter, on-chip POR, LVR, LVI, on-chip oscillator
and clock circuitry.
As a field proven best seller, A96G140/A96G148 has been sold more than 3 billion units up to now,
and introduces rich features such as excellent noise immunity, code optimization, cost effectiveness,
and so on.
Reference document
A96G140/A96G148 programming tools and manuals released by ABOV: They are available
at ABOV website, www.abov.co.kr/e_main.php.
SDK-51 User’s guide (System Design Kit) released by Intel in 1982: It contains all of
components of a single-board computer based on Intel’s 8051 single-chip microcomputer
Information on Mentor Graphics 8051 microcontroller: The technical document is provided at
Mentorwebsite: https://www.mentor.com/products/ip/peripheral/microcontroller/

Contents A96G140/A96G148 User’s manual
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Contents
1Description..................................................................................................................................................... 21
1.1 Device overview ......................................................................................................................... 21
1.2 A96G140/A96G148 block diagram.................................................................................... 22
2Pinouts and pin description................................................................................................................... 24
2.1 Pinouts............................................................................................................................................ 24
2.2 Pin description............................................................................................................................ 28
3Port structures.............................................................................................................................................. 33
4Memory organization................................................................................................................................ 35
4.1 Program memory ...................................................................................................................... 35
4.2 Data memory............................................................................................................................... 36
4.3 External data memory ............................................................................................................. 38
4.4 SFR map......................................................................................................................................... 39
4.4.1 SFR map summary.................................................................................................................... 39
4.4.2 SFR map......................................................................................................................................... 41
4.4.3 Compiler compatible SFR ...................................................................................................... 46
5I/O ports ......................................................................................................................................................... 48
5.1 Port register ................................................................................................................................. 48
5.1.1 Data register (Px)....................................................................................................................... 48
5.1.2 Direction register (PxIO)......................................................................................................... 48
5.1.3 Pull-up register selection register (PxPU)....................................................................... 48
5.1.4 Open-drain Selection Register (PxOD) ............................................................................ 48
5.1.5 De-bounce Enable Register (PxDB)................................................................................... 48
5.1.6 Port Function Selection Register (PxFSR) ....................................................................... 48
5.1.7 Register Map ............................................................................................................................... 50
5.2 P0 port............................................................................................................................................ 51

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5.2.1 P0 port description................................................................................................................... 51
5.2.2 Register description for P0 ................................................................................................... 51
5.3 P1 port............................................................................................................................................ 54
5.3.1 P1 port description................................................................................................................... 54
5.3.2 Register description for P1 ................................................................................................... 54
5.4 P2 port............................................................................................................................................ 58
5.4.1 P2 port description................................................................................................................... 58
5.4.2 Register description for P2 ................................................................................................... 58
5.5 P3 port............................................................................................................................................ 60
5.5.1 P3 port description................................................................................................................... 60
5.5.2 Register description for P3 ................................................................................................... 60
5.6 P4 port............................................................................................................................................ 62
5.6.1 P4 port description................................................................................................................... 62
5.6.2 Register description for P4 ................................................................................................... 62
5.7 P5 port............................................................................................................................................ 64
5.7.1 P5 port description................................................................................................................... 64
5.7.2 Register description for P5 ................................................................................................... 64
6Interrupt controller..................................................................................................................................... 66
6.1 External interrupt....................................................................................................................... 67
6.2 Block diagram ............................................................................................................................. 68
6.3 Interrupt vector table............................................................................................................... 70
6.4 Interrupt sequence.................................................................................................................... 71
6.5 Effective timing after controlling interrupt bit............................................................. 72
6.6 Multi-interrupt ............................................................................................................................ 73
6.7 Interrupt enable accept timing ........................................................................................... 74
6.8 Interrupt service routine address ....................................................................................... 75

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6.9 Saving/restore general purpose registers ...................................................................... 75
6.10 Interrupt timing.......................................................................................................................... 76
6.11 Interrupt register overview.................................................................................................... 76
6.11.1 Interrupt Enable Register (IE, IE1, IE2, and IE3) ........................................................... 76
6.11.2 Interrupt Priority Register (IP and IP1) ............................................................................ 76
6.11.3 External Interrupt Flag Register (EIFLAG0 and EIFLAG1) ......................................... 77
6.11.4 External Interrupt Polarity Register (EIPOL0L, EIPOL0H, and EIPOL1) ............... 77
6.11.5 Register map ............................................................................................................................... 77
6.11.6 Interrupt register description............................................................................................... 77
7Clock generator ........................................................................................................................................... 84
7.1 Clock generator block diagram .......................................................................................... 84
7.2 Register map ............................................................................................................................... 85
7.3 Register description.................................................................................................................. 85
8Basic interval timer..................................................................................................................................... 88
8.1 BIT block diagram ..................................................................................................................... 88
8.2 BIT register map......................................................................................................................... 88
8.3 BIT register description........................................................................................................... 89
9Watchdog timer........................................................................................................................................... 90
9.1 WDT interrupt timing waveform ........................................................................................ 90
9.2 WDT block diagram ................................................................................................................. 91
9.3 Register map ............................................................................................................................... 91
9.4 Register description.................................................................................................................. 91
10 Watch timer ................................................................................................................................. 93
10.1 WT block diagram..................................................................................................................... 93
10.2 Register map ............................................................................................................................... 93
10.3 Watch timer register description........................................................................................ 94

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11 Timer 0/1/2/3/4/5 ..................................................................................................................... 96
11.1 Timer 0 ........................................................................................................................................... 96
11.1.1 8-bit timer/counter mode ..................................................................................................... 96
11.1.2 8-bit PWM mode....................................................................................................................... 98
11.1.3 8-bit capture mode ................................................................................................................100
11.1.4 Timer 0 block diagram..........................................................................................................102
11.1.5 Register map .............................................................................................................................102
11.1.6 Register description................................................................................................................102
11.2 Timer 1 .........................................................................................................................................104
11.2.1 16-bit timer/counter mode.................................................................................................104
11.2.2 16-bit capture mode..............................................................................................................107
11.2.3 16-bit PPG mode.....................................................................................................................108
11.2.4 16-bit timer 1 block diagram.............................................................................................111
11.2.5 Register map .............................................................................................................................111
11.2.6 Register description................................................................................................................111
11.3 Timer 2 .........................................................................................................................................114
11.3.1 16-bit timer/counter mode.................................................................................................115
11.3.2 16-bit capture mode..............................................................................................................117
11.3.3 16-bit PPG mode.....................................................................................................................119
11.3.4 16-bit timer 2 block diagram.............................................................................................121
11.3.5 Register map .............................................................................................................................121
11.3.6 Register description................................................................................................................121
11.4 Timer 3 .........................................................................................................................................124
11.4.1 16-bit timer/counter mode.................................................................................................124
11.4.2 16-bit capture mode..............................................................................................................126
11.4.3 16-bit PPG mode.....................................................................................................................128

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11.4.4 16-bit timer 3 block diagram.............................................................................................130
11.4.5 Register map .............................................................................................................................130
11.4.6 Register description................................................................................................................130
11.5 Timer 4 .........................................................................................................................................133
11.5.1 16-bit timer/counter mode.................................................................................................134
11.5.2 16-bit capture mode..............................................................................................................136
11.5.3 16-bit PPG mode.....................................................................................................................138
11.5.4 16-bit timer 4 block diagram.............................................................................................140
11.5.5 Register map .............................................................................................................................140
11.5.6 Register description................................................................................................................140
11.6 Timer 5 .........................................................................................................................................143
11.6.1 16-bit timer/counter mode.................................................................................................143
11.6.2 16-bit capture mode..............................................................................................................145
11.6.3 16-bit PPG mode.....................................................................................................................147
11.6.4 16-bit timer 5 block diagram.............................................................................................149
11.6.5 Register map .............................................................................................................................149
11.6.6 Register description................................................................................................................149
12 Buzzer driver..............................................................................................................................152
12.1 Buzzer driver block diagram ..............................................................................................152
12.2 Register map .............................................................................................................................152
12.3 Register description................................................................................................................153
13 12-bit ADC..................................................................................................................................154
13.1 Conversion timing...................................................................................................................154
13.2 Block diagram ...........................................................................................................................154
13.3 ADC operation..........................................................................................................................156
13.4 Register map .............................................................................................................................157

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13.5 Register description................................................................................................................157
14 USI (USART + SPI + I2C)......................................................................................................160
14.1 USIn UART mode.....................................................................................................................160
14.2 USIn UART block diagram...................................................................................................161
14.3 USIn clock generation ...........................................................................................................162
14.4 USIn external clock (SCKn)..................................................................................................163
14.5 USIn synchronous mode operation ................................................................................163
14.6 USIn UART data format ........................................................................................................163
14.7 USIn UART parity bit..............................................................................................................164
14.8 USIn UART transmitter..........................................................................................................165
14.8.1 USIn UART sending TX data...............................................................................................165
14.8.2 USIn UART transmitter flag and interrupt....................................................................165
14.8.3 USIn UART parity generator...............................................................................................166
14.8.4 USIn UART disabling transmitter......................................................................................166
14.9 USIn UART receiver.................................................................................................................166
14.9.1 USIn UART receiver RX data...............................................................................................166
14.9.2 USIn UART receiver flag and interrupt ..........................................................................167
14.9.3 USIn UART parity checker....................................................................................................167
14.9.4 USIn UART disabling receiver ............................................................................................167
14.9.5 USIn Asynchronous data reception.................................................................................167
14.10 USIn SPI mode..........................................................................................................................169
14.11 USIn SPI clock formats and timing..................................................................................170
14.12 USIn SPI block diagram........................................................................................................172
14.13 USIn I2C mode .........................................................................................................................172
14.14 USIn I2C bit transfer...............................................................................................................173
14.15 USIn I2C start/ repeated start/ stop ...............................................................................173

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14.16 USIn I2C data transfer...........................................................................................................174
14.17 USIn I2C acknowledge ..........................................................................................................174
14.18 USIn I2C synchronization/ arbitration............................................................................175
14.19 USIn I2C operation .................................................................................................................176
14.19.1 USIn I2C master transmitter ......................................................................................177
14.19.2 USIn I2C master receiver.............................................................................................179
14.19.3 USIn I2C slave transmitter ..........................................................................................180
14.19.4 USIn I2C slave receiver.................................................................................................181
14.20 USIn I2C block diagram........................................................................................................183
14.21 Register map .............................................................................................................................183
14.22 USIn register description......................................................................................................184
14.23 Baud rate settings (example) .............................................................................................192
15 USART2 ........................................................................................................................................195
15.1 Block diagram ...........................................................................................................................196
15.2 Clock generation......................................................................................................................197
15.3 External clock (XCK)................................................................................................................198
15.4 Synchronous mode operation...........................................................................................198
15.5 Data format................................................................................................................................199
15.6 Parity bit ......................................................................................................................................200
15.7 USART2 transmitter ................................................................................................................200
15.7.1 Sending Tx data .......................................................................................................................200
15.7.2 Transmitter flag and interrupt...........................................................................................200
15.7.3 Parity generator........................................................................................................................201
15.7.4 Disabling transmitter..............................................................................................................201
15.8 USART2 receiver.......................................................................................................................201
15.8.1 Receiving Rx data....................................................................................................................201

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15.8.2 Receiver flag and interrupt .................................................................................................202
15.8.3 Parity checker............................................................................................................................202
15.8.4 Disabling receiver....................................................................................................................203
15.8.5 Asynchronous data reception............................................................................................203
15.9 SPI mode.....................................................................................................................................204
15.9.1 SPI clock formats and timing.............................................................................................205
15.10 Receiver time out (RTO).......................................................................................................208
15.11 Register map .............................................................................................................................209
15.12 Register description................................................................................................................209
15.13 Baud rate settings (example) .............................................................................................216
15.14 0% error baud rate.................................................................................................................217
16 Power down operation .........................................................................................................219
16.1 Peripheral operation in IDLE/ STOP mode ..................................................................219
16.2 IDLE mode ..................................................................................................................................220
16.3 STOP mode ................................................................................................................................220
16.4 Released operation of STOP mode.................................................................................221
16.5 Register map .............................................................................................................................222
16.6 Register description................................................................................................................222
17 Reset..............................................................................................................................................224
17.1 Reset block diagram ..............................................................................................................224
17.2 Power on reset .........................................................................................................................224
17.3 External resetb input..............................................................................................................227
17.4 Low voltage reset process...................................................................................................228
17.5 LVI block diagram ...................................................................................................................230
17.6 Register Map .............................................................................................................................231
17.7 Reset Operation Register Description............................................................................231

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18 Memory programming..........................................................................................................234
18.1 Flash control and status registers....................................................................................234
18.1.1 Register map .............................................................................................................................234
18.1.2 Register description................................................................................................................234
18.2 Memory map.............................................................................................................................241
18.2.1 Flash memory map.................................................................................................................241
18.3 Serial in-system program mode.......................................................................................242
18.3.1 Flash operation.........................................................................................................................242
18.4 Mode entrance method of ISP mode............................................................................248
18.4.1 Mode entrance method for ISP........................................................................................248
18.5 Security.........................................................................................................................................249
18.6 Configure option .....................................................................................................................249
19 Electrical characteristics ........................................................................................................251
19.1 Absolute maximum ratings.................................................................................................251
19.2 Recommended operating conditions.............................................................................252
19.3 A/D converter characteristics .............................................................................................252
19.4 Power on reset characteristics...........................................................................................253
19.5 Low voltage reset and low voltage indicator characteristics...............................253
19.6 High internal RC oscillator characteristics....................................................................254
19.7 Low internal RC oscillator characteristics .....................................................................254
19.8 DC characteristics ....................................................................................................................255
19.9 AC characteristics ....................................................................................................................256
19.10 USART characteristics ............................................................................................................257
19.11 SPI0/1 characteristics .............................................................................................................258
19.12 UART0/1 characteristics........................................................................................................259
19.13 I2C0/1 characteristics.............................................................................................................260

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19.14 Data retention voltage in stop mode ............................................................................261
19.15 Internal flash ROM characteristics ...................................................................................262
19.16 Input/output capacitance.....................................................................................................263
19.17 Main clock oscillator characteristics................................................................................263
19.18 Sub-clock oscillator characteristics..................................................................................264
19.19 Main oscillation stabilization characteristics ...............................................................265
19.20 Sub-oscillation characteristics............................................................................................265
19.21 Operating voltage range......................................................................................................266
19.22 Recommended circuit and layout....................................................................................267
19.23 Typical characteristics ............................................................................................................267
20 Development tools .................................................................................................................270
20.1 Compiler ......................................................................................................................................270
20.2 OCD (On-chip debugger) emulator and debugger.................................................270
20.3 Programmers.............................................................................................................................271
20.3.1 E-PGM+ .......................................................................................................................................271
20.3.2 OCD emulator...........................................................................................................................271
20.3.3 Gang programmer ..................................................................................................................271
20.4 Flash programming ................................................................................................................272
20.4.1 On-board programming.......................................................................................................272
20.4.2 Circuit design guide...............................................................................................................272
20.5 On-chip debug system .........................................................................................................273
20.5.1 Two-pin external interface...................................................................................................274
21 Package information ..............................................................................................................279
21.1 48 LQFP package information...........................................................................................279
21.2 44 MQFP package information.........................................................................................281
21.3 32 LQFP package information...........................................................................................283

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21.4 32 SOP package information.............................................................................................285
21.5 28 SOP package information.............................................................................................287
21.6 28 TSSOP package information ........................................................................................289
22 Ordering information.............................................................................................................291
Appendix................................................................................................................................................................293
Instruction table.............................................................................................................................................293
Revision history...................................................................................................................................................299
Worldwide Distributors and Sales Offices ..............................................................................................300
Distributors.......................................................................................................................................................300
Sales Offices.....................................................................................................................................................300

A96G140/A96G148 User’s manual List of figures
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List of figures
FIGURE 1. A96G140/A96G148 BLOCK DIAGRAM...................................................................................................... 23
FIGURE 2. A96G140/A96G148 48LQFP-0707 PIN ASSIGNMENT ....................................................................... 24
FIGURE 3. A96G140/A96G148 44MQFP-1010 PIN ASSIGNMENT ..................................................................... 25
FIGURE 4. A96G140/A96G148 32LQFP PIN ASSIGNMENT ................................................................................... 26
FIGURE 5. A96G140/A96G148 32SOP PIN ASSIGNMENT ..................................................................................... 27
FIGURE 6. A96G140/A96G148 28SOP PIN ASSIGNMENT ..................................................................................... 27
FIGURE 7. GENERAL PURPOSE I/O PORT...................................................................................................................... 33
FIGURE 8. EXTERNAL INTERRUPT I/O PORT................................................................................................................ 34
FIGURE 9. PROGRAM MEMORY MAP............................................................................................................................. 36
FIGURE 10. DATA MEMORY MAP ..................................................................................................................................... 37
FIGURE 11. LOWER 128BYTES OF RAM ......................................................................................................................... 38
FIGURE 12. XDATA MEMORY AREA ................................................................................................................................. 39
FIGURE 13. INTERRUPT GROUP PRIORITY LEVEL...................................................................................................... 67
FIGURE 14. EXTERNAL INTERRUPT DESCRIPTION .................................................................................................... 68
FIGURE 15. INTERRUPT CONTROLLER BLOCK DIAGRAM...................................................................................... 69
FIGURE 16. INTERRUPT SEQUENCE FLOW ................................................................................................................... 72
FIGURE 17. EFFECTIVE TIMING OF INTERRUPT ENABLE REGISTER .................................................................. 73
FIGURE 18. EFFECTIVE TIMING OF INTERRUPT FLAG REGISTER........................................................................ 73
FIGURE 19. EFFECTIVE TIMING OF MULTI-INTERRUPT........................................................................................... 74
FIGURE 20. INTERRUPT RESPONSE TIMING DIAGRAM.......................................................................................... 75
FIGURE 21. CORRESPONDENCE BETWEEN VECTOR TABLE ADDRESS AND THE ENTRY ADDRESS OF
ISR .......................................................................................................................................................................................... 75
FIGURE 22. SAVING/RESTORE PROCESS DIAGRAM AND SAMPLE SOURCE................................................ 75
FIGURE 23. TIMING CHART OF INTERRUPT ACCEPTANCE AND INTERRUPT RETURN INSTRUCTION
................................................................................................................................................................................................. 76
FIGURE 24. CLOCK GENERATOR BLOCK DIAGRAM.................................................................................................. 85
FIGURE 25. BASIC INTERVAL TIMER BLOCK DIAGRAM .......................................................................................... 88
FIGURE 26. WATCH DOG TIMER INTERRUPT TIMING WAVEFORM.................................................................. 90
FIGURE 27. WATCH DOG TIMER INTERRUPT TIMING WAVEFORM.................................................................. 91
FIGURE 28. WATCH TIMER BLOCK DIAGRAM ............................................................................................................. 93
FIGURE 29. 8-BIT TIMER/COUNTER MODE FOR TIMER 0..................................................................................... 97
FIGURE 30. 8-BIT TIMER/COUNTER 0 EXAMPLE........................................................................................................ 97
FIGURE 31. 8-BIT PWM MODE FOR TIMER 0 ............................................................................................................. 98
FIGURE 32. PWM OUTPUT WAVEFORMS IN PWM MODE FOR TIMER 0...................................................... 99
FIGURE 33. 8-BIT CAPTURE MODE FOR TIMER 0 ...................................................................................................100
FIGURE 34. INPUT CAPTURE MODE OPERATION FOR TIMER 0 ......................................................................101

List of figures A96G140/A96G148 User’s manual
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FIGURE 35. EXPRESS TIMER OVERFLOW IN CAPTURE MODE ..........................................................................101
FIGURE 36. 8-BIT TIMER 0 BLOCK DIAGRAM............................................................................................................102
FIGURE 37. 16-BIT TIMER/COUNTER MODE OF TIMER 1...................................................................................106
FIGURE 38. 16-BIT TIMER/COUNTER MODE OPERATION EXAMPLE .............................................................106
FIGURE 39. 16-BIT CAPTURE MODE OF TIMER 1 ...................................................................................................107
FIGURE 40. 16-BIT CAPTURE MODE OPERATION EXAMPLE..............................................................................108
FIGURE 41. 16-BIT PPG MODE OF TIMER 1 ..............................................................................................................109
FIGURE 42. 16-BIT PPG MODE OPERATION EXAMPLE.........................................................................................110
FIGURE 43. 16-BIT TIMER 1 BLOCK DIAGRAM.........................................................................................................111
FIGURE 44. 16-BIT TIMER/COUNTER MODE OF TIMER 2...................................................................................116
FIGURE 45. 16-BIT TIMER/COUNTER MODE OPERATION EXAMPLE .............................................................116
FIGURE 46. 16-BIT CAPTURE MODE OF TIMER 2 ...................................................................................................117
FIGURE 47. 16-BIT CAPTURE MODE OPERATION EXAMPLE..............................................................................118
FIGURE 48. EXPRESS TIMER OVERFLOW IN CAPTURE MODE ..........................................................................118
FIGURE 49. 16-BIT PPG MODE OF TIMER 2 ..............................................................................................................119
FIGURE 50. 16-BIT PPG MODE OPERATION EXAMPLE.........................................................................................120
FIGURE 51. 16-BIT TIMER 2 BLOCK DIAGRAM.........................................................................................................121
FIGURE 52. 16-BIT TIMER/COUNTER MODE OF TIMER 3...................................................................................125
FIGURE 53. 16-BIT TIMER/COUNTER MODE OPERATION EXAMPLE .............................................................125
FIGURE 54. 16-BIT CAPTURE MODE OF TIMER 3 ...................................................................................................126
FIGURE 55. 16-BIT CAPTURE MODE OPERATION EXAMPLE..............................................................................127
FIGURE 56. EXPRESS TIMER OVERFLOW IN CAPTURE MODE ..........................................................................127
FIGURE 57. 16-BIT PPG MODE OF TIMER 3 ..............................................................................................................128
FIGURE 58. 16-BIT PPG MODE OPERATION EXAMPLE.........................................................................................129
FIGURE 59. 16-BIT TIMER 3 BLOCK DIAGRAM.........................................................................................................130
FIGURE 60. 16-BIT TIMER/COUNTER MODE OF TIMER 4...................................................................................135
FIGURE 61. 16-BIT TIMER/COUNTER MODE OPERATION EXAMPLE .............................................................135
FIGURE 62. 16-BIT CAPTURE MODE OF TIMER 4 ...................................................................................................136
FIGURE 63. 16-BIT CAPTURE MODE OPERATION EXAMPLE..............................................................................137
FIGURE 64. EXPRESS TIMER OVERFLOW IN CAPTURE MODE ..........................................................................137
FIGURE 65. 16-BIT PPG MODE OF TIMER 4 ..............................................................................................................138
FIGURE 66. 16-BIT PPG MODE OPERATION EXAMPLE.........................................................................................139
FIGURE 67. 16-BIT TIMER 4 BLOCK DIAGRAM.........................................................................................................140
FIGURE 68. 16-BIT TIMER/COUNTER MODE OF TIMER 5...................................................................................144
FIGURE 69. 16-BIT TIMER/COUNTER MODE OPERATION EXAMPLE .............................................................144
FIGURE 70. 16-BIT CAPTURE MODE OF TIMER 5 ...................................................................................................145
FIGURE 71. 16-BIT CAPTURE MODE OPERATION EXAMPLE..............................................................................146
FIGURE 72. EXPRESS TIMER OVERFLOW IN CAPTURE MODE ..........................................................................146
FIGURE 73. 16-BIT PPG MODE OF TIMER 5 ..............................................................................................................147

A96G140/A96G148 User’s manual List of figures
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FIGURE 74. 16-BIT PPG MODE OPERATION EXAMPLE.........................................................................................148
FIGURE 75. 16-BIT TIMER 5 BLOCK DIAGRAM.........................................................................................................149
FIGURE 76. BUZZER DRIVER BLOCK DIAGRAM........................................................................................................152
FIGURE 77. 12-BIT ADC BLOCK DIAGRAM.................................................................................................................155
FIGURE 78. A/D ANALOG INPUT PIN WITH A CAPACITOR................................................................................155
FIGURE 79. A/D POWER (AVREF) PIN WITH A CAPACITOR................................................................................155
FIGURE 80. CONTROL REGISTERS AND ALIGN BITS .............................................................................................156
FIGURE 81. ADC OPERATION FLOW SEQUENCE .....................................................................................................157
FIGURE 82. USIN USART BLOCK DIAGRAM (N = 0 AND 1) ..............................................................................161
FIGURE 83. CLOCK GENERATION BLOCK DIAGRAM (USIN)...............................................................................162
FIGURE 84. SYNCHRONOUS MODE SCKN TIMING (USIN) ................................................................................163
FIGURE 85. FRAME FORMATS (USIN) ...........................................................................................................................164
FIGURE 86. ASYNCHRONOUS START BIT SAMPLING (USIN) ............................................................................168
FIGURE 87. ASYNCHRONOUS SAMPLING OF DATA AND PARITY BIT (USIN) ...........................................169
FIGURE 88. STOP BIT SAMPLING AND NEXT START BIT SAMPLING (USIN)..............................................169
FIGURE 89. USIN SPI CLOCK FORMATS WHEN CPHAN = 0 .............................................................................170
FIGURE 90. USIN SPI CLOCK FORMATS WHEN CPHAN = 1 .............................................................................171
FIGURE 91. USIN SPI BLOCK DIAGRAM (N = 0 AND 1) ......................................................................................172
FIGURE 92. BIT TRANSFER ON THE I2C-BUS (USIN) .............................................................................................173
FIGURE 93. START AND STOP CONDITION (USIN).................................................................................................174
FIGURE 94. DATA TRANSFER ON THE I2C-BUS (USIN).........................................................................................174
FIGURE 95. ACKNOWLEDGE ON THE I2C-BUS (USIN) .........................................................................................175
FIGURE 96. CLOCK SYNCHRONIZATION DURING ARBITRATION PROCEDURE (USIN) .........................176
FIGURE 97. ARBITRATION PROCEDURE OF TWO MASTERS (USIN)...............................................................176
FIGURE 98. USIN I2C BLOCK DIAGRAM ......................................................................................................................183
FIGURE 99. USART2 BLOCK DIAGRAM.........................................................................................................................196
FIGURE 100. CLOCK GENERATION BLOCK DIAGRAM...........................................................................................197
FIGURE 101. SYNCHRONOUS MODE XCK TIMING ................................................................................................198
FIGURE 102. A FRAME FORMAT......................................................................................................................................199
FIGURE 103. START BIT SAMPLING................................................................................................................................203
FIGURE 104. SAMPLING OF DATA AND PARITY BIT ..............................................................................................204
FIGURE 105. STOP BIT SAMPLING AND NEXT START BIT SAMPLING ..........................................................204
FIGURE 106. SPI CLOCK FORMATS WHEN UCPHA = 0 .......................................................................................206
FIGURE 107. SPI CLOCK FORMATS WHEN UCPHA = 1 .......................................................................................207
FIGURE 108. EXAMPLE FOR RTO IN USART2 ............................................................................................................208
FIGURE 109. 0% ERROR BAUD RATE BLOCK DIAGRAM ......................................................................................218
FIGURE 110. IDLE MODE RELEASE TIMING BY AN EXTERNAL INTERRUPT................................................220
FIGURE 111. STOP MODE RELEASE TIMING BY EXTERNAL INTERRUPT ......................................................221
FIGURE 112. STOP MODE RELEASE FLOW .................................................................................................................222

List of figures A96G140/A96G148 User’s manual
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FIGURE 113. RESET BLOCK DIAGRAM ..........................................................................................................................224
FIGURE 114. FAST VDD RISING TIME............................................................................................................................225
FIGURE 115. INTERNAL RESET RELEASE TIMING ON POWER-UP ..................................................................225
FIGURE 116. CONFIGURATION TIMING WHEN POWER-ON .............................................................................226
FIGURE 117. BOOT PROCESS WAVEFORM.................................................................................................................226
FIGURE 118. TIMING DIAGRAM AFTER RESET..........................................................................................................228
FIGURE 119. OSCILLATOR GENERATING WAVEFORM EXAMPLE .....................................................................228
FIGURE 120. BLOCK DIAGRAM OF LVR........................................................................................................................229
FIGURE 121. INTERNAL RESET AT POWER FAIL SITUATION...............................................................................229
FIGURE 122. CONFIGURATION TIMING WHEN LVR RESET................................................................................230
FIGURE 123. LVI BLOCK DIAGRAM.................................................................................................................................230
FIGURE 124. READ DEVICE INTERNAL CHECKSUM (FULL SIZE).......................................................................239
FIGURE 125. READ DEVICE INTERNAL CHECKSUM (USER DEFINE SIZE).....................................................240
FIGURE 126. FLASH MEMORY MAP ..............................................................................................................................242
FIGURE 127. ADDRESS CONFIGURATION OF FLASH MEMORY.......................................................................242
FIGURE 128. THE SEQUENCE OF PAGE PROGRAM AND ERASE OF FLASH MEMORY..........................243
FIGURE 129. THE SEQUENCE OF BULK ERASE OF FLASH MEMORY .............................................................244
FIGURE 130. ISP MODE .......................................................................................................................................................248
FIGURE 131. AC TIMING .....................................................................................................................................................257
FIGURE 132. WAVEFORM FOR USART TIMING CHARACTERISTICS................................................................258
FIGURE 133. TIMING WAVEFORM FOR THE USART MODULE..........................................................................258
FIGURE 134. SPI0/1/2 TIMING..........................................................................................................................................259
FIGURE 135. WAVEFORM FOR UART0/1 TIMING CHARACTERISTICS ...........................................................260
FIGURE 136. TIMING WAVEFORM FOR THE UART0/1 MODULE .....................................................................260
FIGURE 137. I2C0/1 TIMING..............................................................................................................................................261
FIGURE 138. STOP MODE RELEASE TIMING WHEN INITIATED BY AN INTERRUPT................................262
FIGURE 139. STOP MODE RELEASE TIMING WHEN INITIATED BY RESETB ................................................262
FIGURE 140. CRYSTAL/CERAMIC OSCILLATOR..........................................................................................................264
FIGURE 141. EXTERNAL CLOCK .......................................................................................................................................264
FIGURE 142. CRYSTAL OSCILLATOR ...............................................................................................................................264
FIGURE 143. EXTERNAL CLOCK .......................................................................................................................................265
FIGURE 144. CLOCK TIMING MEASUREMENT AT XIN ..........................................................................................265
FIGURE 145. CLOCK TIMING MEASUREMENT AT SXIN........................................................................................266
FIGURE 146. OPERATING VOLTAGE RANGE...............................................................................................................266
FIGURE 147. RECOMMENDED VOLTAGE RANGE ....................................................................................................267
FIGURE 148. RUN (IDD1) CURRENT...............................................................................................................................268
FIGURE 149. IDLE (IDD2) CURRENT ...............................................................................................................................268
FIGURE 150. STOP1 (IDD3) CURRENT...........................................................................................................................269
FIGURE 151. STOP2 (IDD4) CURRENT...........................................................................................................................269

A96G140/A96G148 User’s manual List of figures
17
FIGURE 152. DEBUGGER (OCD1/OCD2) AND PINOUTS ......................................................................................270
FIGURE 153. E-PGM+ (SINGLE WRITER) AND PINOUTS......................................................................................271
FIGURE 154. E-GANG4 AND E-GANG6 (FOR MASS PRODUCTION)..............................................................272
FIGURE 155. PCB DESIGN GUIDE FOR ON-BOARD PROGRAMMING ...........................................................273
FIGURE 156. ON-CHIP DEBUGGING SYSTEM IN BLOCK DIAGRAM...............................................................274
FIGURE 157. 10-BIT TRANSMISSION PACKET ...........................................................................................................275
FIGURE 158. DATA TRANSFER ON TWIN BUS ..........................................................................................................276
FIGURE 159. BIT TRANSFER ON SERIAL BUS ............................................................................................................276
FIGURE 160. START AND STOP CONDITION.............................................................................................................276
FIGURE 161. ACKNOWLEDGE ON SERIAL BUS ........................................................................................................277
FIGURE 162. CLOCK SYNCHRONIZATION DURING WAIT PROCEDURE .......................................................277
FIGURE 163. CONNECTION OF TRANSMISSION.....................................................................................................278
FIGURE 164. 48 LQFP PACKAGE OUTLINE ..................................................................................................................279
FIGURE 165. 44 MQFP PACKAGE OUTLINE ................................................................................................................281
FIGURE 166. 32 LQFP PACKAGE OUTLINE ..................................................................................................................283
FIGURE 167. 32 SOP PACKAGE OUTLINE ....................................................................................................................285
FIGURE 168. 28 SOP PACKAGE OUTLINE ....................................................................................................................287
FIGURE 169. 28 TSSOP PACKAGE OUTLINE ...............................................................................................................289
FIGURE 170. A96G140/A96G148 DEVICE NUMBERING NOMENCLATURE..................................................292

List of tables A96G140/A96G148 User’s manual
18
List of tables
TABLE 1. A96G140/A96G148 DEVICE FEATURES AND PERIPHERAL COUNTS ............................................. 21
TABLE 2. NORMAL PIN DESCRIPTION ............................................................................................................................ 28
TABLE 3. . SFR MAP SUMMARY......................................................................................................................................... 39
TABLE 4. XSFR MAP SUMMARY......................................................................................................................................... 40
TABLE 5. SFR MAP.................................................................................................................................................................... 41
TABLE 6. XSFR MAP................................................................................................................................................................. 45
TABLE 7. PORT REGISTER MAP .......................................................................................................................................... 50
TABLE 8. INTERRUPT VECTOR ADDRESS TABLE......................................................................................................... 70
TABLE 9. INTERRUPT REGISTER MAP .............................................................................................................................. 77
TABLE 10. CLOCK GENERATOR REGISTER MAP.......................................................................................................... 85
TABLE 11. BASIC INTERVAL TIMER REGISTER MAP.................................................................................................. 88
TABLE 12. WATCHDOG TIMER REGISTER MAP........................................................................................................... 91
TABLE 13. WATCH TIMER REGISTER MAP..................................................................................................................... 94
TABLE 14. TIMER 0 OPERATING MODE.......................................................................................................................... 96
TABLE 15. TIMER 0 REGISTER MAP................................................................................................................................102
TABLE 16. TIMER 1 OPERATING MODES .....................................................................................................................104
TABLE 17. TIMER 1 REGISTER MAP................................................................................................................................111
TABLE 18. TIMER 2 OPERATING MODES .....................................................................................................................115
TABLE 19. TIMER 2 REGISTER MAP................................................................................................................................121
TABLE 20. TIMER 3 OPERATING MODES .....................................................................................................................124
TABLE 21. TIMER 3 REGISTER MAP................................................................................................................................130
TABLE 22. TIMER 4 OPERATING MODES .....................................................................................................................134
TABLE 23. TIMER 4 REGISTER MAP................................................................................................................................140
TABLE 24. TIMER 5 OPERATING MODES .....................................................................................................................143
TABLE 25. TIMER 5 REGISTER MAP................................................................................................................................149
TABLE 26. BUZZER FREQUENCY AT 8MHZ .................................................................................................................152
TABLE 27. BUZZER DRIVER REGISTER MAP................................................................................................................153
TABLE 28. ADC REGISTER MAP........................................................................................................................................157
TABLE 29. EQUATIONS FOR CALCULATING USIN BAUD RATE REGISTER SETTING ................................162
TABLE 30. CPOLN FUNCTIONALITY ...............................................................................................................................170
TABLE 31. USI REGISTER MAP ..........................................................................................................................................183
TABLE 32. EXAMPLE1 OF USI0BD AND USI1BDSETTINGS FOR COMMONLY USED OSCILLATOR
FREQUENCIES..................................................................................................................................................................193
TABLE 33. EXAMPLE2 OF USI0BD AND USI1BDSETTINGS FOR COMMONLY USED OSCILLATOR
FREQUENCIES..................................................................................................................................................................194
TABLE 34. EQUATIONS FOR CALCULATING BAUD RATE REGISTER SETTING ............................................197

A96G140/A96G148 User’s manual List of tables
19
TABLE 35. CPOL FUNCTIONALITY...................................................................................................................................205
TABLE 36. EXAMPLE CONDITION OF RTO..................................................................................................................208
TABLE 37. USART2 REGISTER MAP.................................................................................................................................209
TABLE 38. EXAMPLES OF UBAUD SETTINGS FOR COMMONLY USED OSCILLATOR FREQUENCIES
...............................................................................................................................................................................................216
TABLE 39. PERIPHERAL OPERATION STATUS DURING POWER DOWN MODE.........................................219
TABLE 40. POWER DOWN OPERATION REGISTER MAP ......................................................................................222
TABLE 41. HARDWARE SETTING VALUES IN RESET STATE..................................................................................224
TABLE 42. BOOT PROCESS DESCRIPTION...................................................................................................................227
TABLE 43. RESET OPERATION REGISTER MAP ..........................................................................................................231
TABLE 44. FLASH CONTROL AND STATUS REGISTER MAP ................................................................................234
TABLE 45. PROGRAM AND ERASE TIME......................................................................................................................241
TABLE 46. OPERATION MODE ..........................................................................................................................................248
TABLE 47. MODE ENTRANCE METHOD FOR ISP.....................................................................................................248
TABLE 48. SECURITY POLICY USING LOCK BITS ......................................................................................................249
TABLE 49. ABSOLUTE MAXIMUM RATINGS ...............................................................................................................251
TABLE 50. RECOMMENDED OPERATING CONDITIONS .......................................................................................252
TABLE 51. A/D CONVERTER CHARACTERISTICS ......................................................................................................252
TABLE 52. POWER-ON RESET CHARACTERISTICS...................................................................................................253
TABLE 53. LVR AND LVI CHARACTERISTICS ...............................................................................................................253
TABLE 54. HIGH INTERNAL RC OSCILLATOR CHARACTERISTICS.....................................................................254
TABLE 55. INTERNAL WDTRC OSCILLATOR CHARACTERISTICS........................................................................254
TABLE 56. DC CHARACTERISTICS....................................................................................................................................255
TABLE 57. AC CHARACTERISTICS ....................................................................................................................................256
TABLE 58. USART CHARACTERISTICS ............................................................................................................................257
TABLE 59. SPI0/1/2 CHARACTERISTICS ........................................................................................................................258
TABLE 60. UART0/1 CHARACTERISTICS........................................................................................................................259
TABLE 61. I2C0/1 CHARACTERISTICS ............................................................................................................................260
TABLE 62. DATA RETENTION VOLTAGE IN STOP MODE ......................................................................................261
TABLE 63. INTERNAL FLASH ROM CHARACTERISTICS .........................................................................................262
TABLE 64. INPUT / OUTPUT CAPACITANCE ...............................................................................................................263
TABLE 65. MAIN CLOCK OSCILLATOR CHARACTERISTICS ..................................................................................263
TABLE 66. SUB CLOCK OSCILLATOR CHARACTERISTICS......................................................................................264
TABLE 67. MAIN OSCILLATION STABILIZATION CHARACTERISTICS...............................................................265
TABLE 68. SUB OSCILLATION STABILIZATION CHARACTERISTICS...................................................................266
TABLE 69. PINS FOR FLASH PROGRAMMING...........................................................................................................272
TABLE 70. OCD FEATURES..................................................................................................................................................274
TABLE 71. 48 LQFP PACKAGE MECHANICAL DATA.................................................................................................280
TABLE 72. 44 MQFP PACKAGE MECHANICAL DATA ..............................................................................................282

List of tables A96G140/A96G148 User’s manual
20
TABLE 73. 32 LQFP PACKAGE MECHANICAL DATA.................................................................................................284
TABLE 74. 32 SOP PACKAGE MECHANICAL DATA ..................................................................................................286
TABLE 75. 28 SOP PACKAGE MECHANICAL DATA ..................................................................................................288
TABLE 76. 28 TSSOP PACKAGE MECHANICAL DATA .............................................................................................290
TABLE 77. A96G140/A96G148 DEVICE ORDERING INFORMATION ................................................................291
TABLE 78. INSTRUCTION TABLE.......................................................................................................................................293