Nvidia Jetson Orin NX Series User manual

DG-10931-001_v1.1 | April 2023
PRELIMINARY INFORMATION SUBJECT TO CHANGE
Jetson Orin NX Series and Jetson Orin
Nano Series
Product Design Guide

PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | ii
Document History
DG-10931-001_v1.1
Version
Date
Description of Change
0.1
April 25, 2022
Preliminary information Subject to change
0.99
September 30, 2022
•Updated to include Orin Nano series modules in addition to Orin NX
series modules.
•Section 3.1. Added supported PCIe to NVMe configurationsfor
secondary boot storage.
•Table 6-1 and Section 6.1. Updated description of SYS_RESET*
behavior when drivenby carrier board.
•Section 6.1. Added note thatcarrierboards must support VDD_IN at
5V (support for higher voltage on VDD_IN optional)
•Figure 6-4. Power Up Sequence with Power Button. Added missing
text for last line (carrier board supplies)
•Table 7-3. USB3.2 and PCIe Lane Mapping: Corrected column title in
UPHY mapping table to Orin module instead of AGX Orin.
•Various: Updated on-module I2C pull-
1.0
December 20, 2022
•Table 2-1: Added mention of storage options on USB and PCIe
•Figure 2-1: Updated to include option for storage on USB 3.2 or PCIe
•Section 3.1:
>Corrected UPHY block to UPHY2 instead of UPHY1
>Added USB 3.2 optionfor storage
•Figure 5.1: Updated with Orin NX/Nano module
•Updated Table 6-1:
>Updated SLEEP/WAKE* to remove mention of pull-up on
module
>Updated SYS_RESET* on-module pull-up voltage
>Updated CLK_32K_OUT description
•Figure 6-3, Figure 6-4, Table 6-3, and Table 6-4: Updated
SYS_RESET_N delay from POWER_EN
•Figure 6-5: Updated figure to remove arrow from SHUTDOWN_REQ*
to carrier board supplies falling.
•Table 7-2:
>Corrected P/N swap for Orin signal names SF_PCIE7_CLK
(Pins 52/54)
>Corrected +/- swap for SF_PCIE9_CLK descriptions (Pins
227/229)
•Figure 9-1: Corrected P/N swap for SoC DPAUX pins
•Figure 9-2: Corrected P/N swap for SoC DPAUXand PIAUX221Z
device.
•Figure 9-8: Corrected P/N swap for SoC DPAUX

PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | iii
Version
Date
Description of Change
•Table 10-1 and Figure 10-1: Updated to show swapped P/N on two
data lanes
•Table 10-3: Separated clock and data for all lanes.
•Figure 11-1: Updated notes to correct I2C pull-up resistor value on
module.
•Table 12-10: Updated CAN max data rate
1.1
April 7, 2023
•General: Updated to use Orin Nano DevKit Carrier Board as
reference design.
•Table 2-2: Updated legend
•Updated Chapter 4: Developer Kit Feature Considerations; also
updated USB Hub part number.
•Section 5.1: Replaced mention of Xavier NX SCL withOrin NX/Orin
Nano SCL.
•Section 6.1.1 and Figure 6-7: Updated Power Button Supervisor MCU
part #
•Figure 6-5: Added note above figure about possible discharge
circuits.
•Table 7-1: Added mention of Recovery mode for USB_D_N/P
interface.
•Updated: Table 7-3 and Table 7-4:
>Split UPHY mapping options into separate tables per UPHY block
>Updated text above tables allowing more configuration flexibility.
>Separated RP and EP into separate configurations within tables.
>Added two options for PCIe x4 (C4) in UPHY0 table with limitations.
•Section 7.1: Added mention of polarity inversion support for USB 3.2.
•Table 7-11: Removed mention of Root Port and Endpoint for PCIe
interface 1 (x1). Also changed from Endpoint to Root Port in title of
PCIe interface 3 (x1).
•Table 7-6, Table 7-8, Table 9-3, Table 9-5: Moved smaller figures
inside the table instead of following the table.
•Table 8-2: Added Max Inter-Pair (Pair to Pair) skewrequirement for
MDI.
•Table 9-1: Corrected HDMI_CEC Pin Type. See Jetson Orin NX 16GB
Hardware Errata for more details.
•Figure 9-1: Updated HDP connections to include series & pulldown
resistors and breakout details for level shifter.
•Figure 9-2: Removed CEC circuit from DP++ figure and added weak
pull-up to pin 14 of DP connector.
•Table 9-4: Updated Termination for DP1_AUX and DP1_HPD.
•Updated Figure 9-6:
>Added pulldown and seriesresistors on HPD after level shifter.
>Added details of HDMI_CEC circuit &HPD/DDC level shifters.
•Figure 10-1 and Figure 10-2: Separated 2-lane and 4-lane
configuration option examples.

PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | iv
Version
Date
Description of Change
•Table 10-3: Updated 2-
•Table 12-1 and Figure 12-1: Added I2C usage on the module for I2C0
and I2C2.
•Table 13-2: Updated pull-up voltage and/or pull-up resistor values
for several pins.

PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | v
Table of Contents
Chapter 1. Introduction............................................................................................ 1
1.1 References..........................................................................................................................1
1.2 Attachments.......................................................................................................................2
1.3 Abbreviations and Definitions............................................................................................2
Chapter 2. Jetson Orin Module................................................................................ 4
Chapter 3. Jetson Orin Module Boot Considerations ............................................. 9
3.1 QSPI Boot............................................................................................................................9
3.2 USB Recovery Mode...........................................................................................................9
Chapter 4. Developer Kit Feature Considerations ................................................ 11
4.1 Button Power MCU...........................................................................................................11
4.2 USB SuperSpeed Hub......................................................................................................12
4.3 Power over Ethernet........................................................................................................12
4.4 TI TXB0108 Level Shifters................................................................................................12
4.5 Features Not to Be Implemented....................................................................................12
Chapter 5. Modular Connector.............................................................................. 13
5.1 Module Connector Details...............................................................................................13
5.2 Module to Mounting Hardware........................................................................................13
5.3 Module Installation and Removal....................................................................................14
Chapter 6. Power................................................................................................... 15
6.1 Power Supply and Sequencing........................................................................................16
6.1.1 Power Button Supervisor MCU Power-On ...............................................................21
6.1.1.1 Defined Behaviors...............................................................................................23
6.1.1.2 Power-Off -> Power-On (Power Button Case) ..................................................23
6.1.1.3 Power-Off -> Power-On (Auto-Power-On Case)...............................................24
6.1.1.4 Power-On -> Power-Off (Long Power Button Press)........................................24
Chapter 7. USB and PCIe....................................................................................... 26
7.1 USB...................................................................................................................................30
7.1.1 USB 2.0 Routing Guidelines.......................................................................................31
7.1.2 USB 3.2 Routing Guidelines.......................................................................................31
7.1.2.1 Common USB Routing Guidelines.....................................................................34
7.2 PCIe...................................................................................................................................36
7.2.1 PCIe Routing Guidelines............................................................................................38
Chapter 8. Gigabit Ethernet................................................................................... 43
8.1.1 Ethernet MDI Routing Guidelines..............................................................................44

PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | vi
Chapter 9. Display.................................................................................................. 45
9.1 eDP and DP.......................................................................................................................46
9.1.1 eDP and DP Routing Guidelines................................................................................47
9.2 HDMI.................................................................................................................................52
9.2.1 HDMI Routing Guidelines ..........................................................................................53
Chapter 10. MIPI CSI Video Input ............................................................................ 59
10.1 CSI Routing Guidelines....................................................................................................62
Chapter 11. Audio .................................................................................................... 64
11.1.1 I2S Routing Guidelines...............................................................................................65
Chapter 12. Miscellaneous Interfaces .................................................................... 67
12.1 I2C 67
12.1.1 I2C Design Guidelines................................................................................................68
12.1.2 I2C routing Guidelines ...............................................................................................68
12.2 SPI 69
12.2.1 SPI Routing Guidelines..............................................................................................70
12.3 UART71
12.4 CAN 72
12.4.1 CAN Routing Guidelines............................................................................................73
12.5 Fan 73
12.6 Debug................................................................................................................................74
Chapter 13. PADS .................................................................................................... 76
13.1 Internal Pull-Ups for Dual Voltage Block Pins Power at 1.8V.......................................76
13.2 Schmitt Trigger Usage.....................................................................................................76
13.3 Pins Pulled or Driven High During Power-On................................................................77
Chapter 14. Unused Interface Terminations........................................................... 78
14.1 Unused Multi-Purpose Standard CMOS Pad Interfaces................................................78
14.2 Unused Dedicated Special Purpose Pad Interfaces.......................................................78
Chapter 15. Design and Bring-Up Checklists......................................................... 79
Chapter 16. Orin Module Pin Descriptions.............................................................. 80
Chapter 17. General Routing Guidelines................................................................. 81
17.1 Signal Naming Convention ..............................................................................................81
17.2 Routing Guidelines Format..............................................................................................82
17.3 Signal Routing Conventions.............................................................................................82
17.4 Routing Guidelines...........................................................................................................82
17.4.1 General PCB Routing Guidelines..............................................................................83
17.5 Common High-Speed Interface Requirements..............................................................84
17.6 Test Points for High-Speed Interfaces............................................................................85

PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | vii
Chapter 18. USB 3.2 and Wireless Coexistence...................................................... 86
18.1 Mitigation Techniques......................................................................................................86

PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | viii
List of Figures
Figure 2-1. Jetson Orin Module Block Diagram......................................................................5
Figure 5-1. Jetson Orin Module Installed in SODIMM Connector.........................................14
Figure 5-2. Module to Connector Assembly Diagram...........................................................14
Figure 6-1. System Power and Control Block Diagram........................................................18
Figure 6-2. System Power and Control Block Diagram........................................................18
Figure 6-3. Power Up Sequence No Power Button Auto Power On ..................................19
Figure 6-4. Power Up Sequence with Power Button.............................................................19
Figure 6-5. Power Down Initiated by SHUTDOWN_REQ* Assertion.....................................20
Figure 6-6. Power Down Sudden Power Loss .......................................................................20
Figure 6-7. Power-On Button Circuit .....................................................................................22
Figure 6-8. Power-Off to On Sequence Power Button Case.................................................23
Figure 6-9. Power-Off to On Sequence Auto Power-On Case...............................................24
Figure 6-10. Power-On to Off Power Button Held Low > 10 Seconds....................................25
Figure 7-1. USB Micro B USB Device and Recovery Connection Example..........................30
Figure 7-2. USB 3.2 Type A Host Only Connection Example.................................................30
Figure 7-3. IL/NEXT Plot.........................................................................................................34
Figure 7-4. TDR Plot................................................................................................................34
Figure 7-5. PCIe Root Port Connections Example.................................................................36
Figure 7-6. PCIe Endpoint Connections Example..................................................................37
Figure 7-7. Insertion Loss S-Parameter Plot SDD21............................................................40
Figure 7-8. Insertion Loss S-Parameter Plot SDD11............................................................40
Figure 8-1. Orin Module Ethernet Connections.....................................................................43
Figure 8-2. Gigabit Ethernet Magnetics and RJ45 Connections...........................................44
Figure 9-1. DP and eDP Connection Example.......................................................................46
Figure 9-2. DP++ Connection Example ..................................................................................47
Figure 9-3. eDP and DP Differential Main Link Topology......................................................47
Figure 9-4. S-Parameter Up to HBR2....................................................................................50
Figure 9-5. S-Parameter Up to HBR3....................................................................................51
Figure 9-6. HDMI Connection Example..................................................................................52
Figure 9-7. HDMI CLK and Data Topology .............................................................................53
Figure 9-8. IL/FEXT Plot..........................................................................................................57
Figure 9-9. TDR Plot................................................................................................................57
Figure 10-1. CSI 2-Lane Connection Options...........................................................................60
Figure 10-2. CSI 4-Lane Connection Options...........................................................................61
Figure 10-3. Available Camera Control Pins ...........................................................................61
Figure 11-1. Audio Connection Example..................................................................................65
Figure 12-1. I2C Connections....................................................................................................68

PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | ix
Figure 12-2. SPI Connections...................................................................................................70
Figure 12-3. Basic SPI Initiator and Target Connections........................................................70
Figure 12-4. SPI Topologies......................................................................................................70
Figure 12-5. Orin Module UART Connections..........................................................................72
Figure 12-6. Orin Module CAN Connections............................................................................73
Figure 12-7. Orin Module Fan Connections.............................................................................74
Figure 12-8. Debug UART Connections....................................................................................75
Figure 17-1. General PCB Routing Guidelines ........................................................................83
Figure 17-2. Common Mode Choke..........................................................................................84
Figure 17-3. Serpentine ............................................................................................................85

PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | x
List of Tables
Table 1-1. Abbreviations and Definitions................................................................................2
Table 2-1. Jetson Orin Module Interfaces..............................................................................4
Table 2-2. Jetson Orin Module Connector 260-Pin SO-DIMM Pinout Matrix.......................5
Table 6-1. Jetson Orin Module Power and System Pin Description ...................................15
Table 6-2. Power Button Supervisor Control Signals..........................................................21
Table 6-3. Power-Off to On Timing Power Button Case......................................................23
Table 6-4. Power-Off to On Timing Auto Power-On Case ...................................................24
Table 6-5. Power-On to Off Timing Power Button Held Low > 10 Seconds........................25
Table 7-1. Jetson Orin Module USB 2.0 Pin Description.....................................................26
Table 7-2. Jetson Orin Module USB 3.2 and PCIe Pin Description.....................................27
Table 7-3. UPHY0 Mapping Options (USB 3.2 and PCIe)......................................................29
Table 7-4. UPHY2 Mapping Options (PCIe)...........................................................................29
Table 7-5. USB 2.0 Interface Signal Routing Requirements...............................................31
Table 7-6. USB 3.2 Interface Signal Routing Requirements...............................................31
Table 7-7. Orin USB 2.0 Signal Connections........................................................................34
Table 7-8. Miscellaneous USB 2.0 Signal Connections.......................................................35
Table 7-9. Orin USB 3.2 Signal Connections........................................................................35
Table 7-10. PCIe Interface Signal Routing Requirements up to Gen4..................................38
Table 7-11. PCIe Signal Connections......................................................................................41
Table 8-1. Orin Module Gigabit Ethernet Pin Descriptions .................................................43
Table 8-2. Ethernet MDI Interface Signal Routing Requirements ......................................44
Table 8-3. Ethernet Signal Connections...............................................................................44
Table 9-1. Orin Module eDP, DP, and HDMI Pin Descriptions............................................45
Table 9-2. DP and HDMI Pin Mapping ..................................................................................46
Table 9-3. eDP and DP Main Link Signal Requirements Including DP_AUX......................48
Table 9-4. eDP and DP Signal Connections .........................................................................51
Table 9-5. HDMI Interface Signal Routing Requirements...................................................53
Table 9-6. HDMI Signal Connections....................................................................................58
Table 10-1. Orin Module CSI Pin Descriptions.......................................................................59
Table 10-2. Orin Module Camera Miscellaneous Pin Descriptions......................................60
Table 10-3. CSI Configurations ...............................................................................................62
Table 10-4. MIPI CSI D-PHY Interface Signal Routing Requirements..................................62
Table 10-5. MIPI CSI Signal Connections...............................................................................63
Table 10-6. Miscellaneous Camera Connections ..................................................................63
Table 11-1. Orin Module Audio Pin Descriptions...................................................................64
Table 11-2. I2S Interface Signal Routing Requirements.......................................................65
Table 11-3. Audio Signal Connection......................................................................................66

PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | xi
Table 12-1. Orin Module I2C Pin Descriptions.......................................................................67
Table 12-2. I2C Interface Signal Routing Requirements.......................................................68
Table 12-3. I2C Signal Connections........................................................................................69
Table 12-4. Orin Module SPI Pin Descriptions.......................................................................69
Table 12-5. SPI Interface Signal Routing Requirements.......................................................70
Table 12-6. SPI Signal Connections........................................................................................71
Table 12-7. Orin Module UART Pin Descriptions...................................................................71
Table 12-8. UART Signal Connections....................................................................................72
Table 12-9. Orin Module CAN Pin Descriptions.....................................................................72
Table 12-10. CAN Interface Signal Routing Requirements.....................................................73
Table 12-11. CAN Signal Connections......................................................................................73
Table 12-12. Orin Module Fan Pin Descriptions ......................................................................74
Table 12-13. Orin Module Debug UART Pin Descriptions .......................................................74
Table 12-14. Debug UART Connections....................................................................................74
Table 13-1. Pins Pulled or Driven High by Orin Prior to SYS_RESET* Inactive....................77
Table 13-2. Pins with External Pull-Ups to Supply on before SYS_RESET* Inactive...........77
Table 14-1. Unused MPIO Pins and Pin Group.......................................................................78
Table 17-1. Signal Type Codes................................................................................................81
Table 17-2. Common High-Speed Interface Requirements..................................................84

PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 1
Chapter 1. Introduction
This design guide contains recommendations and guidelines for engineers to follow to create
a product that is optimized to achieve the best performance from the interfaces supported by
the NVIDIA®Jetson Orin NX and Jetson Orin Nano System-on-Module (SOM).
This design guide provides detailed information onthe capabilities of the hardware module,
which may differ from supported configurations by provided software. Refer to software
release documentation for information on supported capabilities.
Notes:
•References to Orin module refers to the Jetson Orin module series. Modules include Jetson
Orin NX 16GB, Jetson Orin NX 8GB, Jetson Orin Nano 8GB, and Jetson Orin Nano 4GB.
•All occurrences of USB 3.2 refer to "USB 3.2 Gen 1x1: SuperSpeed USB 5Gbps" and "USB 3.2
Gen 2x1: SuperSpeed USB 10Gbps" only. Also note that Gen 1x1 and Gen 2x1 are referred to
simply as Gen1 and Gen2 in this design guide.
1.1 References
Refer to the following list of documents or models for more information. Use the latest
revision of all documents.
Jetson Orin NX Series Data Sheet
Jetson Orin Nano Series Data Sheet
Orin (SoC) Technical Reference Manual
Jetson Orin NX and Jetson Orin Nano Series Pinmux
Jetson Orin NX Series and Jetson Orin Nano Series Thermal Design Guide
Jetson Orin NX Series and Jetson Orin Nano Series SCL (Supported Component List)

Introduction
PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 2
1.2 Attachments
The following files are attached to this design guide.
Jetson_Orin_NX_Orin_Nano_Pin_Descriptions.nvxlsx
Jetson_Orin_NX_Orin_Nano_Schematic_Checklist.nvxlsx
Jetson_Orin_NX_Orin_Nano_Layout_Checklist.nvxlsx
To access the attached files, click the Attachment icon on the left-hand toolbar on this PDF
(using Adobe Acrobat Reader or Adobe Acrobat). Select the file and use the Tool Bar options
(Open, Save) to retrieve the documents. Excel files with the .nvxlsx extension will need to be
saved as .xlsx.
1.3 Abbreviations and Definitions
Table 1-1 lists the abbreviations that may be used throughout this design and guide and their
definitions.
Table 1-1. Abbreviations and Definitions
Abbreviation
Definition
CAN
Controller Area Network
CEC
Consumer Electronic Control
CSI
Camera Serial Interface
Diff
Differential
DP
DisplayPort
eDP
Embedded DisplayPort
ESD
Electrostatic Discharge
EMI
Electromagnetic Interference
FET
Field Effect Transistor
GPIO
General Purpose Input Output
HDCP
High-bandwidth Digital Content Protection
HDMI
High Definition Multimedia Interface
I2C
Inter IC Interface
I2S
Inter IC Sound Interface
LDO
Low Dropout (voltage regulator)
LPDDR5
Low Power Double Data Rate DRAM, Fifth generation
MDI
Medium-Dependent Interface
MIPI
Mobile Industry Processor Interface
mm
Millimeter
ms
Milliseconds

Introduction
PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 3
Abbreviation
Definition
PCIe
Peripheral Component Interconnect Express interface
PCM
Pulse Code Modulation
PHY
Physical Interface (that is, USB PHY)
ps
Pico-Seconds
PMIC
Power Management Integrated Circuit
RJ45
8P8C modular connector used in Ethernet and other data links
RTC
Real Time Clock
SE
Single-Ended
SoC
System on Chip
SOM
System on Module
SPI
Serial Peripheral Interface
TMDS
Transition-Minimized Differential Signaling
UART
Universal Asynchronous Receiver-Transmitter
USB
Universal Serial Bus

PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 4
Chapter 2. Jetson Orin Module
The Jetson Orin module resides at the center of the embedded system solution and includes:
Power (Power sequencer, regulators, and so on)
DRAM (LPDDR5)
Gigabit Ethernet PHY
QSPI NOR (Boot device)
In addition, a wide range of interfaces are available at the main connector for use on the
carrier board as shown in Table 2-1 and Figure 2-1.
Table 2-1. Jetson Orin Module Interfaces
Category
Function
Category
Function
USB
USB 2.0 interface (3x)
LAN
Gigabit ethernet
USB 3.2 (3x). Note: SSD via USB 3.2 is
one option for storage.
I2C
4x
PCIe
PCIe (1 x1, 1 x2 or 2 x1, and 1 x4).
Note: NVMe via PCIe is one option for
storage.
UART
3x
Camera
CSI (8 lanes 2 x4 or 4 x2)
SPI
2x
Control, clock
CAN
1x
Display
HDMI/eDP/DP (1x)
Fan
FAN PWM and tach input
DP_AUX/HPD, CEC
Debug
UART
Audio
I2S interface (2x)
System
Power control, reset, alerts
Codec clock
Power
Main input and pin for optional battery
back-up for Real-Time Clock

Jetson Orin Module
PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 5
Figure 2-1. Jetson Orin Module Block Diagram
Jetson Orin Module
Gigabit
Ethernet
LPDDR5
VDD_IN USB 2.0 3x
GBE_MDI
I2S 2x
I2C 1x.8V
CSI: 2 x4 or 4 x2
[E]DP/HDMI 1x
USB 3.2 3x
SPI 2x
I2C 3xV
PCIe x1 + x2 + x4
CAM MCLK 2x
Power
Subsystem
CPU/GPU & Core Regs
Orin
VoltageMonitors
UART 3x
CAN 1x
AUDIO MCLK
QSPI NOR
General Purpose
Clocks2x
PWM 3x
DIGITAL MIC
Power Seq.
DP_AUX/DDC
HPD, CEC
PMIC_BBAT
NVMe for
Storage
SSD for
Storage
or
Table 2-2. Jetson Orin Module Connector 260-Pin SO-DIMM Pinout Matrix
Module Signal Name
Jetson Orin Module
Function
Pin #
Pin #
Module Signal Name
Jetson Orin Module
Function
GND
GND
1
2
GND
GND
CSI1_D0_N
CSI1_D0_N
3
4
CSI0_D0_N
CSI0_D0_N
CSI1_D0_P
CSI1_D0_P
5
6
CSI0_D0_P
CSI0_D0_P
GND
GND
7
8
GND
GND
CSI1_CLK_N
CSI1_CLK_N
9
10
CSI0_CLK_N
CSI0_CLK_N
CSI1_CLK_P
CSI1_CLK_P
11
12
CSI0_CLK_P
CSI0_CLK_P
GND
GND
13
14
GND
GND
CSI1_D1_N
CSI1_D1_N
15
16
CSI0_D1_N
CSI0_D1_N
CSI1_D1_P
CSI1_D1_P
17
18
CSI0_D1_P
CSI0_D1_P
GND
GND
19
20
GND
GND
CSI3_D0_N
CSI3_D0_N
21
22
CSI2_D0_N
CSI2_D0_N
CSI3_D0_P
CSI3_D0_P
23
24
CSI2_D0_P
CSI2_D0_P
GND
GND
25
26
GND
GND
CSI3_CLK_N
CSI3_CLK_N
27
28
CSI2_CLK_N
CSI2_CLK_N
CSI3_CLK_P
CSI3_CLK_P
29
30
CSI2_CLK_P
CSI2_CLK_P
GND
GND
31
32
GND
GND
CSI3_D1_N
CSI3_D1_N
33
34
CSI2_D1_N
CSI2_D1_N
CSI3_D1_P
CSI3_D1_P
35
36
CSI2_D1_P
CSI2_D1_P
GND
GND
37
38
GND
GND
DP0_TXD0_N
USBSS1_RX_N
39
40
CSI4_D2_N
PCIE2_RX0_N
DP0_TXD0_P
USBSS1_RX_P
41
42
CSI4_D2_P
PCIE2_RX0_P
GND
GND
43
44
GND
GND
DP0_TXD1_N
USBSS1_TX_N
45
46
CSI4_D0_N
PCIE2_TX0_N

Jetson Orin Module
PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 6
Module Signal Name
Jetson Orin Module
Function
Pin #
Pin #
Module Signal Name
Jetson Orin Module
Function
DP0_TXD1_P
USBSS1_TX_P
47
48
CSI4_D0_P
PCIE2_TX0_P
GND
GND
49
50
GND
GND
DP0_TXD2_N
USBSS2_RX_N
51
52
CSI4_CLK_N
PCIE2_CLK_N
DP0_TXD2_P
USBSS2_RX_P
53
54
CSI4_CLK_P
PCIE2_CLK_P
GND
GND
55
56
GND
GND
DP0_TXD3_N
USBSS2_TX_N
57
58
CSI4_D1_N
PCIE2_RX1_N
(PCIE3_RX0_N)
DP0_TXD3_P
USBSS2_TX_P
59
60
CSI4_D1_P
PCIE2_RX1_P
(PCIE3_TX0_P)
GND
GND
61
62
GND
GND
DP1_TXD0_N
DP1_TXD0_N
63
64
CSI4_D3_N
PCIE2_TX1_N
(PCIE3_TX0_N)
DP1_TXD0_P
DP1_TXD0_P
65
66
CSI4_D3_P
PCIE2_TX1_P
(PCIE3_TX0_P)
GND
GND
67
68
GND
GND
DP1_TXD1_N
DP1_TXD1_N
69
70
DSI_D0_N
RSVD
DP1_TXD1_P
DP1_TXD1_P
71
72
DSI_D0_P
RSVD
GND
GND
73
74
GND
GND
DP1_TXD2_N
DP1_TXD2_N
75
76
DSI_CLK_N
RSVD
DP1_TXD2_P
DP1_TXD2_P
77
78
DSI_CLK_P
RSVD
GND
GND
79
80
GND
GND
DP1_TXD3_N
DP1_TXD3_N
81
82
DSI_D1_N
RSVD
DP1_TXD3_P
DP1_TXD3_P
83
84
DSI_D1_P
RSVD
GND
GND
85
86
GND
GND
GPIO00
GPIO00
87
88
DP0_HPD
RSVD
SPI0_MOSI
SPI0_MOSI
89
90
DP0_AUX_N
RSVD
SPI0_SCK
SPI0_SCK
91
92
DP0_AUX_P
RSVD
SPI0_MISO
SPI0_MISO
93
94
HDMI_CEC
HDMI_CEC
SPI0_CS0*
SPI0_CS0*
95
96
DP1_HPD
DP1_HPD
SPI0_CS1*
SPI0_CS1*
97
98
DP1_AUX_N
DP1_AUX_N
UART0_TXD
UART0_TXD
99
100
DP1_AUX_P
DP1_AUX_P
UART0_RXD
UART0_RXD
101
102
GND
GND
UART0_RTS*
UART0_RTS*
103
104
SPI1_MOSI
SPI1_MOSI
UART0_CTS*
UART0_CTS*
105
106
SPI1_SCK
SPI1_SCK
GND
GND
107
108
SPI1_MISO
SPI1_MISO
USB0_D_N
USB0_D_N
109
110
SPI1_CS0*
SPI1_CS0*
USB0_D_P
USB0_D_P
111
112
SPI1_CS1*
SPI1_CS1*
GND
GND
113
114
CAM0_PWDN
CAM0_PWDN
USB1_D_N
USB1_D_N
115
116
CAM0_MCLK
CAM0_MCLK
USB1_D_P
USB1_D_P
117
118
GPIO01
GPIO01
GND
GND
119
120
CAM1_PWDN
CAM1_PWDN
USB2_D_N
USB2_D_N
121
122
CAM1_MCLK
CAM1_MCLK
USB2_D_P
USB2_D_P
123
124
GPIO02
GPIO02
GND
GND
125
126
GPIO03
GPIO03
GPIO04
GPIO04
127
128
GPIO05
GPIO05
GND
GND
129
130
GPIO06
GPIO06
PCIE0_RX0_N
PCIE0_RX0_N
131
132
GND
GND
PCIE0_RX0_P
PCIE0_RX0_P
133
134
PCIE0_TX0_N
PCIE0_TX0_N
GND
GND
135
136
PCIE0_TX0_P
PCIE0_TX0_P
PCIE0_RX1_N
PCIE0_RX1_N
137
138
GND
GND
PCIE0_RX1_P
PCIE0_RX1_P
139
140
PCIE0_TX1_N
PCIE0_TX1_N
GND
GND
141
142
PCIE0_TX1_P
PCIE0_TX1_P
CAN_RX
CAN_RX
143
144
GND
GND
KEY
KEY
KEY
KEY
KEY
KEY

Jetson Orin Module
PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 7
Module Signal Name
Jetson Orin Module
Function
Pin #
Pin #
Module Signal Name
Jetson Orin Module
Function
CAN_TX
CAN_TX
145
146
GND
GND
GND
GND
147
148
PCIE0_TX2_N
PCIE0_TX2_N
PCIE0_RX2_N
PCIE0_RX2_N
149
150
PCIE0_TX2_P
PCIE0_TX2_P
PCIE0_RX2_P
PCIE0_RX2_P
151
152
GND
GND
GND
GND
153
154
PCIE0_TX3_N
PCIE0_TX3_N
PCIE0_RX3_N
PCIE0_RX3_N
155
156
PCIE0_TX3_P
PCIE0_TX3_P
PCIE0_RX3_P
PCIE0_RX3_P
157
158
GND
GND
GND
GND
159
160
PCIE0_CLK_N
PCIE0_CLK_N
USBSS_RX_N
USBSS0_RX_N
161
162
PCIE0_CLK_P
PCIE0_CLK_P
USBSS_RX_P
USBSS0_RX_P
163
164
GND
GND
GND
GND
165
166
USBSS_TX_N
USBSS0_TX_N
PCIE1_RX0_N
PCIE1_RX0_N
167
168
USBSS_TX_P
USBSS0_TX_P
PCIE1_RX0_P
PCIE1_RX0_P
169
170
GND
GND
GND
GND
171
172
PCIE1_TX0_N
PCIE1_TX0_N
PCIE1_CLK_N
PCIE1_CLK_N
173
174
PCIE1_TX0_P
PCIE1_TX0_P
PCIE1_CLK_P
PCIE1_CLK_P
175
176
GND
GND
GND
GND
177
178
MOD_SLEEP*
MOD_SLEEP*
PCIE_WAKE*
PCIE_WAKE*
179
180
PCIE0_CLKREQ*
PCIE0_CLKREQ*
PCIE0_RST*
PCIE0_RST*
181
182
PCIE1_CLKREQ*
PCIE1_CLKREQ*
PCIE1_RST*
PCIE1_RST*
183
184
GBE_MDI0_N
GBE_MDI0_N
I2C0_SCL
I2C0_SCL
185
186
GBE_MDI0_P
GBE_MDI0_P
I2C0_SDA
I2C0_SDA
187
188
GBE_LED_LINK
GBE_LED_LINK
I2C1_SCL
I2C1_SCL
189
190
GBE_MDI1_N
GBE_MDI1_N
I2C1_SDA
I2C1_SDA
191
192
GBE_MDI1_P
GBE_MDI1_P
I2S0_DOUT
I2S0_DOUT
193
194
GBE_LED_ACT
GBE_LED_ACT
I2S0_DIN
I2S0_DIN
195
196
GBE_MDI2_N
GBE_MDI2_N
I2S0_FS
I2S0_FS
197
198
GBE_MDI2_P
GBE_MDI2_P
I2S0_SCLK
I2S0_SCLK
199
200
GND
GND
GND
GND
201
202
GBE_MDI3_N
GBE_MDI3_N
UART1_TXD
UART1_TXD
203
204
GBE_MDI3_P
GBE_MDI3_P
UART1_RXD
UART1_RXD
205
206
GPIO07
GPIO07
UART1_RTS*
UART1_RTS*
207
208
GPIO08
GPIO08
UART1_CTS*
UART1_CTS*
209
210
CLK_32K_OUT
CLK_32K_OUT
GPIO09
GPIO09
211
212
GPIO10
GPIO10
CAM_I2C_SCL
CAM_I2C_SCL
213
214
FORCE_RECOVERY*
FORCE_RECOVERY*
CAM_I2C_SDA
CAM_I2C_SDA
215
216
GPIO11
GPIO11
GND
MODULE_ID
217
218
GPIO12
GPIO12
SDMMC_DAT0
PCIE2_RST*
219
220
I2S1_DOUT
I2S1_DOUT
SDMMC_DAT1
PCIE2_CLKREQ*
221
222
I2S1_DIN
I2S1_DIN
SDMMC_DAT2
PCIE3_RST*
223
224
I2S1_FS
I2S1_FS
SDMMC_DAT3
PCIE3_CLKREQ*
225
226
I2S1_SCLK
I2S1_SCLK
SDMMC_CMD
PCIE3_CLK_N
227
228
GPIO13
GPIO13
SDMMC_CLK
PCIE3_CLK_P
229
230
GPIO14
GPIO14
GND
GND
231
232
I2C2_SCL
I2C2_SCL
SHUTDOWN_REQ*
SHUTDOWN_REQ*
233
234
I2C2_SDA
I2C2_SDA
PMIC_BBAT
PMIC_BBAT
235
236
UART2_TXD
UART2_TXD
POWER_EN
POWER_EN
237
238
UART2_RXD
UART2_RXD
SYS_RESET*
SYS_RESET*
239
240
SLEEP/WAKE*
SLEEP/WAKE*
GND
GND
241
242
GND
GND
GND
GND
243
244
GND
GND
GND
GND
245
246
GND
GND
GND
GND
247
248
GND
GND
GND
GND
249
250
GND
GND

Jetson Orin Module
PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 8
Module Signal Name
Jetson Orin Module
Function
Pin #
Pin #
Module Signal Name
Jetson Orin Module
Function
VDD_IN
VDD
251
252
VDD_IN
VDD
VDD_IN
VDD
253
254
VDD_IN
VDD
VDD_IN
VDD
255
256
VDD_IN
VDD
VDD_IN
VDD
257
258
VDD_IN
VDD
VDD_IN
VDD
259
260
VDD_IN
VDD
Legend
Ground
Power
Function Significantly Different than Module Pin Name Implies

PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 9
Chapter 3. Jetson Orin Module Boot
Considerations
The Jetson Orin Module can boot in two ways:
QSPI normal operation
USB Recovery Mode development and production programming
3.1 QSPI Boot MB of storage is
not expected to contain all the files for a fully functioning system. Secondary storage must be
provided. Support is available for the following configurations.
NVMe through PCIe
•PCIE0, x4 (Orin UPHY0 Lanes [7:4]), C4
•PCIE2, x2 (Orin UPHY2 Lanes 1:0]), C7
•PCIE2, x1 (Orin UPHY2 L0), C7
•PCIE3, x1 (Orin UPHY2 L1), C9
SSD through USB 3.2
•USB 3.2 Port 0, 1, or 2
3.2 USB Recovery Mode
USB Recovery mode provides an alternate boot device (USB). In this mode, the system is
connected to a host system and boots over USB. This is used when a new image needs to be
flashed. To enter USB recovery mode, the FORCE_RECOVERY* pin is held low when SYS_RESET*
goes high which can be when the system is powered on or SYS_RESET* is asserted after the
system is powered on. FORCE_RECOVERY* is the SoC RCM0 strap Only USB0_D_N/P supports USB
Recovery Mode