Nvidia JETSON NANO Guide

DG-09502-001_v2.1 | July 2020
NVIDIA Jetson Nano
Product Design Guide

NVIDIA Jetson Nano DG-09502-001_v2.1 | ii
DocumentHistory
DG-09502-001_v2.1
Version
Date
Description of Change
1.0 June 7, 2019 Initial Release
2.0 March2, 2020 • Added MPIOpad code and POR columnsto the pin description
tables through the design guide
•Added chapter on modular connector (Chapter 3)
•Updated power down figures (Figure 4-4 and Figure 4-5)
•Updated Figure 5-1 to show details of FET used as level shifter
for VBUS Detect to show it is inverted.
•Corrected USB2 module pin numbers in Figure 5-1
•Corrected PCIE0_TX3/RX0pin numbers in Figure 5-7
•Updated the notes to the PCIe signal routing requirements
table (Table 5-9)
•Updated Gigabit Ethernet controller in Section 5.3
•Updated Figure 7-1 to “4 Lanes…”
2.1 July 1, 2020 •Added Chapter 3 “DeveloperKitFeature Considerations”
•Updated notes forall pin description tables
•Corrected module pin numbers in Figure 7-2
•Updated Table 9-1 include both 1.8V and 3.3V pins, since the
pins are associated with a rail that may be set to one or the
other voltage
•Updated Figure 9-1 to change SDMMC_SD to connect to
genericGPIO
•Removed GPIO08 forSD Card Detect from Table 9-3 since
figure shows generic GPIO
•Updated Table 11-6to mention buffer on module
•The Jetson Nano pin description and design checklist are now
attachments to this design guide

NVIDIA Jetson Nano DG-09502-001_v2.1 | iii
Table of Contents
Chapter1. Introduction...................................................................................................1
1.1 References ............................................................................................................1
1.2 Abbreviations and Definitions..................................................................................2
Chapter2. Jetson Nano...................................................................................................4
Chapter3. Developer Kit Feature Considerations............................................................7
3.1 USB SuperSpeed Hub.............................................................................................7
3.2 Power Over Ethernet (PoE) .....................................................................................7
3.3 TI TXB0108 Level Shifters .......................................................................................8
3.4 Features Not to be Implemented ............................................................................8
Chapter4. Modular Connector........................................................................................9
4.1 Module Connector Details ......................................................................................9
4.2 Module to Mounting Hardware................................................................................9
4.3 Module Installation and Removal ..........................................................................10
Chapter5. Power..........................................................................................................11
5.1 Power Supply and Sequencing ..............................................................................12
Chapter6. USB and PCI Express....................................................................................15
6.1 USB.....................................................................................................................17
6.1.1 USB 2.0 Design Guidelines............................................................................18
6.1.2 USB 3.0 Design Guidelines............................................................................18
6.1.3 Common USB Routing Guidelines .................................................................21
6.2 PCIe.....................................................................................................................22
6.2.1 PCIe Design Guidelines.................................................................................23
6.3 Gigabit Ethernet ...................................................................................................26
Chapter7. Display.........................................................................................................28
7.1 MIPI DSI...............................................................................................................28
7.1.1 MIPI DSI and CSI Design Guidelines ..............................................................30
7.1.2 MIPI DSI and CSI Connection Guidelines........................................................30
7.2 eDP and DP .........................................................................................................31
7.2.1 eDP Routing Guidelines ................................................................................33
7.3 HDMI and DP .......................................................................................................36
7.3.1 HDMI............................................................................................................37
7.3.2 DP on DP1 Pins ............................................................................................44
7.3.2.1 DP Interface Signal Routing Requirements...............................................45
Chapter8. MIPI CSI Video Input.....................................................................................46
8.1 CSI Design Guidelines ..........................................................................................50

NVIDIA Jetson Nano DG-09502-001_v2.1 | iv
Chapter9. SD Card and SDIO.........................................................................................51
Chapter 10. Audio ...........................................................................................................54
Chapter 11. Miscellaneous Interfaces .............................................................................57
11.1 I2C.......................................................................................................................57
11.1.1 I2C Design Guidelines...................................................................................58
11.2 SPI ......................................................................................................................59
11.2.1 SPI Design Guidelines...................................................................................61
11.3 UART ...................................................................................................................62
11.4 Fan......................................................................................................................63
11.5 Debug..................................................................................................................64
11.5.1 JTAG ............................................................................................................65
11.5.2 Debug UART.................................................................................................66
Chapter 12. PADS ...........................................................................................................67
12.1 Internal Pull-ups for Dual-Voltage Block Pins Powered at 1.8V..............................67
12.2 Schmitt Trigger Usage..........................................................................................67
12.3 Pins Pulled and Driven High During Power-ON .....................................................68
Chapter 13. Unused Interface Terminations....................................................................69
13.1 Unused Multi-purpose Standard CMPS Pad Interfaces..........................................69
Chapter 14. Jetson Nano Pin Descriptions and Design Checklist......................................70
Chapter 15. General Routing Guidelines..........................................................................71
15.1 Signal Name Conventions.....................................................................................71
15.2 Routing Guideline Format.....................................................................................72
15.3 Signal Routing Conventions..................................................................................72
15.4 General Routing Guidelines ..................................................................................72
15.5 General PCB Routing Guidelines...........................................................................73
15.6 Common High-Speed Interface Requirements ......................................................74

NVIDIA Jetson Nano DG-09502-001_v2.1 | v
List of Figures
Figure 2-1. Jetson Nano Block Diagram..........................................................................5
Figure 4-1. Jetson Nano Module Installed in SODIMM Connector...................................10
Figure 4-2. Module to Connector Assembly Diagram.....................................................10
Figure 5-1. Jetson Nano Power and Control Block Diagram...........................................12
Figure 5-2. System Power and Control Block Diagram ..................................................13
Figure 5-3. Power Up Sequence....................................................................................13
Figure 5-4. Power Down – Initiated by SHUTDOWN_REQ* Assertion) .............................13
Figure 5-5. Power Down – Sudden Power Loss..............................................................14
Figure 6-1. USB Connection Example............................................................................17
Figure 6-2. IL/NEXT Plot...............................................................................................20
Figure 6-3. Trace Spacing for TX/RX Non-Interleaving ...................................................20
Figure 6-4. Via Structures.............................................................................................20
Figure 6-5. ESD Layout Recommendations....................................................................21
Figure 6-6. Component Order .......................................................................................21
Figure 6-7. Example PCIe Connections .........................................................................23
Figure 6-8. AC Cap Voiding ...........................................................................................25
Figure 6-9. Jetson Nano Ethernet Connections .............................................................26
Figure 6-10. Gigabit Ethernet Magnetics and RJ45 Connections.......................................27
Figure 7-1. DSI 1 x 2 Lane Connection Example.............................................................29
Figure 7-2. DP/eDP Connection Example on DP0 Pins...................................................32
Figure 7-3. eDP Differential Main Link Topology............................................................33
Figure 7-4. S-parameter...............................................................................................35
Figure 7-5. Via Topology #1 ..........................................................................................35
Figure 7-6. Via Topology #2 ..........................................................................................35
Figure 7-7. HDMI Connection Example..........................................................................37
Figure 7-8. HDMI Clk and Data Topology.......................................................................38
Figure 7-9. IL and FEXT Plot.........................................................................................41
Figure 7-10. TDR Plot.....................................................................................................41
Figure 7-11. HDMI Via Topology......................................................................................41
Figure 7-12. Add-on Components – T op ..........................................................................41
Figure 7-13. Add-on Components – Bottom ....................................................................42
Figure 7-14. AC Cap Void................................................................................................42
Figure 7-15. RPD, Choke, FET Placement.......................................................................42
Figure 7-16. ESD Footprint.............................................................................................42
Figure 7-17. ESD Void.....................................................................................................42
Figure 7-18. SMT Pad Trace Entering..............................................................................43
Figure 7-19. SMT Pad Trace Between .............................................................................43

NVIDIA Jetson Nano DG-09502-001_v2.1 | vi
Figure 7-20. Connector Voiding.......................................................................................43
Figure 7-21. DP Connection Example..............................................................................44
Figure 8-1. 4 Lane CSI Camera Connection Example.....................................................48
Figure 8-2. Available Cameral Control Pins...................................................................49
Figure 8-3. CSI Connection Options...............................................................................49
Figure 9-1. SD Card Connection Example......................................................................52
Figure 10-1. Audio Codec Connection Example ...............................................................55
Figure 11-1. I2C Connections..........................................................................................58
Figure 11-2. SPI Connections .........................................................................................60
Figure 11-3. Basic SPI Master and Slave Connections .....................................................60
Figure 11-4. SPI Topologies............................................................................................61
Figure 11-5. Jetson Nano UART Connections..................................................................62
Figure 11-6. Jetson Nano Fan Connections.....................................................................64
Figure 11-7. JTAG and Debug UART Connections............................................................65
Figure 11-8. JTAG Test Point Detail ................................................................................65
Figure 15-1. GSSG Stack-Up...........................................................................................73
Figure 15-2. Common Mode Choke.................................................................................75
Figure 15-3. Serpentine..................................................................................................75

NVIDIA Jetson Nano DG-09502-001_v2.1 | vii
List of Tables
Table 1-1. Abbreviations and Definitions ........................................................................2
Table 2-1. Jetson Nano Interfaces.................................................................................4
Table 2-2. Jetson Nano Connector Pinout Matrix ...........................................................5
Table 5-1. Jetson Nano Power and System Pin Descriptions ........................................11
Table 6-1. Jetson Nano USB 2.0 Pin Descriptions.........................................................15
Table 6-2. Jetson Nano USB 3.0 and PCIe Pin Descriptions..........................................15
Table 6-3. Jetson Nano USB 3.0 and PCIe Lane Mapping Configurations.......................16
Table 6-4. USB 2.0 Interface Signal Routing Requirements...........................................18
Table 6-5. USB 3.0 Interface Signal Routing Requirements...........................................18
Table 6-6. Tegra USB 2.0 Signal Connections...............................................................21
Table 6-7. Miscellaneous USB 2.0 Signal Connections..................................................22
Table 6-8. Tegra USB 3.0 Signal Connections...............................................................22
Table 6-9. PCIe Interface Signal Routing Requirements ...............................................23
Table 6-10. PCIe Signal Connections.............................................................................25
Table 6-11. Jetson Nano Gigabit Ethernet Pin Description..............................................26
Table 6-12. Ethernet MDI Interface Signal Routing Requirements ..................................27
Table 6-13. Ethernet Signal Connections.......................................................................27
Table 7-1. Jetson Nano Display General Pin Description ..............................................28
Table 7-2. Jetson Nano DSI Pin Description.................................................................29
Table 7-3. MIPI DSI and CSI Interface Signal Routing Requirements.............................30
Table 7-4. MIPI DSI Signal Connections.......................................................................30
Table 7-5. Jetson Nano eDP and DP Pin Description....................................................31
Table 7-6. eDP and DP Main Link Signal Routing Requirements including DP_AUX.......33
Table 7-7. eDP Signal Connections..............................................................................35
Table 7-8. Jetson Nano HDMI and DP Pin Description..................................................36
Table 7-9. DP and HDMI Pin Mapping..........................................................................36
Table 7-10. HDMI Interface Signal Routing Requirements..............................................38
Table 7-11. HDMI Signal Connections............................................................................43
Table 7-12. DP Signal Connections................................................................................45
Table 8-1. Jetson Nano CSI Pin Description.................................................................46
Table 8-2. Jetson Nano Camera Miscellaneous Pin Description....................................47
Table 8-3. CSI Configuration........................................................................................48
Table 8-4. MIPI CSI Signal Connections .......................................................................50
Table 8-5. Miscellaneous Camera Connections............................................................50
Table 9-1. Jetson Nano SDIO Pin Description...............................................................51
Table 9-2. SD Card and SDIO Interface Signal Routing Requirements...........................52
Table 9-3. SD Card and SDIO Signal Connections.........................................................53

NVIDIA Jetson Nano DG-09502-001_v2.1 | viii
Table 10-1. Jetson Nano Audio Pin Description..............................................................54
Table 10-2. Interface Signal Routing Requirements .......................................................56
Table 10-3. Audio Signal Connections............................................................................56
Table 11-1. Jetson Nano I2C Pin Description .................................................................57
Table 11-2. I2C Interface Signal Routing Requirements..................................................59
Table 11-3. I2C Signal Connections ...............................................................................59
Table 11-4. Jetson Nano SPI Pin Description.................................................................59
Table 11-5. SPI Interface Signal Routing Requirements .................................................61
Table 11-6. Jetson Nano UART Pin Description..............................................................62
Table 11-7. UART Signal Connections............................................................................63
Table 11-8. Jetson Nano Fan Pin Description.................................................................63
Table 11-9. Jetson Nano JTAG and Debug UART Description..........................................64
Table 11-10. JTAG Connections.......................................................................................66
Table 11-11. Debug UART Connections ...........................................................................66
Table 12-1. Pins Pulled and Driven High by Tegra Prior to SYS_RESET* Inactive.............68
Table 12-2. Pins Pulled High on Module with External Resistors Prior to SYS_RESET_IN*
Inactive.......................................................................................................68
Table 13-1. Unused MPIO Pins and Pin Groups..............................................................69
Table 15-1. Signal Type Codes.......................................................................................71
Table 15-2. Common High-Speed Interface Requirements.............................................74

NVIDIA Jetson Nano DG-09502-001_v2.1 | 1
Chapter 1. Introduction
This design guide contains recommendations and guidelines for engineers to follow in
creating a product that is optimized to achieve the best performance from the common
interfaces supported by the NVIDIA®Jetson Nano™System-on-Module (SOM).
This design guide provides detailed information on the capabilities of the hardware module,
which may differ from supported configurations by provided software. Refer to software
release documentation for information on supported capabilities.
Note: Mostof the interface usage noted in this designguide is based onthe NVIDIA developerkit
carrier board design.
1.1 References
Refer to the following list of documents or models for more information. Always use the latest
revision of all documents.

Jetson Nano Module Data Sheet
 Tegra X1 (SoC) Technical Reference Manual
 Jetson Nano Developer Kit Carrier Board Specification
 Jetson Nano Module Pinmux
 Jetson Nano Thermal Design Guide
 Jetson Nano Developer Kit Carrier Board Design Files
 Jetson Nano Developer KIt Carrier Board BOM
 Jetson Nano SCL (Supported Component List)

Introduction
NVIDIA Jetson Nano DG-09502-001_v2.1 | 2
1.2 Abbreviations and Definitions
Table 1-1 lists abbreviations that may be used throughout this document and their definitions.
Table 1-1. Abbreviations and Definitions
Abbreviation
Definition
CEC Consumer Electronic Control
CSI Camera Serial Interface
Diff Differential
DP VESA®DisplayPort™(output)
DSI Display Serial Interface
eDP Embedded DisplayPort
ESD Electrostatic Discharge
eMMC Embedded MMC
EMI Electromagnetic Interference
FET Field Effect Transistor
GPIO General Purpose Input Output
HDCP High-bandwidth Digital Content Protection
HDMI™High Definition Multimedia Interface
I2C InterIC Interface
I2S Inter IC Sound Interface
LCD Liquid Crystal Display
LDO Low Dropout(voltage regulator)
LPDDR4 Low Power Double Data Rate DRAM, Fourth generation
MDI Medium-Dependent Interface
MIL 1/1000th of an inch
MIPI Mobile Industry Processor Interface
mm Millimeter
PCIe Peripheral Component Interconnect Express interface
PCM Pulse Code Modulation
PHY Physical Interface (i.e.USB PHY)
ps Pico-Seconds
PMU Power Management Unit
RJ45 8P8C modular connector used in Ethernet and other data
links
RTC Real Time Clock

Introduction
NVIDIA Jetson Nano DG-09502-001_v2.1 | 3
Abbreviation
Definition
SD Card Secure Digital Card
SDIO Secure Digital I/O Interface
SE
Single-Ended
SPI Serial Peripheral Interface
TMDS Transition-minimized differential signaling
UART Universal Asynchronous Receiver-Transmitter
USB Universal Serial Bus

NVIDIA Jetson Nano DG-09502-001_v2.1 | 4
Chapter 2. Jetson Nano
The Jetson Nano resides at the center of the embedded system solution and includes the
following:
Power (PMIC/Regulators, etc.)
DRAM (LPDDR4)
eMMC
Gigabit Ethernet Controller
Power Monitor
In addition, a wide range of interfaces are available at the main connector for use on the
carrier board as shown Table 2-1 and Figure 2-1.
Table 2-1. Jetson Nano Interfaces
Category
Function
Category
Function
USB USB 2.0 Interface (3x) LAN Gigabit Ethernet
USB 3.0 (1x) I2C 4x
PCIe PCIe (x1/2/4) UART 3x
Camera CSI (3 x4 or 2 x4 + 2 x2 or 1 x4 + 3 x2), Control,
Clock
SPI 2x
Display
eDP/DP (see Note 1) Wi-Fi/BT/Modem PCIe/UART/I2S, Control/handshake
HDMI/DP Interface (w/CEC) Fan FAN PWM and Tach Input
DSI (1, 2-lane), Display/Backlight Control Debug JTAG test points on module and UART
Audio I2S Interface (2x) and Clock System Power Control, Reset, alerts
SD Card/SDIO SD Card or SDIO Interface (1x) Power Main Input and battery back-up for RTC
Note: DP on eDP interface does not support HDCP or Audio

Jetson Nano
NVIDIA Jetson Nano DG-09502-001_v2.1 | 5
Figure 2-1. Jetson Nano Block Diagram
Jetson Nano
Giga bit
Ethernet
LPDDR4
4GB
eMMC
16GB
3.3V Pre-
Reg
VDD_IN USB 2.0 x3
GBE_M DI
AUDIO MCLK
I2S x2
I2C x1–1.8V
CSI: 3 x4 or
2 x4 + 2 x2 or
1 x4 + 3 x2 or
4 x2
eDP/DP
1
SD CARD/SDIO
USB 3.0 x1
SPI x2
I2C x3–3.3V
DSI, 2-lane x1
PCIe x4
CAM MCLK x2
Powe r
Subs ystem
PMIC MAX77 620
CPU Reg uP1666Q
GPU Reg uP1666Q
Tegra X1
Po wer Mon itor
Un der-Voltage Mo nit or
UART x3
DP_AUX/DDC
HPD x2, CEC
DP/HDMI
JTAG Test Points
Note:
1
DP on eDP interface does notsupport HDCP or Audio
Table 2-2 lists the 260-pin SO-DIM description for the Jetson Nano connector.
Table 2-2. Jetson Nano Connector Pinout Matrix
Module Signal Name
Pin #
Pin #
Module Signal Name
Module Signal Name
Pin #
Pin #
Module Signal Name
GND
1
2
GND
PCIE0RX0P
133
134
PCIE0TX0N
CSI1D0N
3
4
CSI0D0N
GND
135
136
PCIE0TX0P
CSI1D0P
5
6
CSI0D0P
PCIE0RX1N
137
138
GND
GND
7
8
GND
PCIE0RX1P
139
140
PCIE0TX1N
RSVD
9
10
CSI0 CLK N
GND
141
142
PCIE0TX1P
RSVD
11
12
CSI0 CLK P
RSVD
143
144
GND
GND
13
14
GND
KEY
KEY
KEY
KEY
CSI1D1N
15
16
CSI0D1N
RSVD
145
146
GND
CSI1D1P
17
18
CSI0D1P
GND
147
148
PCIE0TX2N
GND
19
20
GND
PCIE0RX2N
149
150
PCIE0TX2P
CSI3D0N
21
22
CSI2D0N
PCIE0RX2P
151
152
GND
CSI3D0P
23
24
CSI2D0P
GND
153
154
PCIE0TX3N
GND
25
26
GND
PCIE0RX3N
155
156
PCIE0TX3P
CSI3 CLK N
27
28
CSI2 CLK N
PCIE0RX3P
157
158
GND
CSI3 CLK P
29
30
CSI2 CLK P
GND
159
160
PCIE0 CLK N
GND
31
32
GND
USBSS RX N
161
162
PCIE0 CLK P
CSI3D1N
33
34
CSI2D1N
USBSS RX P
163
164
GND
CSI3D1P
35
36
CSI2D1P
GND
165
166
USBSS TX N
GND
37
38
GND
RSVD
167
168
USBSS TX P
DP0 TXD0 N
39
40
CSI4D2N
RSVD
169
170
GND
DP0 TXD0 P
41
42
CSI4D2P
GND
171
172
RSVD

Jetson Nano
NVIDIA Jetson Nano DG-09502-001_v2.1 | 6
Module Signal Name
Pin #
Pin #
Module Signal Name
Module Signal Name
Pin #
Pin #
Module Signal Name
GND
43
44
GND
RSVD
173
174
RSVD
DP0 TXD1 N
45
46
CSI4D0N
RSVD
175
176
GND
DP0 TXD1 P
47
48
CSI4D0P
GND
177
178
MOD SLEEP*
GND
49
50
GND
PCIE WAKE*
179
180
PCIE0 CLKREQ*
DP0 TXD2 N
51
52
CSI4 CLK N
PCIE0 RST*
181
182
RSVD
DP0 TXD2 P
53
54
CSI4 CLK P
RSVD
183
184
GBE MDI0 N
GND
55
56
GND
I2C0 SCL
185
186
GBE MDI0 P
DP0 TXD3 N
57
58
CSI4D1N
I2C0 SDA
187
188
GBE LED LINK
DP0 TXD3 P
59
60
CSI4D1P
I2C1 SCL
189
190
GBE MDI1 N
GND
61
62
GND
I2C1 SDA
191
192
GBE MDI1 P
DP1 TXD0 N
63
64
CSI4D3N
I2S0 DOUT
193
194
GBE LED ACT
DP1 TXD0 P
65
66
CSI4D3P
I2S0 DIN
195
196
GBE MDI2 N
GND
67
68
GND
I2S0 FS
197
198
GBE MDI2 P
DP1 TXD1 N
69
70
DSI D0 N
I2S0 SCLK
199
200
GND
DP1 TXD1 P
71
72
DSI D0 P
GND
201
202
GBE MDI3 N
GND
73
74
GND
UART1 TXD
203
204
GBE MDI3 P
DP1 TXD2 N
75
76
DSI CLK N
UART1 RXD
205
206
GPIO07
DP1 TXD2 P
77
78
DSI CLK P
UART1 RTS*
207
208
GPIO08
GND
79
80
GND
UART1 CTS*
209
210
CLK 32K OUT
DP1 TXD3 N
81
82
DSI D1 N
GPIO09
211
212
GPIO10
DP1_TXD3_P
83
84
DSI_D1_P
CAM_I2C_SCL
213
214
FORCE_ RECOVERY*
GND
85
86
GND
CAM I2C SDA
215
216
GPIO11
GPIO00
87
88
DP0 HPD
GND
217
218
GPIO12
SPI0 MOSI
89
90
DP0 AUX N
SDMMC DAT0
219
220
I2S1 DOUT
SPI0 SCK
91
92
DP0 AUX P
SDMMC DAT1
221
222
I2S1 DIN
SPI0_MISO
93
94
HD MI_CEC
SDMMC_DAT2
223
224
I2S1_FS
SPI0 CS0*
95
96
DP1 HPD
SDMMC DAT3
225
226
I2S1 SCLK
SPI0 CS1*
97
98
DP1 AUX N
SDMMC CMD
227
228
GPIO13
UART0 TXD
99
100
DP1 AUX P
SDMMC CLK
229
230
GPIO14
UART0 RXD
101
102
GND
GND
231
232
I2C2 SCL
UART0 _RTS*
103
104
SPI1_MOSI
SH UTD OWN_REQ*
233
234
I2C2_SDA
UART0 CTS*
105
106
SPI1 SCK
PMIC BBAT
235
236
UART2 TXD
GND
107
108
SPI1 MISO
POWER EN
237
238
UART2 RXD
USB0 D N
109
110
SPI1 CS0*
SYS RESET*
239
240
SLEEP/ WAKE*
USB0 D P
111
112
SPI1 CS1*
GND
241
242
GND
GND
113
114
CAM0_PWDN
GND
243
244
GND
USB1_D_N
115
116
CAM0_MCLK
GND
245
246
GND
USB1 D P
117
118
GPIO01
GND
247
248
GND
GND
119
120
CAM1 PWDN
GND
249
250
GND
USB2 D N
121
122
CAM1 MCLK
VDD IN
251
252
VDD IN
USB2 D P
123
124
GPIO02
VDD IN
253
254
VDD IN
GND
125
126
GPIO03
VDD_IN
255
256
VDD_IN
GPIO04
127
128
GPIO05
VDD IN
257
258
VDD IN
GND
129
130
GPIO06
VDD IN
259
260
VDD IN
PCIE0RX0N
131
132
GND
Legend
Ground
Power
Reserved - must be left unconnected

NVIDIA Jetson Nano DG-09502-001_v2.1 | 7
Chapter 3. Developer Kit Feature
Considerations
The Jetson Nano Developer Kit Carrier Board design files are provided as a reference design.
This chapter describes details necessary for designers to know to replicate certain features if
desired. In addition, aspects of the design that are specific to the NVIDIA Developer Kit usage
but not useful or supported on a custom carrier board are also identified.
Most of the features implemented on the Jetson Nano Developer Kit carrier board design can
be duplicated by copying the connections from the P3449 carrier board reference design. The
Some features have aspects that would require additional information as listed
USB SuperSpeed Hub
Power over Ethernet (PoE)
TI TXB0108 level shifters
ID EEPROM (Not to be copied from reference design)
3.1 USB SuperSpeed Hub
The USB SS hub design uses a Realtek RTS5411S device. The hub device has been customized
using internal fuses with the Realtek tool. A design intending to duplicate the DevKit hub
implementation should customize the hub as follows:
Power enables (DPS1/2/3/4_PWR) set to be active high
Charging feature disabled
SSC valid
3.2 Power Over Ethernet (PoE)
The P3449 carrier board includes a 4-pin Power over Ethernet (PoE) header (J38) which brings
out the VC power pins of the Ethernet connector. In order to use this alternate PoE power
mechanism to power the carrier board, the design would require a power converter to take the
high voltage PoE supply (38V-60V) and convert it to the correct voltage for the custom carrier
board. This could be the 5V that the Jetson Nano DevKit uses, or a different voltage depending
on the design of the custom carrier board.

Developer Kit Feature Considerations
NVIDIA Jetson Nano DG-09502-001_v2.1 | 8
3.3 TI TXB0108 Level Shifters
The P3449 carrier board uses these level shifters to shift many of the signals going to the 40-
pin header from 1.8V to 3.3V. The design of these level shifters supports bidirectional signaling
without the use of a direction signal but has some side effects that should be considered. See
the
Jetson Nano Developer Kit 40-Pin Expansion Header GPIO Usage Considerations
Applications Note
for details.
3.4 Features Not to be Implemented
The Jetson Nano Developer Kit carrier board features that should not be copied as they are
not required or useful for a custom carrier board design. The ID EEPROM (P3449 - U11) is a
feature that is used for NVIDIA internal purposes, but not useful on a custom design. A similar
function may be desired for a custom design, but the NVIDIA software will not interact with
these devices and the I2C address used by the developer kit carrier board ID EEPROM on the
I2C2 interface (7’h57) should be avoided.

NVIDIA Jetson Nano DG-09502-001_v2.1 | 9
Chapter 4. Modular Connector
4.1 Module ConnectorDetails
Jetson Nano modules connect to the carrier board using a 260-pin SO-DIMM connector. The
mating connector used on the Developer Kit carrier board is listed in the Jetson Nano SCL
(Supported Components List). This connector is a DDR4 SODIMM, 260-pin, right-angle,
standard key type. The full height of the connector is 9.2 mm. Refer to the Connector
specification for details. Other heights are available.
4.2 Module to MountingHardware
The Jetson Nano module is installed in the SODIMM connector which has latching
mechanisms to hold the board in place. In addition, it is required that the module is mounted
to the main carrier board PCB using metal standoffs and screws (or equivalent), both for
mechanical integrity and to provide additional grounding points. The Developer Kit uses
threaded standoffs that are hex, 4.5 mm widths (narrow diameter) x 6.57 ± 0.1 mm length.
These have M.2.5 threads. The screws used are M2.5 x 3.7 mm, pad head.
Other SODIMM connector heights are available. If a different height connector is used, the
standoff height will have to be adjusted accordingly to account for the difference in height from
main PCB to module PCB.

Modular Connector
NVIDIA Jetson Nano DG-09502-001_v2.1 | 10
Figure 4-1. Jetson Nano Module Installed in SODIMM Connector
Standoffs
SO-DIMM
Connector
Jetson Nano
Module
(Envelop view)
Mounting Screws
4.3 Module Installation and Removal
To install the Jetson Nano module correctly, follow the sequence and mounting hardware
instructions:
Here are some suggested assembly guidelines.
1. Assemble any required thermal solution on the module.
2. Install the Jetson Nano module
a) Baseboard with suitable standoff for as per SODIMM connector height defined
b) Insert module fully at an angle of 25-35 degree into the SODIMM connector.
c) Arc down the module board until the SODIMM connector latch engages.
d) Secure the Jetson Nano module to the baseboard with screws into the standoff/spacer.
The Developer Kit (shown in Figure 4-2) uses a standoff and screws to secure the
module to the system/base- board.
Figure 4-2. Module to Connector Assembly Diagram
To remove the Jetson Nano module correctly, follow the reverse of the installation sequence.

NVIDIA Jetson Nano DG-09502-001_v2.1 | 11
Chapter 5. Power
Power for the module is supplied on the VDD_IN pins and is nominally 5.0V (see the Jetson
Nano Data Sheet
for supply tolerance and maximum current).
!
CAUTION: Jetson Nano is not hot-pluggable. When installing the module, the main power supply
should notbe connected. Before removingthe module,the main power supply (to VDD_IN pins)
must be disconnected and allowed to discharge below 0.6V.
Table 5-1. Jetson Nano Power and System Pin Descriptions
Pin # Module Pin Name Tegra X1 Signal Usage/Description
Usage on NVIDIA DevKit
Carrier Board
Direction Pin Type
MPIO Pad
Code
Power-on
Reset
251
↓
260
VDD_IN
−
Main power – Supplies PMIC and other
regulators
Main DC input
Input
5.0V
−
−
235 PMIC_BBAT −
PMIC Battery Back-up. Optionally used to
provide back-up power for the Real-Time-
Clock (RTC). Connects to Lithium Cell or super
capacitor on Carrier Board. PMIC is source
when charging cap or coin cell. Super cap or
coin cell is source when system is
disconnected from power.
Battery Back-up using
Super-capacitor Bidir 1.65V-5.5V
−
−
214
FORCE_
RECOVERY*
BUTTON_V OL_UP Force Recovery strap pin Automation header Input CMOS – 1.8V ST pu
240 SLEEP/WAKE* BUTTON_PWR_ON
Sleep/Wake. Configured as GPIO for optional
use to indicate the system should enter or exit
sleep mode.
Automation header Input CMOS – 5.0V ST pu
233 SHUTDOWN_REQ* −
Used by the module to request the carrier
board to shut down. 100kΩ pull-up to VDD_IN
(5V) on the module.
System Output Open Drain, 5.0V
−
−
237 POWER_EN (PMIC EN0 through
converter logic)
Signal for module on/off: high level on, low
level off. Connects to module PMIC EN0
through converter logic. 100kΩ pulldown on
the module.
System Input Analog 5.0V
−
−
239 SYS_RESET* SYS_RESET_IN_N
Module Reset. Reset to the module when
driven low by the carrier board. Used as
carrier board supply enable when driven high
by the module. when module power
sequence is complete. Used to ensure proper
power on/off sequencing for between module
and carrier board supplies. 4.7kΩ pull-up to
1.8V on the module.
Automation header Bidir Open Drain, 1.8V JT_RST 1
178 MOD_SLEEP* GPIO_PA6
Indicates the module sleep status. Low is in
sleep mode, high is normal operation. This pin
HDMI termination pull-
down FET control disable
Output CMOS – 1.8V ST z

Power
NVIDIA Jetson Nano DG-09502-001_v2.1 | 12
Pin # Module Pin Name Tegra X1 Signal Usage/Description
Usage on NVIDIA DevKit
Carrier Board
Direction Pin Type
MPIO Pad
Code
Power-on
Reset
is controlled by system software and should
not be modified.
Notes:
1. In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals.
2. The directions for FORCE_RECOVERY* and SLEEP/WAKE* signals are true when used for those functions. Otherwise as GPIOs, the
direction is bidirectional.
3. The MPIO Pad Codes are described in the Tegra X1 SoC Technical Reference Manual “Multi-Purpose I/O Pins and Pin Multiplexing
(PinMux)” section for details.
4. The Power-on Reset State column indicates the pin state when reset is active and when it is deactivated before any changes are made by
software. “z” is tristate, pu/pd indicates internal weak pull-up/down resistor is enabled, 1/0 indicates actively driven high/low.
Figure 5-1. Jetson Nano Power and Control Block Diagram
Jetson Nano
Main 5V
Power
Source
255
256
257
258
259
260
235
Memory/Peripherals
LPDDR4, eMMC,
Ethernet
Power Subsystem
Tegra X1
PMIC_BBAT
VDD_IN
233
240
239
237
POWER_EN
SYS_RESET*
SLEEP/WAKE*
MOD_SLEEP *
SHUTDOWN_REQ*
To Carrier Board – Used to force
power off if shutdown request
(T he rmal S hut down , P owe r B ad o r
Software Shutdown, etc.) is received
From Carrier Board power
ON/ OF F c ont r ol l o gic
System Reset from Carrier
Board. Carrier Board power
enable f rom Module.
Optional Sleep/Wake Button
SLE EP/W AK E
Super
Cap or
Li Cell
251
252
253
254
178
Indicates Module is entering
Sleep (LP0) mode
10 0k Ω4. 7kΩ
VDD_1V8
4. 7kΩ
VDD_1V8
10 0k Ω
VDD_1V8
Lev el
Shifter
10 0k Ω
VDD_IN (5V)
5.1 Power Supply and Sequencing
The carrier board receives the main power source and uses this to generate the enable to
Jetson Nano (POWER_EN) after the carrier board has ensured the main supply is stable and the
associated decoupling capacitors have charged. The carrier board supplies are not enabled at
this time. Once POWER_ENis driven active (high), Jetson Nano begins to Power-ON. When the
module Power-ON sequence has completed, the SYS_RESET* signal is driven inactive (high) and
this is used by the carrier board to enable its various supplies. SYS_RESET* is bidirectional and
can be driven by the carrier board to reset Jetson Nano, which results in a full system power
cycle. The SHUTDOWN_REQ* signal from Jetson Nano can be driven active (low) if the system
must be shut down, due to a critical thermal issue, etc. The power control logic on the carrier
board should drive POWER_EN inactive (low) if SHUTDOWN_REQ* is asserted. The SHUTDOWN_REQ*
signal is latched to a logic low level when the VDD_IN supply is at or below 4.2V.