NXP Semiconductors TFA9812 Instruction Manual

1. General description
The TFA9812 is a high-efficiency Bridge Tied Load (BTL) stereo Class-D audio amplifier
with a digital I2S audio input. It is available in a HVQFN48 package with exposed die
paddle. The exposed die paddle technology enhances the thermal and electrical
performances of the device.
The TFA9812 features digital sound processing and audio power amplification. It supports
I2C control mode and Legacy mode. In Legacy mode I2C involvement is not needed
because the key features are controlled by hardware pin connections.
A continuous time output power of 2 ×12W(R
L=8Ω,V DDP = 15 V) is supported without
an external heat sink. Due to the implementation of a programmable thermal foldback
even for high supply voltages, higher ambient temperatures, and/or lower load
impedances, the device operates without sound interrupting behavior.
TFA9812 is designed in such a way that it starts up easily (no special power-up sequence
required). It features various soft and hard impact protection mechanisms to ensure an
application that is both user friendly and robust.
A modulation technique is applied for the TFA9812, which supports common mode choke
approach (1 common mode choke only per BTL amplifier stage). This minimizes the
number of external components.
2. Features
2.1 General features
n3.3 V and 8 V to 20 V external power supply
nHigh efficiency and low power dissipation
nSpeaker outputs fully short circuit proof across load, to supply lines and ground
nPop noise free at power-up/power-down and sample rate switching
nLow power Sleep mode
nOvervoltage and undervoltage protection on the 8 V to 20 V power supply
nUndervoltage protection on the 3.3 V power supply
nOvercurrent protection (no audible interruptions)
nOverdissipation protection
nThermally protected and programmable thermal foldback
nClock error protection
nI2C mode control or Legacy mode (i.e. no I2C) control
nFour different I2C addresses supported
nInternal Phase-Locked Loop (PLL) without using external components
TFA9812
BTL stereo Class-D audio amplifier with I2S input
Rev. 02 — 22 January 2009 Preliminary data sheet

TFA9812_2 © NXP B.V. 2009. All rights reserved.
Preliminary data sheet Rev. 02 — 22 January 2009 2 of 66
NXP Semiconductors TFA9812
BTL stereo Class-D audio amplifier with I2S input
nNo high system clock required (PLL is able to lock on BCK)
nNo external heat sink required
n5 V tolerant digital inputs
nSupports dual coil inductor application
nEasy application and limited external components required
2.2 DSP features
nDigital parametric 10-band equalizer
nDigital volume control per channel
nSelectable +24 dB gain boost
nAnalog interface to digital volume control in Legacy mode
nDigital clip level control
nSoft and hard mute
nThermal foldback threshold temperature control
nDe-emphasis
nOutput power limiting control
nPolarity switch
nFour Pulse Width Modulation (PWM) switching frequency settings
2.3 Audio data input interface format support
nMaster or slave Master Clock (MCLK), Bit Clock (BCK) and Word Select (WS) signals
nPhilips I2S, standard I2S
nJapanese I2S, Most Significant Bit (MSB) justified
nSony I2S, Least Significant Bit (LSB) justified
nSample rates from 8 kHz to 192 kHz
3. Applications
nDigital-in Class-D audio amplifier applications
nCRT and flat-panel television sets
nFlat-panel monitors
nMultimedia systems
nWireless speakers
nDocking stations for MP3 players

TFA9812_2 © NXP B.V. 2009. All rights reserved.
Preliminary data sheet Rev. 02 — 22 January 2009 3 of 66
NXP Semiconductors TFA9812
BTL stereo Class-D audio amplifier with I2S input
4. Quick reference data
[1] IPis the current through the analog supply voltage (VDDA) pin added to the current through the power supply
voltage (VDDP) pin.
Table 1. Quick reference table
Unless specified otherwise, V
DDA
=V
DDP
=12V,V
SSP1
=V
SSP2
=0V,V
DDA(3V3)
=V
DDD(3V3)
= 3.3 V,
V
SS1
=V
SS2
= REFD = REFA = 0 V, T
amb
=25 ° C, R
L
=8 Ω ,f
i
= 1 kHz, f
s
= 44.1 kHz, f
sw
= 400 kHz,
24-bit I
2
S input data, MCLK clock mode, typical application diagram (Figure 13).
Symbol Parameter Conditions Min Typ Max Unit
General
VDDA analog supply
voltage 81220V
VDDP power supply
voltage 81220V
VDDA(3V3) analog supply
voltage (3.3 V) 3.0 3.3 3.6 V
VDDD(3V3) digital supply
voltage (3.3 V) 3.0 3.3 3.6 V
IPsupply current soft mute mode, with load,
filter and snubbers
connected
[1] -3845mA
sleep mode [1] - 160 270 µA
IDDA(3V3) analog supply
current (3.3 V) operating mode
I2S slave mode - 2 4 mA
I2S master mode - 4 6 mA
sleep mode
VDDA =V
DDP = 12 V - 120 - µA
VDDA =V
DDP = 1 V - 40 70 µA
IDDD(3V3) digital supply
current (3.3 V) operating mode
I2S slave mode - 15 25 mA
I2S master mode - 25 40 mA
sleep mode;
DATA = WS = BCK =
MCLK = 0 V
-430µA
Po(RMS) RMS output power Continuous time output power per channel; THD = 10 %;
RL=8Ω
VDDA = VDDP = 12 V - 8.3 - W
VDDA = VDDP = 13.5 V - 10 - W
VDDA = VDDP = 15 V - 12 - W
Short time (≤10 s) output power per channel; THD = 10 %;
RL=8Ω
VDDA = VDDP = 17 V - 15 - W
ηpo output power
efficiency RL=8Ω; Po(RMS) = 8.3 W - 88 - %

TFA9812_2 © NXP B.V. 2009. All rights reserved.
Preliminary data sheet Rev. 02 — 22 January 2009 4 of 66
NXP Semiconductors TFA9812
BTL stereo Class-D audio amplifier with I2S input
5. Ordering information
Table 2. Ordering information
Type number Package
Name Description Version
TFA9812HN HVQFN48 plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 7 ×7×0.85 mm SOT619-8

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
TFA9812_2 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 02 — 22 January 2009 5 of 66 NXP Semiconductors TFA9812
BTL stereo Class-D audio amplifier with I2S input
6. Block diagram
Fig 1. TFA9812 block diagram
15
16, 17
18, 19
10, 11
25
23, 24
26, 27
VDDP
VSSP1
22
BOOT1P
VDDP
OUT1P
VSSP2
BOOT1N
OUT1N
STAB1
BOOT2P
STAB1
CONTROL
LOGIC 20, 21
DRIVER
HIGH
12
13, 14
VDDP
VSSP2
VDDP
OUT2P
VSSP2
BOOT2N
OUT2N
STAB2
STAB2
XTALIN
XTALOUT
MCLK
REFERENCES
PROTECTION
OVP
UVP
OCP
OTP
ODP
WP
CDELAYDIAG
1
2
47
31
39
41 42 45
TFA9812
010aaa217
CONTROL
LOGIC
DRIVER
HIGH
DRIVER
LOW
DRIVER
LOW
CONTROL
LOGIC
CONTROL
LOGIC
DRIVER
HIGH
DRIVER
LOW
DRIVER
HIGH
DRIVER
LOW
PWM
CONTROLLER
PWM
CONTROLLER
CONTROL
INTERFACE
REGISTER
ADDRESS
HEX 01
PHASED
LOCKED
LOOP
THERMAL
FOLDBACK
OSCILLATOR
ADC
10
34
35
36
37
38
POWERUP
SDA/MS
GAIN
33ENABLE
CSEL
ADSEL2/PLIM2
ADSEL1/PLIM1
SCL/SFOR
STABD REFD STABA REFA
30
29 488
EXPOSED DIE PADDLE VSS1 VSS2
46
45
44
BCK
WS
DATA
CSEL
TEST1 TEST2 AVOL VDDD(3V3) VDDA(3V3) VDDA
743 32 40 36
9
28
CLOCK
PROTECTION
LP
UFP
OFP
IBP
SERIAL
AUDIO
INTERFACE
10-BAND
PARAMETRIC
EQUALIZER
VOLUME
CONTROL
AND SOFT
MUTE
INTER-
POLATION
FILTER AND
DE-EMPHASIS
POWER
LIMITER
GAIN

TFA9812_2 © NXP B.V. 2009. All rights reserved.
Preliminary data sheet Rev. 02 — 22 January 2009 6 of 66
NXP Semiconductors TFA9812
BTL stereo Class-D audio amplifier with I2S input
Figure 1 shows the block diagram of the TFA9812. For a detailed description of the audio
signal path see Section 8.1.
7. Pinning information
7.1 Pinning
Fig 2. Pin configuration, transparent top view
Table 3. Pinning description TFA9812
Pin Symbol Type Description
1 XTALIN I Crystal oscillator input
2 XTALOUT O Crystal oscillator output
3V
DDA(3V3) P Analog supply voltage (3.3 V)
4 STABA O 1.8 V analog stabilizer output
5 REFA P Analog reference voltage
6V
DDA P Analog supply voltage (8 V to 20 V)
7 TEST1 I Test signal input 1. For test purposes only (connect to VSS)
8V
SS1 P PCB ground reference
9 STAB2 O Decoupling of internal 11 V regulator for channel 2 drivers
10 VSSP2 P Negative power supply voltage for channel 1 and channel 2
11 VSSP2 P Negative power supply voltage for channel 1 and channel 2
12 BOOT2N O Bootstrap high-side driver negative PWM output channel 2
13 OUT2N O Negative PWM output channel 2
010aaa218
TFA9812HN
BOOT1N
VSSP2
BOOT2N
VSSP1
VSSP2 VSSP1
STAB2 STAB1
VSS1 DIAG
TEST1 CDELAY
VDDA POWERUP
REFA AVOL
STABA ENABLE
VDDA(3V3) GAIN
XTALOUT CSEL
XTALIN ADSEL2/PLIM2
OUT2N OUT2N
BOOT1P
OUT2P OUT1P
VDDP
VDDP
OUT1P OUT1P
BOOT1P
OUT1N OUT1N
VSS2
MCLK BCK WS DATA TEST2 REFD STABD VDDD(3V3) SDA/MS SCL/SFOR ADSEL1/PLIM1
12 25
11 26
10 27
9 28
8 29
7 30
6 31
5 32
4 33
3 34
2 35
1 36
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
terminal 1
index area
Transparent top view

TFA9812_2 © NXP B.V. 2009. All rights reserved.
Preliminary data sheet Rev. 02 — 22 January 2009 7 of 66
NXP Semiconductors TFA9812
BTL stereo Class-D audio amplifier with I2S input
14 OUT2N O Negative PWM output channel 2
15 BOOT1P O Bootstrap high-side driver positive PWM output channel 1
16 OUT1P O Positive PWM output channel 1
17 OUT1P O Positive PWM output channel 1
18 VDDP P Positive power supply voltage (8 V to 20 V)
19 VDDP P Positive power supply voltage (8 V to 20 V)
20 OUT2P O Positive PWM output channel 2
21 OUT2P O Positive PWM output channel 2
22 BOOT2P O Bootstrap high-side driver positive PWM output channel 2
23 OUT1N O Negative PWM output channel 1
24 OUT1N O Negative PWM output channel 1
25 BOOT1N O Bootstrap high-side driver negative PWM output channel 1
26 VSSP1 P Negative power supply voltage for channel 1 and channel 2
27 VSSP1 P Negative power supply voltage for channel 1 and channel 2
28 STAB1 O Decoupling of internal 11 V regulator for channel 1 drivers
29 DIAG O Fault mode indication output (open-drain pin)
30 CDELAY I Timing reference
31 POWERUP I Power-up pin to switch between Sleep and other operational
modes
32 AVOL I Analog volume control (Legacy mode)
33 ENABLE I Enable input to switch between 3-state and other
operational modes
34 GAIN I Gain selection input to select between 0 dB and +24 dB
gain (Legacy mode)
35 CSEL I Control selection input to select between Legacy mode
(no I2C bus control) and I2C bus control
36 ADSEL2/PLIM2 I Address selection in I2C mode input 2, power limiter
selection input 2 in Legacy mode
37 ADSEL1/PLIM1 I Address selection in I2C mode input 1, power limiter
selection input 1 in Legacy mode
38 SCL/SFOR I I2C bus clock input in I2C mode, I2S serial data format
selection input in Legacy mode
39 SDA/MS I/O I2C bus data input and output in I2C mode, master/slave
selection input in Legacy mode
40 VDDD(3V3) P Digital supply voltage (3.3 V)
41 STABD O 1.8 V digital stabilizer output
42 REFD P Digital reference voltage
43 TEST2 I Test signal input 2; for test purposes only (connect to VSS)
44 DATA I I2S bus data input
45 WS I/O I2S bus word select input (I2S slave mode) or output (I2S
master mode)
46 BCK I/O I2S bus bit clock input (I2S slave mode) or output (I2S
master mode)
Table 3. Pinning description TFA9812
…continued
Pin Symbol Type Description

TFA9812_2 © NXP B.V. 2009. All rights reserved.
Preliminary data sheet Rev. 02 — 22 January 2009 8 of 66
NXP Semiconductors TFA9812
BTL stereo Class-D audio amplifier with I2S input
8. Functional description
8.1 General
The TFA9812 is a high-efficiency stereo BTL Class-D amplifier with a digital I2S audio
input. It supports all commonly used I2S formats.
Figure 1 shows the functional block diagram, which includes the key function blocks of the
TFA9812. In the digital domain the audio signal is processed and converted to a pulse
width modulated signal using BD modulation. A BTL configured power comparator carries
out power amplification.
The audio signal processing path is as follows:
1. The Digital Audio Input (DAI) block translates the I2S (-like) input signal into a
standard internal stereo audio stream.
2. The 10-band parametric equalizer can optionally equalize the stereo audio stream.
Both channels have separate equalization streams. It can be used for speaker transfer
curve compensation to optimize the audio performance of applied speakers.
3. Volume control in the TFA9812 is done by attenuation. The attenuation depends on
the volume control settings and the thermal foldback value. Soft mute is also arranged
at this part. In Legacy mode the volume control is done by an on-board
Analog-to-Digital Converter (ADC) which measures the analog voltage on pin 32.
4. The interpolation filter interpolates from 1 fs to the PWM controller sample rate
(2048 fs at 44.1 kHz) by cascading FIR filters.
5. The gain block can boost the signal with 0 dB or +24 dB. Four specific gain settings
are also provided in this block. These specific gain settings are related to maximum
clip levels of < 0.5 %, 10 %, 20 % or 30 % THD at the TFA9812 output. These
maximum clip levels are only valid with the gain boost set to 0 dB and a 0 dBFS input
signal.
6. The power limiter limits the maximum output signal of the TFA9812. The power limiter
settings are 0 dB, −1.5 dB, −3 dB, and −4.5 dB. This function can be used to reduce
the maximum output power delivered to the speakers at a fixed supply voltage and
speaker impedance.
7. The PWM controller block transforms the audio signal into a BD-modulated PWM
signal. The BD-modulation provides a high signal-to-noise performance and
eliminates clock jitter noise.
8. Via four differential comparators the PWM signals are amplified by two BTL power
output stages. By default the left audio signal is connected to channel 1 and the right
audio signal to channel 2.
47 MCLK I/O Master clock input (I2S slave mode) or output (I2S master
mode)
48 VSS2 P PCB ground reference
Exposed
die-paddle - P PCB ground reference
Table 3. Pinning description TFA9812
…continued
Pin Symbol Type Description

TFA9812_2 © NXP B.V. 2009. All rights reserved.
Preliminary data sheet Rev. 02 — 22 January 2009 9 of 66
NXP Semiconductors TFA9812
BTL stereo Class-D audio amplifier with I2S input
The block control defines the operational control settings of the TFA9812 in line with the
actual I2C settings and the pin-controlled settings.
The PLL block creates the system clock and can take the I2S BCK, the MCLK or an
external crystal as reference source.
The following protections are built into the TFA9812:
•Thermal Foldback (TF)
•OverTemperature Protection (OTP)
•OverCurrent Protection (OCP)
•OverVoltage Protection (OVP)
•UnderVoltage Protection (UVP)
•Window Protection (WP)
•Lock Protection (LP)
•UnderFrequency Protection (UFP)
•OverFrequency Protection (OFP)
•Invalid BCK Protection (IBP)
•DC-blocking
•ElectroStatic Discharge (ESD)
8.2 Functional modes
8.2.1 Control modes
The two control modes of the TFA9812 are I2C and legacy.
•In I2C mode the I2C format control is enabled.
•In Legacy mode a pin-based subset of the control options is available. The control
settings for features which are not available in Legacy mode are set to the default I2C
register settings.
The control mode is selected via pin CSEL as shown in Table 4.
In the functional descriptions below the control for the various functions will be described
for each control mode. Section 9.6 summarizes the support given by each control mode
for the various TFA9812 functions.
8.2.2 Key operating modes
There are six key operating modes:
•In Sleep mode the voltage supplies are present, but power consumption for the whole
device is reduced to the minimum level. The output stages in Sleep mode are 3-state
and I2C communication is disabled.
Table 4. Control mode selection
CSEL Pin value Control mode
0 Legacy (no I2C)
1I
2C

TFA9812_2 © NXP B.V. 2009. All rights reserved.
Preliminary data sheet Rev. 02 — 22 January 2009 10 of 66
NXP Semiconductors TFA9812
BTL stereo Class-D audio amplifier with I2S input
•In Soft mute mode the I2S input signal is overruled with a soft mute.
–In Legacy control mode the analog input pin AVOL controls Soft mute mode.
–In I2C control mode I2C control can be used to enable an automatic soft mute
function. See also Section 8.5.3.
•In Hard mute mode the PWM controller is overruled with a 50 % duty cycle square
pulse. The Hard mute mode is only available in I2C control mode.
•In Operating mode the TFA9812 amplifies the I2S audio input signal in line with the
actual control setting.
•In 3-state mode the output stages are switched off.
•Fault mode is entered when a fault condition is detected by one or more of the
protection mechanisms implemented in the TFA9812. In Fault mode the actual device
configuration depends on the fault detected: see Section 8.7 for more information.
Fault mode is for a subset of the faults flagged on the DIAG output pin. When the
DIAG pin is flagged the output stages will be forced to enter 3-state mode. In Sleep
mode the DIAG pin will not flag fault modes.
[1] Clocking faults do not trigger DIAG output.
[2] Under these conditions soft mute still has to be enabled by the appropriate I2C setting.
8.2.3 I2S master/slave modes and MCLK/BCK clock modes
The I2S interface can be set in master or in slave.
•In I2S master mode the PLL locks to the output signal of the internal crystal oscillator
circuit which uses an external crystal. The BCK, WS and MCLK signals are generated
by the TFA9812. On the MCLK pin the TFA9812 delivers a master clock running at the
crystal frequency.
•In I2S slave mode the PLL can lock to:
–The external MCLK signal on the MCLK pin called MCLK clock mode.
–The I2S input BCK signal on the BCK pin called BCK clock mode.
The I2S master or slave mode can be selected:
•In I2C control mode by selecting the right I2C setting.
•In legacy control mode by selecting the right setting on the SDA/MS pin.
Table 5. Operational mode selection
Pin: DIAG Output Operational mode
selected:
POWERUP ENABLE CSEL AVOL
0 - - - floating Sleep mode
1 - - - 0 / floating Fault mode (enabled by
system)[1]
1 1 1 - floating Soft mute mode (in I2C
control mode)[2]
1 1 0 < 0.8 V floating Soft mute (in Legacy control
mode)
1 0 - - floating 3-state mode
1 1 - - floating Operational mode