NXP Semiconductors MCXN 4 Series Guide

UG10092
MCXNx4x Hardware Design Guide
Rev. 1 — 19 January 2024 User guide
Document information
Information Content
Keywords UG10092, MCXNx4x, MCX N, MCX N Series, MCX N94x, MCX N54x, High-Performance
MCU, eIQ Neutron NPU, EdgeLock Secure Enclave, Dual-Core MCU, 150 MHz MCU, Artificial
Intelligence, Machine Learning, Advanced Security MCU, Secure MCU, Neural Processing Unit,
Low-Power MCU, General Purpose MCU, Arm Cortex-M33 MCU
Abstract This document aims to help hardware engineers design and test their MCXNx4x MCU-based
designs.

NXP Semiconductors UG10092
MCXNx4x Hardware Design Guide
1 Introduction
This document aims to help hardware engineers design and test their MCXNx4x MCU-based designs. It
provides information about board layout recommendations and design checklists to ensure first-pass success
and avoid board bring-up problems. For the relevant device-specific hardware documentation, see MCX N
Series Microcontrollers.
2 Architecture overview
Before designing your system, it is essential to understand the architecture so that the schematic process is
performed correctly, see Figure 1.
Analog domain
VDD_ANA
VDD_BAT
VDD
_CO
RE
VDD
_
L
D
O
_
C
O
R
E
aaa-053995
LDO_CORE
VDD
_US
B
USB FS PHY
Core domain System domain
VOUT_SYS
1.8/2.5 V
VDD_LDO_SYS
USB HS PHY
LDO_SYS
VDD_DCDC
DCDC_LX
DCDC_CORE
Retention
RAM
VBAT domain
VBAT
switch
Dig.
Anal.
RAM
LDO Switch
VDD
GPIO
Port 0/1
GPIO
VDD_P2
GPIO
Port 2
GPIO
VDD_P3
GPIO
Port 3
GPIO
VDD_P4
GPIO
Port 4
GPIO GPIO
Port 5
GPIO
Figure 1. MCXNx4x hardware architecture block diagram
The design process typically begins with power for the device, as it is one of the most critical aspects of the
design. MCXNx4x was designed to allow for flexibility in the power schema for the device. There are eight
independent power domains to consider. Each power domain has its own operating ranges and restrictions, see
Table 1.
Power domain Voltage range Package pin Remarks
Core 1.71 V – 3.60 V VDD_DCDC or VDD_
LDO_CORE
This value applies to both DCDC and core LDO.
System 1.71 V – 1.98 V
2.25 V – 2.75 V
VDD_LDO_SYS
(VDD_DCDC in HLQFP)
Onboard regulators do accept 1.71 V – 3.6 V.
The extended voltage range of 2.25 V - 2.75 V is for fuse
programming only.
VDD 1.71 V – 3.60 V VDD It also powers VDD_P2 in the HLQFP package.
Table 1. Power domain operating requirements
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Power domain Voltage range Package pin Remarks
VDD_P2 1.71 V – 3.60 V
1.14 V – 1.32 V
VDD_P2
(VDD in HLQFP)
The extended voltage range of 1.14 V – 1.32 V is
allowed, provided this rail ramps after the system
domain.
The extended voltage range of 1.14 V – 1.32 V is not
allowed in the HLQFP package because it is powered by
the VDD pin.
VDD_P3 1.71 V – 3.60 V
1.14 V – 1.32 V
VDD_P3 The extended voltage range allowed, provided this rail
ramps after the system domain.
VDD_P4/VDD_
ANA
1.71 V – 3.60 V VDD_P4 and VDD_ANA VDD_P4 and VDD_ANA must be tied together.
VDD_BAT 1.71 V – 3.60 V VDD_BAT This rail is required and must ramp before or with the
system domain.
USB 3.00 V – 3.60 V VDD_USB This rail is optional if USB is not used in the application.
If USB is not used, this rail must be grounded.
Table 1. Power domain operating requirements...continued
3 Power configurations
Two basic power configurations are allowed for the MCXNx4x:
•Single supply configuration
•Mixed supply configuration
3.1 Single supply configuration
In this configuration, a single power source between 1.71 V - 3.6 V supplies power to the entire system, see
Figure 2.
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Analog domain
VDD_ANA
VDD_BAT
VDD_
C
O
RE
VDD_
L
DO
_
CO
R
E
aaa-054003
LDO_CORE
V
DD_
US
B
USB FS PHY
Core domain System domain
VOUT_SYS
1.8/2.5 V
VDD_LDO_SYS
USB HS PHY
LDO_SYS
VDD_DCDC
1.71 - 3.6 V
DCDC_LX
DCDC_CORE
Retention
RAM
VBAT domain
VBAT
switch
Dig.
Anal.
RAM
LDO Switch
V
DD
G
P
IO
Port 0/1
G
P
I
O
V
D
D_
P
2
G
P
I
O
Port 2
G
P
I
O
V
D
D_
P
3
G
P
IO
Port 3
G
P
I
O
V
D
D
_
P
4
G
P
I
O
Port 4
G
P
I
O
G
P
I
O
Port 5
G
P
I
O
Figure 2. Single supply power configuration
The connections highlighted in the red box in Figure 2, shown as dashed lines in this configuration, have
options available:
•Either the VDD_DCDC or the VDD_LDO_CORE can be powered, but it is optional to power both simultaneously.
–If using the DCDC, VDD_DCDC must be powered, and VDD_LDO_CORE is connected directly to VDD_CORE.
Also, the DCDC_LX pin must be connected to the VDD_CORE pin through the DCDC inductor. The inductor
and specifics are explained later in this document.
Note: NXP recommends using the DCDC as the core regulator. it is more efficient than the LDO regulator.
–If using the core LDO, VDD_LDO_CORE must be powered, and both VDD_DCDC and DCDC_LX must be
grounded through a 10 k ohm resistor, the same resistor must be used for both pins.
Note: Designs that reduce BoM costs or save physical space must use the core LDO.
•The main source powers VDD_BAT, or an always-on source, such as a backup battery, may power it.
•VDD_USB may be omitted if it is not being used in the application. If not used, it must be connected to the
ground.
In the single supply configuration, sources less than 2.75 V cannot blow fuses. It must be considered in
the design phase of your project. Supplies of 1.95 V or less must power the VOUT_SYS pin directly and tie
VDD_LDO_SYS to VOUT_SYS.
3.2 Mixed supply configuration
In this configuration, at least two different voltage supplies power the system. Both must still be between 1.71 V
– 3.6 V, see Figure 3.
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NXP Semiconductors UG10092
MCXNx4x Hardware Design Guide
Analog domain
VDD_ANA
VDD_BAT
V
DD
_
C
O
RE
V
DD_
L
DO
_CO
R
E
aaa-054007
LDO_CORE
V
DD_
USB
USB FS PHY
Core domain System domain
VOUT_SYS
1.8/2.5 V
VDD_LDO_SYS
USB HS PHY
LDO_SYS
VDD_DCDC
DCDC_LX
DCDC_CORE
Retention
RAM
VBAT domain
VBAT
switch
Dig.
Anal.
RAM
LDO Switch
V
DD
G
P
IO
Port 0/1
G
P
IO
V
D
D_
P
2
G
P
IO
Port 2
G
P
I
O
V
DD
_
P
3
G
P
I
O
Port 3
G
P
I
O
V
D
D
_
P
4
G
P
I
O
Port 4
G
P
I
O
G
P
I
O
Port 5
G
P
I
O
Supply A
Supply B
Figure 3. Mixed supply power configuration
The connections highlighted in the red box in Figure 3, shown as dashed lines in this configuration, have
options available. It is assumed that Supply A is a ~3.3 V supply highlighted in green, while Supply B is
approximately ~1.8 V highlighted in blue, as shown in Figure 3. These supplies could be different, as in the
case of a 1.8 V system that needs to interface to legacy 3.3 V devices or a 1.8 V system that requires a higher
analog voltage for performance reasons, but these are common supply voltages. Some notes concerning this
configuration:
•If using the DCDC, the lower voltage should be selected. The DCDC is more efficient at lower voltages. The
same thumb rule applies to the core LDO. The VDD_CORE must ramp after VDD. Designers must ensure that
these conditions are met.
•Either source can supply VDD_BAT but should power up before or with VDD_SYS. Designers must ensure that
these conditions are met.
•Secondary IOs VDD_P2, VDD_P3, and VDD_P4 must ramp after VDD_SYS unless they are shorted with the
VDD.
4 Bulk and decoupling capacitance
Bulk and decoupling capacitors must be used for proper chip operation. Bulk capacitors are used for local
power supply to the pin, and decoupling capacitors are used to prevent noise from entering the MCU by
shortening it to the ground. Selecting decoupling capacitors that exhibit low reactance in the frequency ranges
of interest is essential.
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NXP Semiconductors UG10092
MCXNx4x Hardware Design Guide
In general, NXP recommends that each power pin have one decoupling capacitor of 0.1 µF and each power
domain have one bulk capacitor of 1 µF. The decoupling and bulk capacitors must be placed as close to their
respective MCU pins as possible. The minimum recommended bulk and decoupling capacitors are listed
in Table 2 and are based on the assumption that no devices operate in the system with a higher operating
frequency than the MCX device.
Power domain Recommendation Remarks
VDD_LDO_CORE 1x 0.1 µF If the core LDO is not being used, this capacitor can be omitted.
It is also not applicable for the HLQFP package.
VDD_CORE 1x 3.7 µF - 10 µF (4.7 µF is
recommended)
2x 0.1 µF
If the DCDC is used to power the core, the bulk capacitor (1x
3.7-10 µF) must be excluded.
VDD_LDO_SYS 1x 1.0 µF If the LDO system is not being used, this capacitor can be
omitted.
It is also not applicable for the HLQFP package.
VDD_SYS 1x 1.0 µF - 4.0 µF -
VDD 1x 1 µF
3x 0.1 µF
-
VDD_P2 1x 1 µF
2x 0.1 µF
This row is not applicable to the HLQFP package.
VDD_P3 1x 1 µF
3x 0.1 µF
-
VDD_P4 1x 1 µF
2x 0.1 µF
-
VDD_ANA - It must be tied to VDD_P4 through a filtering inductor. As such,
this net uses VDD_P4 bulk and decoupling capacitance.
VDD_BAT 1x 0.1 µF -
VDD_USB 1x 0.1 µF If USB is not being used, it can be omitted.
VREFH 1x 1 µF -
VDD_DCDC 1x 10 µF
1x 6 – 30 µF
If the DCDC is not used, both of these capacitors can be omitted.
Otherwise, the 10 µF capacitor must be placed on the input to the
DCDC, while the 6 µF - 30 µF capacitor must be placed on the
output close to the VDD_CORE pin.
Table 2. Minimum recommended bulk and decoupling capacitors for VFBGA package
5 Package details, route-out, and special considerations
The MCXNx4x device is available in two packages:
•184-pin VFBGA
•100-pin HLQFP
This section discusses the package dimensions, specifications, recommended general layout, recommended
route-out, and PCB stack-up.
5.1 184-pin VFBGA package
This section provides details about the 184-pin VFBGA package outline, placement, routing, and PCB stack-up.
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MCXNx4x Hardware Design Guide
5.1.1 Package outline
This section provides the details about the outline of the 84-pin VFBGA package, see Figure 4.
aaa-054008
Package drawing:
SOT2172-1
184VFBGA
9 x 9 x 0.86 mm
0.5 mm
Figure 4. 184-pin VFBGA package drawing
5.1.2 VFBGA placement
The key peripheral placement of the VFBGA package is shown Figure 5.
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NXP Semiconductors UG10092
MCXNx4x Hardware Design Guide
P1_8A
aaa-054009
P1_7 P1_4 P0_25
ENET
XTAL48M
FlexSPI_A
DCDC
USB
XTAL32K
FlexSPI_B
uSDHC
Analog
functions
P0_21 P0_17 P0_9 P0_5 P0_1 P0_0
P1_9 P1_6 P1_5 P1_3 P0_24 P0_23 P0_22 P0_16 P0_11 P0_10 P0_4 P0_3 P0_2 P3_0
1 2 3 4 6 8 10 12 14 16 17
P1_10 P1_2 P1_1 P1_0 P0_ 20 P0_19 P0_18 P0_8 P0_7 P0_6 P3_1
P1_13 P1_12 P1_11 P1_14 VSS P0_31 P0_12 VSSVSS P3_7 P3_2 P3_3 P3_6
P1_15 VSS
P1_19
P0_30 P0_28 P0_27 P0_14 VSS P3_8
P1_30 P1_31 RESE
T_B P1_17 P1_16 P0_ 29 P0_26 P0_13 P3_4 P3_9 P3_11 P3_10
VSS P1_18 VDD VDD_
P3 P3_5P0_15 P3_12
P2_1 P2_0 P2_2 VSS VDD VDD VSS VDD_
P3
VDD_
P3 VSS P3_15 P3_13 P3_14
P2_3 VSS VSS VSS VSS P3_16
P2_5 P2_6 P2_4 P1_20
VDO_
LDO_
CORE
VDD_
P2 VSS VDO_
CORE P5_5 P5_6 P3_17 P3_18 P3_19
P2_7 P1_22 P1_21 VDO_
P2
VDO_
CORE P5_8P5_7 P3_21
P2_9 P2_8 P2_10 P1_23 P4_4 P4_5 P5_2 P5_4 P5_9 P3_23 P3_ 22 P3_20
P2_11 VDO_
P4 P4_14P4_6 P4_18 P5_3 VSS VDD_ SYS
P4_0 P4_1 ANA_0 VDO_
P4
VSS_
P4
VSS_
P4
VSS_
P4
USB1_
MVSS VSS
VDD_
LDO_
SYS
VSS_
DCDC
DCDC_
LX
ANA_1 VDO_
ANA
VREF
H
VREF
LP4_16 P4_17 P4_19 VDD_ USB
USB1_
DP
USB1_
DM
VDD_
DCDC
P4_ 2 ANA_4 ANA_5 P4_7 P4_12 P4_13 P4_15 P4_ 20 P4_ 21 P4_22 USB0
DM
USB0
DP VSS VDD_ BAT
P4_3 ANA_6 ANA_7 ANA_1
4
ANA_1
8
ANA_
22 P4_ 23 USB1_ VBUS P5_0 P5_1
5 7 9 11 13 15
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
P4_0
P4_1
ANA_0
VDO_
P4
VSS_
P4
VSS_
P4
VSS_
P4
USB
M
ANA_1
VDO_
ANA
VREF
H
VREF
L
P4_16
P4_17
P4_19
P4_ 2
ANA_4
ANA_5
P4_7
P4_12
P4_13
P4_15
P4_ 20
P4_
P4_3
ANA_6
ANA_7
ANA_1
4
ANA_1
8
ANA_
22
P
R
T
U
P2_1
P2_0
P2_2
P2_3
P2_5
P2_6
P2_4
P2_7
P2_9
P2_8
P2_10
H
J
K
L
M
N
P1_30
P1_31
F
P1_8
A
P1_7
P1_4
P1_9
P1_6
P1_5
P1_3
3
P1_10
P1_2
P1_1
P1_13
P1_12
P1_11
P1_14
5
B
C
D
P3_7
P3_2
P3_3
P3_6
P3_8
P3_4
P3_9
P3_11
P3_10
P3_5
P3_12
P3_15
P3_13
P3_14
VSS
P3_16
VDD_
USB
USB1_
DP
USB1_
DM
VDD_
DCDC
P4_22
USB0
DM
USB0
DP
VSS
P5_0
P5_1
VSS_
DCDC
DCDC_
LX
Figure 5. Key peripheral placement for VFBGA package
5.1.2.1 Bulk and decoupling capacitor placement
Like other high-speed BGA devices, decoupling and bulk capacitors must be placed on the bottom side of the
PCB, directly underneath the device. It is recommended to use the smallest package type allowed by budget
and manufacturing constraints for both capacitor types. These capacitors must be mounted as close to the
power vias as possible. It minimizes the inductance and ensures high-speed transient current demand by the
processor.
An example layout is shown in Figure 6.
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NXP Semiconductors UG10092
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Figure 6. Example decoupling and bulk capacitor layout for VFBGA package
5.1.3 VFBGA routing
The MCXNx4x VFBGA is designed to allow for routing all 184-pins externally in a four-layer design using 4 mil
trace widths and Via-In-Pad (VIP) technology. The recommended route-out is shown in Figure 7.
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L1
L2
L3 L4
Figure 7. Recommended VFBGA escape routing
5.1.4 PCB stack-up for VFBGA
As per NXP recommendations, MCXNx4x VFBGA is designed to be routed on a minimum of four layers. Less
may be possible, but it may require special toolings and/or a nonoptimal design. It may also not be possible to
route out all of the connections. Two examples of a four-layer stack-up are shown in Figure 8 and Figure 9.
Signal
2x
aaa-054010
GND
PWR
Signal
2x
>> 2x
Figure 8. Example four-layer stack-up #1
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NXP Semiconductors UG10092
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Signal
2x
aaa-054011
GND
Signal
GND
2x
2x
Figure 9. Example four-layer stack-up #2
An example six-layer stack-up is shown in Figure 10. This stack-up is used in the MCX-N9XX-EVK.
aaa-053996
Subclass name Type Material Thickness (MIL)
SURFACE AIR
TOP CONDUCTOR COPPER_1OZ 1.200000
DIELECTRIC FR-4
L2_GND1 PLANE COPPER_1OZ 1.200000
DIELECTRIC FR-4
L3-SIG1 CONDUCTOR COPPER 1.250000
DIELECTRIC FR-4
L4-PWR1 PLANE COPPER 1.250000
DIELECTRIC FR-4
L5-GND2 PLANE COPPER 1.200000
DIELECTRIC FR-4
BOTTOM CONDUCTOR COPPER_1OZ 1.200000
2.520000
2.520000
44.500000
2.520000
2.520000
SURFACE AIR
2x
2x
>> 2x
2x
2x
Figure 10. Example six-layer stack-up
Considering six layers for high-speed design requires a proper PCB stack-up to ensure impedance control for
critical interfaces and to minimize EMC effects. Impedance control depends on several factors, such as the
trace width and space, associated dielectric and copper thicknesses, and required impedance. High-speed
signals must-have reference planes on an adjacent layer to provide a constant impedance.
First, notice the dielectric thicknesses between the successive layers. L1 is tightly coupled to L2 with a 2.52 mil
dielectric. L3 is tightly coupled to L2 with a 2.52 mil dielectric.
•L3 is isolated from L4 with a thick 44.5 mil dielectric
•L4 is tightly coupled to L5 with a 2.52 mil dielectric
•L6 is tightly coupled to L5 with a 2.52 mil dielectric
The tight coupling of signals to planes with thin dielectrics is the basis of impedance control. The trace widths
and spaces on the signal layers determine the desired signal impedance.
A recommended stack-up for six or more layers:
•L1 - Signals and components
•L2 - Ground plane
•L3 - Signals, power, and ground
Thick core:
•L4 - Power and ground
•L5 - Ground plane
•L6 - Signals, power, ground, and components
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NXP Semiconductors UG10092
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L2 and L5 are solid ground planes that provide the reference planes:
•L1 and L3 are tightly coupled to L2 as the reference plane
•L4 and L6 are tightly coupled to L5 as the reference plane
5.2 100-pin HLQFP package
This section provides details about the 100-pin HLQFP package outline, placement, routing, and PCB stack-up.
5.2.1 Package outline
This section provides the details about the outline of the 100-pin HLQFP package, see Figure 11.
aaa-053997
Package drawing:
SOT1570-6
100HLQFP
14 x 14 x 1.4 mm
0.5 mm
Figure 11. 100-pin HLQFP package drawing
5.2.2 HLQFP placement
The key peripheral placement of the 100-pin HLQFP package is shown Figure 12.
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NXP Semiconductors UG10092
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P1_7 P1_6 P1_5 P1_4 VDD P1_3 P1_2 P1_1 P1_0 P0_23 P0_22 P0_ 21 P0_20 P0_19 P0_18 P0_17 P0_16 VDO P0_6 P0_5 P0_ 4 P0_3 P0_2 P0_1 P0_0
P1_7 P1_6 P1_5 P1_4 VDD P1_3 P1_2 P1_1 P1_0 P0_23 P0_22 P0_ 21 P0_20 P0_19 P0_18 P0_17 P0_16 VDO P0_6 P0_5 P0_ 4 P0_3 P0_2 P0_1 P0_0
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P1_8
P1_9
P1_10
P1_11
P1_12
P1_13
P1_14
P1_15
RESET_
P1_30
P1_31
VDD_COR
VDD
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
P4_0
P4_1
P4_2
P4_3
P1_8
P1_9
P1_10
P1_11
P1_12
P1_13
P1_14
P1_15
RESET_
P1_30
P1_31
VDD_COR
VDD
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
P4_0
P4_1
P4_2
P4_3
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
P3_0
P3_1
P3_2
P3_6
P3_7
P3_8
P3_9
P3_10
P3_11
VDD
P3_12
P3_13
P3_14
P3_15
P3_16
P3_17
P3_18
VDD_COR E
P3_ 20
P3_21
VDD_SYS
VDD
P5_5
P5_4
51 P5_ 3
P3_0
P3_1
VDD_ P3
P3_6
P3_7
P3_ 8
P3_ 9
P3_10
P3_11
VDD_ P3
P3_12
P3_13
P3_14
P3_15
P3_16
P3_17
VDD_ P3
VDD_CORE
P3_20
P3_ 21
VDD_SYS
VDD_D
CDC
DCDC_L X
DCDC_L X
P5_3
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
26 27 28 29 30 31 32 33 34 35 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P4_4 P4_5 P4_6 P4_7 VDD_A
NA VREFH VREFL VSS_ P4 VD D_P4 P4_12
36
P4_13 P4_15 P4_16 P4_17 P4_19 P4_20 P4_21 P4_23 VDD_
USB
USB0_
DM
USB0_
DP
VDD_
BAT P5_0 P5_1 P5_2 N3XX
P4_4
N3X X
N5X X
N3X X
N5X X
P4_5 P4_6 P4_7 VDD_A
NA VREFH VREFL VSS_ P4 VDD_P4 P4_12 P4_13 P4_15 P4_16 P4_17 USB1_ DP USB1_D B1_VB VSS_ USB
VDD_
USB
USB0_
DM
USB0_
DP
VDD_
BAT P5_0 P5_1 P5_2 N5X X
N5X X
P4_0
P4_1
P4_2
P4_3
P4_0
P4_1
P4_2
P4_3
26
27
28
29
30
31
32
33
34
35
37
38
39
P4_4
P4_5
P4_6
P4_7
VDD_ A
NA
VREFH
VREFL
VSS_ P4
VDD_P4
P4_12
36
P4_13
P4_15
P4_16
P4_17
P4_4
P4_5
P4_6
P4_7
VDD_ A
NA
VREFH
VREFL
VSS_ P4
VDD_P4
P4_12
P4_13
P4_15
P4_16
P4_17
VDD
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
VDD
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
XTAL48M
P1_30
P1_31
P1_30
P1_31
FlexSPI_B
uSDHC
Analog
functions
ENET
P4_19
P4_20
P4_21
P4_23
VDD_
USB
USB0_
DM
USB0_
DP
USB1_
DP
USB1_D
B1_VB
VSS_
USB
VDD_
USB
USB0_
DM
USB0_
DP
P5_0
P5_1
P5_0
P5_1
DCDC
VDD
P5_5
VDD_D
CDC
DCDC_L X
P1_8
P1_9
P1_10
P1_11
P1_12
P1_13
P1_14
P1 15
P1_8
P1_9
P1_10
P1_11
P1_12
P1_13
P1_14
P1 15
P1_7
P1_6
P1_5
P1_4
P1_7
P1_6
P1_5
P1_4
USB XTAL32K aaa- 053998
FlexSPI_ A
P3_0
P3_1
P3_2
P3_6
P3_7
P3_8
P3_9
P3_10
P3_11
VDD
P3_12
P3_13
P3_14
P3_15
P3_16
P3_17
P3_18
P3_0
P3_1
VDD_ P3
P3_6
P3_7
P3_ 8
P3_ 9
P3_10
P3_11
VDD_ P3
P3_12
P3_13
P3_14
P3_15
P3_16
P3_17
VDD_ P3
Figure 12. Key peripheral placement of HLQFP package
5.2.3 HLQFP routing
Due to the nature of the HLQFP package, a complicated route-out similar to the VFBA is not necessary. All
traces can be routed to the top layer of the PCB. However, the HLQFP does have a ground pad underneath the
package that must be handled appropriately. The recommended routing for the HLQFP is shown in Figure 13.
Figure 13. Optimal placement example for HLQFP package
Note: The nine pads shown in the center of Figure 13 required for the grounding of the device.
5.2.4 PCB stack-up for HLQFP
Due to the nature of HLQFP packages, there are no restrictions or requirements on the number of layers used
for the HLQFP package. However, the recommended stack-up specified for the VFBGA package still applies for
the HLQFP.
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6 DCDC
The MCXNx4x includes an on-chip DCDC converter to regulate the VDD_CORE domain voltage. The DCDC
regulator is required to achieve optimal power performance of the MCXNx4x devices. An external inductor
is needed for the use of the DCDC converter. The inductor must be placed between the DCDC_LX pin and
the VDD_CORE pin. The inductor should meet all of the specifications outlined in Section "DCDC converter
specifications" in MCXNx4x Data Sheet (document MCXNX4X). An unshielded inductor can be used but is not
recommended for emissions and performance reasons.
6.1 DCDC inductor layout and routing
Proper routing and layout of the DCDC inductor are essential for optimal DCDC performance and for avoiding
unwanted emissions from the inductor. When routing the DCDC inductor, the following rules must be observed:
1. The loop must be on the same layer as the MCXNx4x device.
2. The input capacitor must be closely connected to the output capacitor and input pin.
3. The ground connection trace from the input capacitor to the load capacitor must be well stitched.
An example of a good DCDC circuit layout is shown in Figure 14.
Figure 14. Optimal DCDC routing
The loop referred to in layout rule 1 refers to the path and current follows during the charging and discharging
phases of the DCDC. During the charging phase, the current starts from the DCDC_LX pin travel through the
inductor, and then through the load capacitor to the ground. It is highlighted by the yellow arrows in Figure 14.
During the discharging phase, the current is pulled from the ground, through the bulk capacitor, and to the
VDD_DCDC pin. The blue arrows shown in Figure 14 indicate this return path. This entire loop path must be
minimized for optimal DCDC operation.
7 Clocks
The MCXNx4x includes two external oscillator modules: a 32 kHz oscillator module and a high frequency 16
MHz – 50 MHz oscillator module. The layout and routing of the modules are the same, but there are some
differences as follows:
•The 32 kHz oscillator module has an internal capacitor bank capable of 0 pF to 30 pF in steps, so external
load capacitors are not required. Therefore, the load capacitors are marked DNP.
•The high-frequency oscillator has a High-gain mode resistor footprint. The high-frequency oscillator does not
have an internal capacitor bank, so external load capacitors ARE required.
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NXP Semiconductors UG10092
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The schematics for the two oscillator modules are shown in Figure 15 and Figure 16.
aaa-053999
32.768 KHz
Y2
1 2
EXTAL32K
XTAL32K
Clock
SC32S-12.5PF20PPM
P5_1/XTAL32K
C144
12 pF
DNP
P5_0/EXTAL32K
C145
12 pF
DNP
Figure 15. 32 kHz oscillator schematic
Note: C144 and C145 are marked DNP in Figure 15.
The case includes footprints for the capacitors if needed.
aaa-054000
R194
1 MΩ
DNP
24 MHz
Y3
1 3
EXTAL
XTAL
2
NX2016SA-24MHz-EXS00A_CS07859
4
P1_30/XTAL48M
C147
4.7 pF
50 V
P1_31/EXTAL48M
C148
4.7 pF
50 V
Figure 16. High-frequency oscillator schematic
For more details, see Figure 17.
Figure 17. Recommended oscillator layout
8 Digital interfaces
This section provides details about general high-speed design recommendations, debug circuits, high-speed
USB, full-speed USB, Ethernet, uSHDC, and FlexSPI.
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8.1 General high-speed design recommendations
NXP recommends using high-speed design techniques for most of the digital interfaces. While the interface
speeds are only up to 100 MHz, and some interfaces are slow enough that these recommendations do not
need to be strictly followed. These techniques are good practice and are not cost-prohibitive recommendations.
The recommended layout techniques are detailed below and apply to the data and signaling lines of all digital
interfaces unless otherwise specified:
•Route traces over continuous planes.
–Do not route over power/ground plane slots or antietch.
•Length match data and signaling lines.
•Do not route data and signaling lines under oscillators or parallel to other clock traces and/or data buses.
•Minimize the number of corners needed. When corners are needed, use 45 degree turns instead of 90 degree
turns.
•Minimize data and signaling line length.
•Avoid layer changes.
•Do not create stubs or branches.
•Provide the ground return vias within a 50 mil distance from the signals that layer-transition vias when
transitioning between different reference ground planes.
8.2 Debug circuit
NXP recommends a pull-up resistor on the SWDIO/TMS signal and a pull-down resistor on the SWDCLK/TCK
signal. Other pull-ups are not required. The debug pins are port P0 pins, so they must be pulled up to VDD.
Note: MCU_PWR_SRC sources to VDD are not shown Figure 18, so the JTAG pins can only be pulled up to VDD
levels.
Figure 18 shows the schematic excerpt for the MCX-N9XX-EVK.
2SWDIO/TMS
1.9 V or 3.3 V
VCC_IF_LINK
IF_TMS_SWDIO
aaa-054001
4SWDCLK/TCK IF_TCK_SWDCLK
6SWO/TDO IF_TDO_SWO
8TDI IF_TDI
10 nRST IF_TRGRST_SWDRST
12 TRACE_CLKOUT P1_12/TR
14 TRACE_D0 P1_8/TR
16 TRACE_D1 P1_9/TR
18 TRACE_D2 P1_10/TR
20
1
JTAG_VREF
JTAG_PWR 3
5
7
9
11
13
15
17
19 TRACE_D3
1 3 4
2DNP D18
PESD3V3L5UY
PESD3V3S1UB PESD3V3S1UB
R138
10 KΩ
R136
2.2 KΩ
D16
DNP
C C
A A
R135
100 Ω
C107
10 μF
D15
PMEG1020EH
R134
10 KΩ
5 6
P1_11/TR
HDR 2X10
SILK = MCX N9 DBG
FTSH-110-01-F-DV
50mil pitch header
J11
JP12
HDR_1X3
A
C
1
2
3
1.9 V or 3.3 V
VCC_IF_LINKMCU_PWR_SRC
Buffer power select:
On-board target 1-2 (default)
Off-board target 2-3
Debug trace connector
P3,8 P0_6/ISPMODE_N-DEBUG
P8 IF_DEFECT
D17
DNP
Figure 18. Example debug circuit schematic
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The MCX-N9XX-EVK also includes ESD diodes for the critical pin connections. It is recommended but optional.
The trace signals TRACE_CLKOUT, TRACE_D0, TRACE_D1, TRACE_D2, and TRACE_D3 should be treated as the
data/signaling lines and must be routed with the recommendations detailed in Section 8.1.
8.3 High-speed USB
The USB controller block provides high-performance Universal Serial Bus (USB) functionality that conforms
to the USB Specification, Rev. 2.0 (Compaq, Hewlett-Packard, Intel, Lucent, Microsoft, NEC, Philips; 2000),
and the On-The-Go and embedded host supplement to the USB revision 2.0 specification (Hewlett-Packard
Company, Intel Corporation, LSI Corporation, Microsoft Corporation, Renesas Electronics Corporation, ST-
Ericsson; 2012). There are four dedicated pins to consider in your hardware design:
•USB D+
•USB D-
•USB ID
•USB VBUS
The USB D+ and D- signals should be treated as the data/signaling lines and must be routed with the
recommendations detailed in Section 8.1.
The USB routing must follow these recommendations:
•Route the D+ and D- differential pairs first.
•Route the D+ and D- signals on the top or bottom layer of the board.
•The trace width and spacing of the D+ and D- signals must meet the differential impedance requirement of 90
ohms.
•When placing the connectors, make sure that the ground plane clearouts around each pin have ground
continuity between all pins.
•Maintain parallelism (skew-matched) between D+ and D-, and match the overall differential length difference
to fewer than 5 mil.
•Maintain symmetric routing for each differential pair.
•Minimize the lengths of the high-speed signals that run parallel to the D+ and D- pair.
•These pins are not required and must not use a termination resistor. They must be routed directly to the USB
connector or to any Common mode chokes used in the design.
•The use of TVS diodes on these dedicated pins is also recommended.
The USB VBUS pin is a unique pin in that it is the only 5 V tolerant pin. The VBUS pin from the connector must
be routed directly to the USB_VBUS MCX pin.
The High-Speed USB (HS USB) module requires the use of the HS USB PHY module, which requires the use
of the USB PLL. This module requires specific crystal frequencies to be used. So, if your application uses HS
USB, it must make use of the high-frequency external oscillator, and one of these specific crystal frequencies
must be used:
•12 MHz
•16 MHz
•19.2 MHz
•20 MHz
•24 MHz
•30 MHz
•32 MHz
•38.4 MHz
•40 MHz
•48 MHz
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If using the HS USB in ISP mode, a 24 MHz crystal must be used in at least the first access of the device. It is
possible to change the security fuse configuration to allow for a different crystal, but it must be configured by the
user, for example, factory configuration requires a 24 MHz crystal for HS USB ISP operation.
8.4 Full-speed USB
The USB controller block provides high-performance USB functionality that conforms to the Universal Serial Bus
Specification, Rev. 2.0 (Compaq, Hewlett-Packard, Intel, Lucent, Microsoft, NEC, Philips; 2000), and the On-
The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification (Hewlett-Packard Company,
Intel Corporation, LSI Corporation, Microsoft Corporation, Renesas Electronics Corporation, ST-Ericsson;
2012). There are only two dedicated pins to consider in your hardware design:
•USB D+
•USB D-
The USB VBUS detect pin for the FS USB block is not 5V tolerant. A voltage divider or other similar translator
circuit is necessary for proper operation.
When designing the USB circuit, it is important to know if you plan on implementing a crystal-less design.
Crystal-less designs are only supported in Device mode. Other modes require the high-frequency oscillator to
use a crystal of specific frequencies.
The USB D+ and D- signals should be treated as the data/signaling lines and must be routed with the
recommendations detailed in Section 8.1.
The USB routing must follow these recommendations:
•Route the D+ and D- differential pairs first.
•Route the D+ and D- signals on the top (or bottom) layer of the board.
•The trace width and spacing of the D+ and D- signals must meet the differential impedance requirement of 90
ohms.
•When placing the connectors, ensure that the ground plane clearouts around each pin have ground continuity
between all pins.
•Maintain parallelism (skew-matched) between D+ and D-, and match the overall differential length difference
to fewer than 5 mil.
•Maintain symmetric routing for each differential pair.
•Minimize the lengths of the high-speed signals that run parallel to the D+ and D- pair.
•Provide the ground return vias within a 50 mil distance from the signals that layer-transition vias when
transitioning between different reference ground planes.
•33 ohm termination resistors are required for proper operation.
•TVS diodes are strongly recommended, and Common mode chokes are optional.
8.5 Ethernet
The Ethernet module enables a host to transmit and receive data over Ethernet in compliance with the IEEE
802.3-2008 standard. The Ethernet interface contains a full-featured 10 Mbit/s or 100 Mbit/s Ethernet Media
Access Controller (MAC) designed to provide optimized performance by using DMA hardware acceleration.
Features include full-duplex or half-duplex operation, RMII support, MII support, flow control, control frames,
hardware acceleration for transmit retry, receive packet filtering, and wake-up on LAN activity, supporting both
wake-up and magic packet frames.
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8.5.1 RMII
This section provides information about Reduced Media Independent Interface (RMII), Ethernet schematic, and
layout recommendations.
8.5.1.1 Ethernet schematic recommendations
When implementing the Ethernet in a design, sourcing the clock for the Ethernet Phy is a major concern due
to specific timing requirements of the Ethernet standard. This clock can be MCU supplied or Phy supplied.
Which option you select depends on the selected Phy and individual situations. MCX supports either of these
configurations via the same pin.
Figure 19 shows the Ethernet clocking scheme.
0
1
25 MHz
2.5/25 MHz clk_tx_i
1
DIV
(2/20)
MAC speed
(10 MHz/100 MHz)
ENET0_RX_CLK
ENET0_TX_CLK
(50 MHz/25 MHz)
If P1_4 function =
ENET0_TX_CLK and
ENETRMIICLKSEL! = 0
ENETRMIICLKSEL
ENET RMII divider
clk_rmii
DIV
SYSCON.ENET_PHY_INTF_SEL.PHY_SEL
0
2.5/25 MHz
25 MHz clk_rx_i
clk_rmii_i
50 MHz
aaa-054002
GATE
0000
SYSCON.ENET_PHY_INTF_SEL.PHY_SEL
ENET0_RX_CLKP1_11
ENET0_TX_CLKP1_4
ENETPTPREFCLKSEL
ENET 1588 divider
clk_ptp_ref_i
DIV
pll0_clk
clk_in
0
ENET0_TX_CLK
pll1_clk1
0
none
001
010
011
100
101
110
111
ENET 1588
divider clk_ptp_ref_i
to ethernet
125 MHz
ENETPTPREFCLKDIV[7:0]
ENET 1588 PTP clock select
ENETPTPREFCLKSEL[2:0]
0000
pll0_clk
clk_in
0
0
pll1_clk0
0
none
001
010
011
100
101
110
111
ENET RMII
divider clk_rmii
to ethernet
50 MHz
ENETRMIICLKDIV[7:0]
ENET RMII clock select
ENETRMIICLKSEL[2:0]
Figure 19. Ethernet clocking scheme
As shown by the red arrows in Figure 19, the Ethernet clock is output to the Phy through the ENET0_TX_CLK
(P1_4) when software configures P1_4 to select the ENET0_TX_CLK mux function and ENETRMIICLKSEL
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is not 0x0. As shown by the blue arrows in Figure 19, pin P1_4 accepts the RMII clock from the Phy when the
P1_4 digital input buffer is enabled ENET_PHY_INTF_SEL[PHY_SEL] selects the RMII clock.
In addition to the previous recommendation, NXP suggests impedance matching the MCU to Phy signals, which
may or may not require a termination resistor. It is important to consult the design tools to determine if this is
necessary.
8.5.2 Ethernet layout recommendations
Given the relatively high-speed and tight timing requirements, NXP recommends using high-speed design
techniques when routing the Ethernet in MII or RMII configuration. The RXDx, TXDx, RXDV (RMII only), TXEN
(RMII only), RXCLK (MII only), TXCLK (MII only), TXER (MII only), RXER (MII only), CRS (MII only), and COL
(MII only) signals should be treated as the data/signaling lines and must be routed with the recommendations
detailed in Section 8.1.
8.6 uSHDC
The uSDHC provides the interface between the host system and the eMMC, SD card, and SDIO media.
The module acts as a bridge, passing host bus transactions to the eMMC, SD card, and SDIO by sending
commands and performing data accesses to/from the cards. It handles the SD card/SDIO/eMMC protocols
at the transmission level. It supports up to 104 MHz interface frequencies in SDR mode and 50 MHz in DDR
mode. As such, the data/signaling lines must be routed with the recommendations detailed in the Section 8.1.
The following signals must be considered for data/signaling lines:
•CLK
•CMD
•DATx
Note: The MCX uSDHC module does support using DAT3 as the card detection line.
For more information on building SD-memory card and MMC card systems with EMI filtering and protection
compliant with the relevant standards, see SD(HC)-memory card and MMC interface conditioning (document
AN10911).
8.7 FlexSPI
FlexSPI is a flexible SPI host controller that supports two SPI channels and up to four external devices. Each
channel supports Single/Dual/Quad/Octal mode data transfer and 1/2/4/8 bidirectional data lines. FlexSPI is
most commonly used to interface to external memory.
For more information, see Section "FlexSPI specifications" in MCXNx4x Data Sheet (document MCXNX4X).
There are several sources for the internal sample clock for FlexSPI read data:
•Dummy read strobe generated by the FlexSPI controller and looped back internally
FlexSPIn_MCR0[RXCLKSRC] = 0x0.
•Dummy read strobe generated by FlexSPI controller and looped back through DQS pad
FlexSPIn_MCR0[RXCLKSRC] = 0x1.
•SCLK output clock and looped back from SCLK pad FlexSPIn_MCR0[RXCLKSRC] = 0x2.
•Read strobe provided by a memory device and input from a DQS pad FlexSPIn_MCR0[RXCLKSRC] = 0x3.
For QSPI Flash without a DQS provided by the memory, only the option of FlexSPIn_MCR0[RXCLKSRC] =
0x1 can achieve 100 MHz SDR R/W speed, and the FlexSPI_DQS pin must be left floating.
The Octal flash, where a DQS signal is provided by the memory, must use the option of
FlexSPIn_MCR0[RXCLKSRC] = 0x3, which can achieve 166 MHz DDR R/W. In such a case, the
FlexSPI_DQS pin must be connected to the flash directly.
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