NXP Semiconductors QorIQ LS1028A User manual

QorIQ LS1028A Reference Design
Board Reference Manual
Document Number: LS1028ARDBRM
Rev. A, 02/2018

QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
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Contents
Section number Title Page
Chapter 1
LS1028ARDB Overview
1.1 Acronyms and abbreviations...........................................................................................................................................7
1.2 Related documentation....................................................................................................................................................9
1.3 Block diagrams............................................................................................................................................................... 10
1.4 Board features................................................................................................................................................................. 11
Chapter 2
LS1028ARDB Functional Description
2.1 Processor.........................................................................................................................................................................15
2.2 Power supplies................................................................................................................................................................ 16
2.3 Clocks............................................................................................................................................................................. 22
2.4 DDR interface................................................................................................................................................................. 24
2.5 USB interface .................................................................................................................................................................26
2.6 DisplayPort..................................................................................................................................................................... 28
2.7 SerDes interface..............................................................................................................................................................28
2.8 Ethernet controller interface........................................................................................................................................... 29
2.9 M.2 connectors................................................................................................................................................................33
2.10 DUART interface............................................................................................................................................................34
2.11 CAN interface................................................................................................................................................................. 35
2.12 I2C interface....................................................................................................................................................................36
2.13 XSPI interface.................................................................................................................................................................39
2.14 JTAG port....................................................................................................................................................................... 41
2.15 eSDHC interface............................................................................................................................................................. 41
2.16 Mikro-click modules.......................................................................................................................................................43
2.17 GPIOs..............................................................................................................................................................................45
2.18 Interrupt handling............................................................................................................................................................46
2.19 Temperature measurement..............................................................................................................................................46
2.20 System controller ........................................................................................................................................................... 47
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Section number Title Page
Chapter 3
Board Configuration and Debug Support
3.1 Switch configuration.......................................................................................................................................................55
3.2 LEDs............................................................................................................................................................................... 57
Chapter 4
Qixis Programming Model
4.1 Register Conventions......................................................................................................................................................62
4.2 Resets..............................................................................................................................................................................63
4.3 Identification Registers................................................................................................................................................... 63
4.4 Identification (ID)........................................................................................................................................................... 63
4.5 Board Version (VER)..................................................................................................................................................... 64
4.6 Qixis Version (QVER)....................................................................................................................................................66
4.7 Programming Model (MODEL)..................................................................................................................................... 66
4.8 Minor Revision (MINOR).............................................................................................................................................. 68
4.9 Control and Status Registers...........................................................................................................................................69
4.10 General Control (CTL)................................................................................................................................................... 69
4.11 Auxiliary (AUX).............................................................................................................................................................70
4.12 System Status (STAT_SYS)...........................................................................................................................................71
4.13 Alarm (ALARM)............................................................................................................................................................ 72
4.14 Presence Detect 1 (STAT_PRES1).................................................................................................................................73
4.15 Presence Detect 2 (STAT_PRES2).................................................................................................................................74
4.16 Misc Status (STAT_MISC)............................................................................................................................................ 75
4.17 LED Control (LED)........................................................................................................................................................ 76
4.18 Reconfiguration Registers...............................................................................................................................................77
4.19 Reconfiguration Control (RCFG)................................................................................................................................... 77
4.20 USB Control (USB_STAT)............................................................................................................................................79
4.21 USB Control (USB_CTL).............................................................................................................................................. 79
4.22 Watchdog (WATCH)......................................................................................................................................................80
4.23 Power Control/Status Registers...................................................................................................................................... 82
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Section number Title Page
4.24 Power Control 2 (PWR_CTL2)...................................................................................................................................... 82
4.25 Power Status 0 (PWR_MSTAT).....................................................................................................................................83
4.26 Power Status 1 (PWR_STAT1)...................................................................................................................................... 84
4.27 Clock Control Registers..................................................................................................................................................85
4.28 Clock Speed 1 (CLK_SPD1).......................................................................................................................................... 86
4.29 Clock ID/Status (CLK_ID).............................................................................................................................................87
4.30 Reset Control Registers...................................................................................................................................................87
4.31 Reset Control (RST_CTL)..............................................................................................................................................88
4.32 Reset Status (RST_STAT)..............................................................................................................................................89
4.33 Reset Event Trace (RST_REASON).............................................................................................................................. 90
4.34 Reset Force 1 (RST_FORCE1).......................................................................................................................................91
4.35 Reset Force 2 (RST_FORCE2).......................................................................................................................................92
4.36 Reset Force 3 (RST_FORCE3).......................................................................................................................................93
4.37 Reset Mask 1 (RST_MASK1)........................................................................................................................................ 94
4.38 Reset Mask 2 (RST_MASK2)........................................................................................................................................ 96
4.39 Reset Mask 2 (RST_MASK3)........................................................................................................................................ 97
4.40 Board Configuration Registers....................................................................................................................................... 98
4.41 Board Configuration 0 (BRDCFG0)...............................................................................................................................98
4.42 Board Configuration 1 (BRDCFG1)...............................................................................................................................99
4.43 Board Configuration 2 (BRDCFG2)...............................................................................................................................100
4.44 Board Configuration 3 (BRDCFG3)...............................................................................................................................101
4.45 Board Configuration 4 (BRDCFG4)...............................................................................................................................102
4.46 Board Configuration 5 (BRDCFG5)...............................................................................................................................103
4.47 Board Configuration 6 (BRDCFG6)...............................................................................................................................105
4.48 DUT Configuration Registers.........................................................................................................................................106
4.49 DUT Configuration 0 (DUTCFG0)................................................................................................................................ 106
4.50 DUT Configuration 1 (DUTCFG1)................................................................................................................................ 107
4.51 DUT Configuration 2 (DUTCFG2)................................................................................................................................ 108
4.52 DUT Configuration 11 (DUTCFG11)............................................................................................................................ 109
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Section number Title Page
4.53 Core Management Space Registers................................................................................................................................ 110
4.54 Core Management Address (CMSA)..............................................................................................................................111
4.55 Core Management Data (CMSD)................................................................................................................................... 112
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Chapter 1
LS1028ARDB Overview
The QorIQ®LS1028A reference design board (LS1028ARDB) is a computing,
evaluation, development, and test platform supporting the QorIQ LS1028A processor,
which is a dual-core Arm®Cortex®-v8 A72 processor with frequency up to 1.3 GHz. The
LS1028ARDB is optimized to support SGMII (1 Gbit/s), QSGMII (5 Gbit/s), PCIe x1 (8
Gbit/s), and SATA (6 Gbit/s) over high-speed SerDes ports, USB 3.0, DisplayPort, and
also a high-bandwidth DDR4 memory.
The LS1028ARDB can be used to develop and demonstrate human machine interface
systems, industrial control systems such as robotics controllers and motion controllers,
and PLCs. The reference design also provides the functionality needed for Industrial IoT
gateways, edge computing, industrial PCs, and wireless or wired networking gateways.
The board is lead-free and RoHS-compliant.
NOTE
The LS1043A processor is used in the LS1028ARDB for early
evaluation of board. Throughout this document, description of
LS1028ARDB features also applies to the board with the
LS1043A interposer, unless otherwise noted.
Developers using the LS1028ARDB can perform standard debugging tasks, such as:
• Upload and run code
• Set breakpoints
• Display memory and registers
• Connect and incorporate proprietary hardware into target systems using the LS1028A
as a host processor
• Use the LS1028ARDB as a demonstration tool
The board support package (BSP) is developed using the Linux operating system. The
onboard CPLD provides startup configuration information for the U-Boot and Linux.
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1.1 Acronyms and abbreviations
The table below lists and explains the acronyms and abbreviations used in this document.
Table 1-1. Acronyms and abbreviations
Term Description
CAN Controller area network
CCI Cache coherency interconnect
CPLD Complex programmable logic device
CTS Clear to send
DCM Development system control monitor
DDR SDRAM Double data rate synchronous dynamic random-access memory
DIP Dual inline package
DPAA Data path acceleration architecture
DQS Data strobe
DUART Dual universal asynchronous receiver/transmitter
DUT Device under test
EC Ethernet controller
ECC Error correcting code
eDP Embedded DisplayPort
EMI Ethernet management interface
ENETC Ethernet controller
eMMC Embedded multimedia card
eSDHC Enhanced secure digital host controller
FET Field-effect transistor
FPGA Field-programmable gate array
GbE Gigabit Ethernet
GPIO General purpose input/output
GT/s GigaTransfers/second
HDLC High-level data link control
HSSI High-speed serial interface
I2C Inter-integrated circuit
JTAG Joint Test Action Group (IEEE®Standard 1149.1™)
LOS Loss of signal
OCM Offline configuration manager
OTG On-The-Go
PBL Pre-boot loader
PLL Phase-locked loop
PMIC Power management multi-channel IC
POR Power-on reset
PSU Power supply unit
PTP Precision time protocol
Table continues on the next page...
Acronyms and abbreviations
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Table 1-1. Acronyms and abbreviations (continued)
Term Description
PWM Pulse width modulation
QSGMII Quad serial gigabit media independent interface
QSPI Quad serial peripheral interface
RCW Reset configuration word
RTC Real time clock
RTS Request to send
SATA Serial advanced technology attachment
SDRAM Synchronous dynamic random-access memory
SerDes Serializer/deserializer
SGMII Serial gigabit media independent interface
SPD Serial presence detect
SPI Serial peripheral interface
SS Spread spectrum
SSC Spread spectrum clocking
TCXO Temperature compensated crystal (Xtal) oscillator
UART Universal asynchronous receiver/transmitter
UDIMM Unbuffered dual inline memory module
UFT Universal frequency translator
USB Universal serial bus
XSPI Octal serial peripheral interface
1.2 Related documentation
The table below lists and explains the additional documents and resources that you can
refer to for more information on the LS1028ARDB.
Some of the documents listed below may be available only under a non-disclosure
agreement (NDA). To request access to these documents, contact your local field
applications engineer or sales representative.
Table 1-2. Related documentation
Document Description
QorIQ LS1028A Product Brief Provides a brief overview of the LS1028A processor
QorIQ LS1028A Data Sheet Provides information about electrical characteristics, hardware design considerations,
and ordering information
QorIQ LS1028A Family Reference
Manual
Provides a detailed description about the LS1028A QorIQ multicore processor and its
features, such as memory map, serial interfaces, power supply, chip features, and
clock information
Table continues on the next page...
Chapter 1 LS1028ARDB Overview
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Table 1-2. Related documentation (continued)
Document Description
QorIQ LS1028A Chip Errata Lists the details of all known silicon errata for the LS1028A
QorIQ LS1028A Reference Design
Board Getting Started Guide
Explains the LS1028ARDB settings and physical connections needed to boot the
board
1.3 Block diagrams
This section provides block diagrams showing major functional units of the LS1028A
processor and LS1028ARDB.
The figure below shows the LS1028A processor block diagram.
Watchpoint
Cross
Trigger
Trust Zone
Power Management
FlexSPI, 3x SPI
DUART, 6x LPUART
32-bit
DDR3L/4
Memory Controller
Real Time Debug
Perf
Monitor
8x I2C, GPIO
8x FlexTimer
Trace
SMMUs
2x USB3.0 w/PHY
CCI-400™ Coherency Fabric
2x SD/SDIO/eMMC
DMA
Core Complex
Accelerators and Memory Control
Basic Peripherals, Interconnect and Debug
Networking Elements
Security Engine (SEC)
6x SAI
1 MB L2 - Cache
32 KB
D-Cache
48 KB
I-Cache
ARM®Cortex®-A72
32b/64b Core
GPU
LCDC
eDP
Secure Boot
4-Lane 10 GHz SerDes
PCIe 3.0
PCIe 3.0
4 port 2.5G Switch TSN
Ethernet
ENETC
1G
2.5G TSN
SATA 3.0
Figure 1-1. LS1028A block diagram
The figure below shows the LS1028ARDB block diagram.
Block diagrams
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