NXP Semiconductors QorIQ LS1028A User manual

QorIQ LS1028A Reference Design
Board Reference Manual
Document Number: LS1028ARDBRM
Rev. A, 02/2018

QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
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Contents
Section number Title Page
Chapter 1
LS1028ARDB Overview
1.1 Acronyms and abbreviations...........................................................................................................................................7
1.2 Related documentation....................................................................................................................................................9
1.3 Block diagrams............................................................................................................................................................... 10
1.4 Board features................................................................................................................................................................. 11
Chapter 2
LS1028ARDB Functional Description
2.1 Processor.........................................................................................................................................................................15
2.2 Power supplies................................................................................................................................................................ 16
2.3 Clocks............................................................................................................................................................................. 22
2.4 DDR interface................................................................................................................................................................. 24
2.5 USB interface .................................................................................................................................................................26
2.6 DisplayPort..................................................................................................................................................................... 28
2.7 SerDes interface..............................................................................................................................................................28
2.8 Ethernet controller interface........................................................................................................................................... 29
2.9 M.2 connectors................................................................................................................................................................33
2.10 DUART interface............................................................................................................................................................34
2.11 CAN interface................................................................................................................................................................. 35
2.12 I2C interface....................................................................................................................................................................36
2.13 XSPI interface.................................................................................................................................................................39
2.14 JTAG port....................................................................................................................................................................... 41
2.15 eSDHC interface............................................................................................................................................................. 41
2.16 Mikro-click modules.......................................................................................................................................................43
2.17 GPIOs..............................................................................................................................................................................45
2.18 Interrupt handling............................................................................................................................................................46
2.19 Temperature measurement..............................................................................................................................................46
2.20 System controller ........................................................................................................................................................... 47
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Section number Title Page
Chapter 3
Board Configuration and Debug Support
3.1 Switch configuration.......................................................................................................................................................55
3.2 LEDs............................................................................................................................................................................... 57
Chapter 4
Qixis Programming Model
4.1 Register Conventions......................................................................................................................................................62
4.2 Resets..............................................................................................................................................................................63
4.3 Identification Registers................................................................................................................................................... 63
4.4 Identification (ID)........................................................................................................................................................... 63
4.5 Board Version (VER)..................................................................................................................................................... 64
4.6 Qixis Version (QVER)....................................................................................................................................................66
4.7 Programming Model (MODEL)..................................................................................................................................... 66
4.8 Minor Revision (MINOR).............................................................................................................................................. 68
4.9 Control and Status Registers...........................................................................................................................................69
4.10 General Control (CTL)................................................................................................................................................... 69
4.11 Auxiliary (AUX).............................................................................................................................................................70
4.12 System Status (STAT_SYS)...........................................................................................................................................71
4.13 Alarm (ALARM)............................................................................................................................................................ 72
4.14 Presence Detect 1 (STAT_PRES1).................................................................................................................................73
4.15 Presence Detect 2 (STAT_PRES2).................................................................................................................................74
4.16 Misc Status (STAT_MISC)............................................................................................................................................ 75
4.17 LED Control (LED)........................................................................................................................................................ 76
4.18 Reconfiguration Registers...............................................................................................................................................77
4.19 Reconfiguration Control (RCFG)................................................................................................................................... 77
4.20 USB Control (USB_STAT)............................................................................................................................................79
4.21 USB Control (USB_CTL).............................................................................................................................................. 79
4.22 Watchdog (WATCH)......................................................................................................................................................80
4.23 Power Control/Status Registers...................................................................................................................................... 82
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Section number Title Page
4.24 Power Control 2 (PWR_CTL2)...................................................................................................................................... 82
4.25 Power Status 0 (PWR_MSTAT).....................................................................................................................................83
4.26 Power Status 1 (PWR_STAT1)...................................................................................................................................... 84
4.27 Clock Control Registers..................................................................................................................................................85
4.28 Clock Speed 1 (CLK_SPD1).......................................................................................................................................... 86
4.29 Clock ID/Status (CLK_ID).............................................................................................................................................87
4.30 Reset Control Registers...................................................................................................................................................87
4.31 Reset Control (RST_CTL)..............................................................................................................................................88
4.32 Reset Status (RST_STAT)..............................................................................................................................................89
4.33 Reset Event Trace (RST_REASON).............................................................................................................................. 90
4.34 Reset Force 1 (RST_FORCE1).......................................................................................................................................91
4.35 Reset Force 2 (RST_FORCE2).......................................................................................................................................92
4.36 Reset Force 3 (RST_FORCE3).......................................................................................................................................93
4.37 Reset Mask 1 (RST_MASK1)........................................................................................................................................ 94
4.38 Reset Mask 2 (RST_MASK2)........................................................................................................................................ 96
4.39 Reset Mask 2 (RST_MASK3)........................................................................................................................................ 97
4.40 Board Configuration Registers....................................................................................................................................... 98
4.41 Board Configuration 0 (BRDCFG0)...............................................................................................................................98
4.42 Board Configuration 1 (BRDCFG1)...............................................................................................................................99
4.43 Board Configuration 2 (BRDCFG2)...............................................................................................................................100
4.44 Board Configuration 3 (BRDCFG3)...............................................................................................................................101
4.45 Board Configuration 4 (BRDCFG4)...............................................................................................................................102
4.46 Board Configuration 5 (BRDCFG5)...............................................................................................................................103
4.47 Board Configuration 6 (BRDCFG6)...............................................................................................................................105
4.48 DUT Configuration Registers.........................................................................................................................................106
4.49 DUT Configuration 0 (DUTCFG0)................................................................................................................................ 106
4.50 DUT Configuration 1 (DUTCFG1)................................................................................................................................ 107
4.51 DUT Configuration 2 (DUTCFG2)................................................................................................................................ 108
4.52 DUT Configuration 11 (DUTCFG11)............................................................................................................................ 109
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Section number Title Page
4.53 Core Management Space Registers................................................................................................................................ 110
4.54 Core Management Address (CMSA)..............................................................................................................................111
4.55 Core Management Data (CMSD)................................................................................................................................... 112
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Chapter 1
LS1028ARDB Overview
The QorIQ®LS1028A reference design board (LS1028ARDB) is a computing,
evaluation, development, and test platform supporting the QorIQ LS1028A processor,
which is a dual-core Arm®Cortex®-v8 A72 processor with frequency up to 1.3 GHz. The
LS1028ARDB is optimized to support SGMII (1 Gbit/s), QSGMII (5 Gbit/s), PCIe x1 (8
Gbit/s), and SATA (6 Gbit/s) over high-speed SerDes ports, USB 3.0, DisplayPort, and
also a high-bandwidth DDR4 memory.
The LS1028ARDB can be used to develop and demonstrate human machine interface
systems, industrial control systems such as robotics controllers and motion controllers,
and PLCs. The reference design also provides the functionality needed for Industrial IoT
gateways, edge computing, industrial PCs, and wireless or wired networking gateways.
The board is lead-free and RoHS-compliant.
NOTE
The LS1043A processor is used in the LS1028ARDB for early
evaluation of board. Throughout this document, description of
LS1028ARDB features also applies to the board with the
LS1043A interposer, unless otherwise noted.
Developers using the LS1028ARDB can perform standard debugging tasks, such as:
• Upload and run code
• Set breakpoints
• Display memory and registers
• Connect and incorporate proprietary hardware into target systems using the LS1028A
as a host processor
• Use the LS1028ARDB as a demonstration tool
The board support package (BSP) is developed using the Linux operating system. The
onboard CPLD provides startup configuration information for the U-Boot and Linux.
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1.1 Acronyms and abbreviations
The table below lists and explains the acronyms and abbreviations used in this document.
Table 1-1. Acronyms and abbreviations
Term Description
CAN Controller area network
CCI Cache coherency interconnect
CPLD Complex programmable logic device
CTS Clear to send
DCM Development system control monitor
DDR SDRAM Double data rate synchronous dynamic random-access memory
DIP Dual inline package
DPAA Data path acceleration architecture
DQS Data strobe
DUART Dual universal asynchronous receiver/transmitter
DUT Device under test
EC Ethernet controller
ECC Error correcting code
eDP Embedded DisplayPort
EMI Ethernet management interface
ENETC Ethernet controller
eMMC Embedded multimedia card
eSDHC Enhanced secure digital host controller
FET Field-effect transistor
FPGA Field-programmable gate array
GbE Gigabit Ethernet
GPIO General purpose input/output
GT/s GigaTransfers/second
HDLC High-level data link control
HSSI High-speed serial interface
I2C Inter-integrated circuit
JTAG Joint Test Action Group (IEEE®Standard 1149.1™)
LOS Loss of signal
OCM Offline configuration manager
OTG On-The-Go
PBL Pre-boot loader
PLL Phase-locked loop
PMIC Power management multi-channel IC
POR Power-on reset
PSU Power supply unit
PTP Precision time protocol
Table continues on the next page...
Acronyms and abbreviations
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Table 1-1. Acronyms and abbreviations (continued)
Term Description
PWM Pulse width modulation
QSGMII Quad serial gigabit media independent interface
QSPI Quad serial peripheral interface
RCW Reset configuration word
RTC Real time clock
RTS Request to send
SATA Serial advanced technology attachment
SDRAM Synchronous dynamic random-access memory
SerDes Serializer/deserializer
SGMII Serial gigabit media independent interface
SPD Serial presence detect
SPI Serial peripheral interface
SS Spread spectrum
SSC Spread spectrum clocking
TCXO Temperature compensated crystal (Xtal) oscillator
UART Universal asynchronous receiver/transmitter
UDIMM Unbuffered dual inline memory module
UFT Universal frequency translator
USB Universal serial bus
XSPI Octal serial peripheral interface
1.2 Related documentation
The table below lists and explains the additional documents and resources that you can
refer to for more information on the LS1028ARDB.
Some of the documents listed below may be available only under a non-disclosure
agreement (NDA). To request access to these documents, contact your local field
applications engineer or sales representative.
Table 1-2. Related documentation
Document Description
QorIQ LS1028A Product Brief Provides a brief overview of the LS1028A processor
QorIQ LS1028A Data Sheet Provides information about electrical characteristics, hardware design considerations,
and ordering information
QorIQ LS1028A Family Reference
Manual
Provides a detailed description about the LS1028A QorIQ multicore processor and its
features, such as memory map, serial interfaces, power supply, chip features, and
clock information
Table continues on the next page...
Chapter 1 LS1028ARDB Overview
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Table 1-2. Related documentation (continued)
Document Description
QorIQ LS1028A Chip Errata Lists the details of all known silicon errata for the LS1028A
QorIQ LS1028A Reference Design
Board Getting Started Guide
Explains the LS1028ARDB settings and physical connections needed to boot the
board
1.3 Block diagrams
This section provides block diagrams showing major functional units of the LS1028A
processor and LS1028ARDB.
The figure below shows the LS1028A processor block diagram.
Watchpoint
Cross
Trigger
Trust Zone
Power Management
FlexSPI, 3x SPI
DUART, 6x LPUART
32-bit
DDR3L/4
Memory Controller
Real Time Debug
Perf
Monitor
8x I2C, GPIO
8x FlexTimer
Trace
SMMUs
2x USB3.0 w/PHY
CCI-400™ Coherency Fabric
2x SD/SDIO/eMMC
DMA
Core Complex
Accelerators and Memory Control
Basic Peripherals, Interconnect and Debug
Networking Elements
Security Engine (SEC)
6x SAI
1 MB L2 - Cache
32 KB
D-Cache
48 KB
I-Cache
ARM®Cortex®-A72
32b/64b Core
GPU
LCDC
eDP
Secure Boot
4-Lane 10 GHz SerDes
PCIe 3.0
PCIe 3.0
4 port 2.5G Switch TSN
Ethernet
ENETC
1G
2.5G TSN
SATA 3.0
Figure 1-1. LS1028A block diagram
The figure below shows the LS1028ARDB block diagram.
Block diagrams
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QSGMII PHY F104
LS1028
POWER SUPPLIES
(VDD, GVDD, etc.)
1600 MT/s
DDR4 4GB
SDHC1
JTAG
RS232 IO
USB
3.0
Port 2
I2C
SPD, INA220, TEMP, RTC etc.
DUART
DB9
DB9
JTAG
x1
DDR4
PWR
12V
FANS
12V
RST
Cadence
eDP
QIXMin
CPLD
(EPM2210F256C5N)
PCIe3.0 m.2
Slot
PCIe3.0 m.2
Slot
SATA 3.0
m.2
x1
x1
Display port
connector
47272-0001
Molex
CFG
C
L
O
C
K
S
DC
Switches
USB 3.0
type C
S
E
R
D
E
S
DIFF_
SYSCLK
DPCLK
5P49V5907
25 MHz
M.2 Slot
Clocks
USB
3.0
Port 1
USB 3.0
Type A
uCliq Module (x2)
BLE, BEE, NFC on
SPI/UART/I2C
ENETC
(1588)
SGMII PHY
AR8033 RJ-45 with
Transformer
SD1CLK
x2
CAN2 Standard
Display
CAN1 Standard
Display
CAN
transceiver
TJA1051
CAN
transceiver
TJA1051
x4 RJ-45 with
Transform
er
Rmux
A
B
C
D
eMMC-8GB
(MTFC8GAKAJCN-
1M WT)
Mux XSPI
A
SPI
Emulator
I2C
Micron xSPI NAND
512MB
(MT29F4G01ABBFD12-ITES:F)
SDHC2
Mux
10
11
8
6
9
7
5
3
4
21
12
SD Connector
SPI3 }Type-E
WiFi
Type-B
SATA
IEEE1588
Connector
Micron xSPI x8 NOR
256MB
(MT35XU02GCBA1G12)
Figure 1-2. LS1028ARDB block diagram
1.4 Board features
The table below lists the features of the LS1028ARDB.
Chapter 1 LS1028ARDB Overview
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Table 1-3. LS1028ARDB features
LS1028ARDB feature Specification Description
Processor Two-core processor Two Arm®Cortex®- A72 processor cores:
• Based on 64-bit ARMv8 architecture
• Up to 1.3 GHz operation
• Single-threaded cores with 48 KB L1 instruction cache and 32 KB
L1 data cache
• Arranged as a single cluster of two cores sharing a single 1 MB L2
cache
NOTE: For more details on the LS1028A processor, see QorIQ LS1028A
Family Reference Manual.
DDR memory DDR4 • Five onboard 1G x8 discrete memory modules (Four data byte lanes
+ ECC)
• 32-bit data and 4-bit ECC
• One chip select
• Data transfer rates of up to 1.6 GT/s
• Single-bit error correction and double-bit error detection ECC (4-bit
check word across 32-bit data)
High-speed serial ports
(SerDes)
One four-lane SerDes • Lane 0: Supports one 1 GbE RJ45 SGMII, connected through the
Qualcomm AR8033 PHY
• Lane 1: Supports four 1.25 GbE RJ45 QSGMII, each connected
through the NXP F104S8A PHY
• Lane 2: Connects to one PCIe M.2 Key-E slot to support PCIe Gen3
(8 Gbit/s) cards
• Lane 3: Connects to one PCIe M.2 Key-E slot and one SATA M.2
Key-B slot through a register mux to support either PCIe Gen 3 (8
Gbit/s) or SATA Gen 3 cards (6 Gbit/s) at a time
eSDHC eSDHC1 Supports a secure digital (SD) connector for connecting an external SD
3.0 card
eSDHC2 • Onboard 8 GB eMMC memory (MTFC8GAKAJCN) supporting
• x1, x4, and x8 I/Os
• SDR/DDR modes up to 52 MHz clock speed
• HS200/HS400 modes
SPI SPI3 Connects to two mikroBUS™ sockets to support mikro-click modules,
such as Bluetooth 4.0, 2.4 GHz IEEE 802.15.4 radio transceiver, near field
communications (NFC) controller
Octal SPI (XSPI) One XSPI (XSPI A) • One 256 MB onboard XSPI serial NOR flash memory
• One 512 MB onboard XSPI serial NAND flash memory
• Supports a QSPI emulator for offboard QSPI emulation
I2C Six I2C interfaces • All system devices are accessed via I2C1, which is multiplexed on
I2C multiplexer PCA9848 to isolate address conflicts and reduce
capacitive load
• I2C1 is used for EEPROMs, RTC, INA220 current-power sensor,
thermal monitor, PCIe/SATA M.2 connectors and mikro-click
modules 1 and 2
Serial ports Two UART ports
(UART1 and UART2)
• UART1 supports RS-232 levels of up to 1 Mbit/s data rate on a DB9
male connector. LTC8204 RS232 transceiver is used for interface
conversion. Hardware handshaking is not supported.
• UART2 can be used to interface with either mikro-click modules or
RS-232 transceiver LTC2804 (similar to UART1). The selection can
be controlled from FPGA.
Table continues on the next page...
Board features
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Table 1-3. LS1028ARDB features (continued)
LS1028ARDB feature Specification Description
CAN Two CAN ports (CAN1
and CAN2)
The two CAN DB9 ports can support CAN FD fast phase at data rates of
up to 5 Mbit/s.
Ethernet SGMII (1 GB Ethernet
port)
QSGMII (four 1 GB
Ethernet ports)
IEEE 1588™
• Five 1G/100M/10BaseT Ethernet ports supported. One port is
supported on SGMII ENET MAC and the other four through the TSN
switch.
• Five RJ45 connectors with link and activity status are used with the
SGMII and QSGMII interfaces
• IEEE 1588 precision time protocol (PTP) is supported through an
onboard header (J11) and SMA connector (J12) on the
PULSE_OUT1 signal for 1PPS timing signal generation
USB 3.0 Two high-speed USB
3.0 ports with
integrated PHYs
• Supports super-speed (5 Gbit/s) operations
• USB 3.0 port 1 is configured as host with a Type A connector
• USB 3.0 port 2 is configured as downstream facing port (DFP) or
upstream facing port (UFP) with a Type C connector
Display DisplayPort (not
supported by the
LS1043A processor)
• Supports display resolution of up to 4Kp60
• Supports link transfer rates of up to HBR2 (5.4 Gbit/s)
Clocks Differential system
clock (DIFF_SYSCLK)
100 MHz
SerDes clocks REF_CLK1 and REF_CLK2 of 100 MHz
Ethernet clocks 125 MHz clock to Ethernet controller either from the IEEE 1588 port or an
onboard oscillator
Display Port clock
(DP_REFCLK)
27 MHz
FPGA CLK 25 MHz clock to CPLD
Power supplies • 12 V input power from DC input adaptor
• 5.0 V for USB1, USB2, CAN1, CAN2, and mikro-click modules
• 1.0 V (VDD) for core and platforms
• Filtered 1.0 V / 0.9 V USB_SDVDD, USB_SVDD, DP_SVDD, SVDD
• 3.3 V for board components (SGMII PHY, M.2 connectors, SD card,
eMMC, CAN transceivers, mikroBUS connectors, LEDs, DP port,
CPLD IO and VDD, clockgen VDDO)
• Filtered 3.3 V for USB_HVDD
• 1.8 V for board components (UART transceivers, XSPI memories,
eMMC memory IO VDD, CPLD IO bank3)
• 1.8 V clockgen VDD and VDDA
• 1.8 V OVDD, TH_VDD
• Filtered 1.35 V X1VDD, AVDD_SD1_PLL1, AVDD_SD1_PLL2
• 2.5 V QSGMII PHY VDD25, VDD25A, and DDR4 memory VPP
• 1.0 V QSGMII PHY VDD, VDDA
• 1.2 V DRAM VDD
• 0.6 V DRAM VTT, VREF
• 3.3 V / 1.8 V EVDD for eSDHC
• 0.9 V / 1.0 V TA_BB_VDD
Debug interface • Arm Cortex 10-pin JTAG connector
• CPLD programming header
Package • Package type is Flip Chip, Plastic-ball, Grid Array (FC-PBGA), 17
mm x 17 mm
• Socket and heat sink are included
System logic CPLD • Manages the following:
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Table 1-3. LS1028ARDB features
LS1028ARDB feature Specification Description
• System reset sequencing
• SoC POR configuration at reset
• Implements registers for system control and monitoring
• General fault monitoring and logging
Board features
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Chapter 2
LS1028ARDB Functional Description
This chapter explains all major functional components of the LS1028ARDB. The chapter
is divided into the following sections:
•Processor
•Power supplies
•Clocks
•DDR interface
•USB interface
•DisplayPort
•SerDes interface
•Ethernet controller interface
•M.2 connectors
•DUART interface
•CAN interface
•I2C interface
•XSPI interface
•JTAG port
•eSDHC interface
•Mikro-click modules
•GPIOs
•Interrupt handling
•Temperature measurement
•System controller
2.1 Processor
The LS1028ARDB board is based on the QorIQ LS1028A processor having two Arm®
Cortex®- A72 processor cores. The LS1028ARDB board supports as many features of
the LS1028A as possible. In addition, the LS1028ARDB board supports an LS1043A
interposer that allows early evaluation of the board with limited features and restrictions.
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As a restriction, the following interfaces cannot be tested using the LS1043A interposer:
• DisplayPort
• SDHC2
• Octal SPI (XSPI)
• CAN
2.2 Power supplies
The LS1028ARDB generates all the voltages necessary for the correct operation of the
LS1028A processor, DDR4, PHYs, and numerous other peripherals. All power is derived
from an external 12 V DC power supply.
The following figures show the block diagram of LS1028ARDB power supplies:
DDR3/2 PS
1.35/1.5V/1.8V
USB_SDVDD
0.9V/1.0V@ 0.2A
USB_SVDD
0.9V/1.0V@ 0.2A
SVDD
0.9/1.0 @ 5A
LPFx2
LPF
LPF
LS1028 USB_SDVDD
LS1028 USB_SVDD
LS1028 SVDD
CORE & PLAT
Current
Measuring
INA220
I2C1_CH2
VDD=1V0
Est 7A
VDD_CORE_PL
1mOHm
WSL27261L000FEA 3W
VDD
1/0.9 V@ 11A
DP_SVDD
0.9V/1.0V@ 0.1A
LPF LS1028 DP_SVDD
12V0
J5
12V, 5A
Adaptor CHASSIS FAN1
LTC7151S
VIN
PS_VDD_PG
LED
LTC7151S
VIN
PS_3V3_PG
LED
3.3V
3.3V @ 15A
VDD
3V3
PS_3V3_PG LT8609SEV
VIN
PS_5V0_PG
5.0V
5V @ 2A
5V0
LPF x2 LS1028 USB_HVDD
USB_HVDD
3.3V @ .45 A
POWER
SWITCH
LTC2955-2 PWR_EN
12V0_IN
J3
J4
CHASSIS FAN2
DUT SOCKET FAN
PS_VDD_EN
BOARD COMPONENTS
CLOCKGEN VDDO
CPLD IO & VDD
DP PORT DP_PWR
SGMII PHY
M.2 CONNECTORS
SD CARD
eMMC MEMORY
I2C EEPROMs
CURRENT MONITOR INA220
TEMPERATURE MONITOR SA56004ED
RTC PCF2129AT
CAN TRANSCEIVERS
MIKROBUS CONNECTORS
LEDs
MISC PARTS (BUFFERS & TRANSLATORS
BOARD COMPONENTS
USB 1 (TYPE C) AND 2 (TYPE A)
CAN TRANSCEIVERS
MIKROCLICK MODULES
Figure 2-1. Power supplies - Part 1
Power supplies
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LS1028 EVDD
to CPLD
PS_DDR_EN
VR500
PS_VDD_EN
LPFx6
to regulators
LS1028 PROG_MTR
HDR 1x2
LS1028 TA_PROG_SFP
HDR 1x2 1K
1K
2.5V @0.8A
POR_OUT_VR500_B
PS_3V3_EN
EVDD SWITCH
FPF1321UCX 3.3V/1.8V
VOUT2
VOUT1
LS1028 AVDD_CGA1
LS1028 AVDD_CGA2
LS1028 AVDD_PLAT
LS1028 DP_SAVDD
LS1028 AVDD_D1
LS1028 AVDD_PIXEL
1V0
1.0V @ 1.1A QSGMII PHY VDD, VDDA
VOUT3
VOUT4
QSGMII PHY VDD25, VDD25A
DDR4 MEMORY VPP
LPFx2
X1VDD
1.35V LS1028 X1VDD
1.35V@0.4A AVDD_SD
1.35
LPFx4
LS1028 AVDD_SD1_PLL1
LS1028 AVDD_SD1_PLL2
2V5
1V35
BOARD COMPONENTS
CLOCKGEN VDD & VDDA
CPLD IO BANK3
UART TRANSCEIVER
XSPI MEMORIES
eMMC MEMORY IO VDD
MISC PARTS (BUFFERS & TRANSLATORS)
LS1028 OVDD, TH_VDD
1.8V
@2.5A
{
EN
PORB
LDO2
LDO4
1V8
3.3V
1.8V
SD_VSEL
from LS1028
SD_VS EL: EV DD
0 : 3.3V
1 : 1.8V
GVDD
1.2V @ 5A
MC34716EP/R2
DDR4 VDDQ,
VTT, VREF
VDDQ,SINK/SOURCE
DDRTERMINATION
REGULATOR
PS_DDR_EN
PS_DDRREG_PG_B
VTT
0.60V @ 3A
VREFCA_S
0.60V @ 3A
To CPLD
3V3
DRAM VTT
DRAM VREFCA_S
LS1028 VCC_GVDD
VCC_GVDD_S DRAM VDD
SD_B
3V3 PVIN1:4
VLDOIN
1V2
VTT-0V6
MVREF-0V6
EVDD
LS1028 TA_BB_VDD
TA_BB_VDD
0.9V/1.0V @ .15A
MAX8902B
3.3V
BAT
3V_STBY
TA_BB_VDD
Figure 2-2. Power supplies - Part 2
Note that several power supplies have onboard low-pass filters, to prevent board
switching noise from coupling into sensitive analog supplies. The figure below shows the
filters used.
2.2uF 2.2uF
2.2uF=NFM18PC225B1A3
2.2uF=GRM155R60J225KE95
LPF
LPF
47uF 3nF
4.7uF
0.33OHm
LPF
10uF 1uF
5.1OHm
0.22uF
Figure 2-3. Passive low pass filters
Chapter 2 LS1028ARDB Functional Description
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2.2.1 Primary power supply
The LS1028ARDB is powered up through an external 12 V DC power adapter. The
specifications of the DC adapter are as follows:
• Input: 100 - 240 VAC, 50 - 60 Hz
• Output: 12 V, 0 - 5 A DC power supply adapter (160 W) - Standard
• DC Jack (2 pin, 2.5 mm x 5.5 mm x 11 mm)
2.2.2 Secondary power supplies
The following table lists different power supply components used to generate various
LS1028ARDB power supplies.
Table 2-1. Secondary power supplies
Part
identifi
er
Manufacturing
part number
Part
manufacturer
Power
supply
Specifications Description
U1 LT8609SEV Linear
Technology
5V0 5 V at 2 A Supplies power to the board components:
• USB 1 and USB 2 connectors
• CAN transceivers
• Mikro-click modules
U2 LTC7151S Linear
Technology
VDD 1.0 V / 0.9 V at 20 A1Supplies power to the LS1028A core
supplies.
NOTE: Filtered VDD also powers USB
(USB_SDVDD, USB_SVDD),
Display Port (DP_SVDD), and
SerDes (SVDD) power supplies of
LS1028A.
U3 LTC7151S Linear
Technology
3V3 3.3 V at 15 A Supplies power to board components:
CPLD IO and VDD, Display Port, SGMII
PHY, M.2 connectors, SD card, eMMC
memory, I2C EEPROMs, current monitor
(INA220), Temperature monitor
(SA56004ED), CAN transceivers,
mikroBUS connectors, misc components
(buffers and translators).
NOTE: Filtered 3V3 also powers USB
(USB_HVDD of LS1028A).
U4 MC34716EP NXP
Semiconductors
1V2 1.2 V at 4 A DDR4 DRAM memories
LS1028A DRAM controller core and I/O
VTT_0V6 0.6 V at 3 A Address and control bus termination supply
MVREF 0.6 V at 3 A Reference voltage for DDR4 DRAM
memories
Table continues on the next page...
Power supplies
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Table 2-1. Secondary power supplies (continued)
Part
identifi
er
Manufacturing
part number
Part
manufacturer
Power
supply
Specifications Description
U6 MC34VR500V9
ES
NXP
Semiconductors
1V0, 2V5,
1V35, 1V8
• 1.0 V at 1.1 A
• 2.5 V at 0.8 A
• 1.35 V at 0.4 A
• 1.8 V at 2.5 A
Multi-output DC/DC regulator with four
switched outputs, two LDO outputs (VDD
and DDR enable), and one reset control
output to CPLD (RST_OUT). Four switched
outputs are:
• SW1LX: 1.0 V for the QSGMII PHY
VDD and VDDA
• SW2LX: 2.5 V for QSGMII PHY
VDD25, VDD25A, and DDR4
memory VPP
• SW3LX: 1.35 V; Filtered 1.35 V is
supplied to LS1028A X1VDD,
AVDD_SD1_PLL1, and
AVDD_SD1_PLL2
• SW4LX: 1.8 V for board components:
UART transceiver, XSPI memories,
eMMC memory IO, CPLD IO bank3,
clockgen VDD and VDDA
NOTE: Filtered 1V8
also powers
LS1028A power
supplies:
AVDD_CGA1,
AVDD_CGA2,
AVDD_PLAT,
DP_SAVDD,
AVDD_D1, and
AVDD_PIXEL.
NOTE: Jumper-enabled
1V8 also powers
PROG_MTR
and
PROG_SFP.
U7 FPF1321UCX ON
Semiconductor
EVDD 3.3 V
1.8 V
eSDHC IO Power.
NOTE: EVDD boots up to 3.3 V and can
be changed to 1.8 V depending
upon the SD_VSEL pin state that
is controlled from the LS1028A
SDHC IP block.
NOTE: The FPF1321UCX is a power
switch, not a power supply.
.
U8 MAX8902B Maxim
Integrated
TA_BB_VD
D
0.9 V / 1.0 V at 0.15
A
Power supply for TA_BB_VDD.
1. VDD is 1.0 V or 0.9 V depending upon the state of GPIO1_DAT24 GPIO pin of LS1028A.
Chapter 2 LS1028ARDB Functional Description
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
NXP Semiconductors 19
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2.2.3 Power supply sequence
The LS1028ARDB board is configured to switch ON automatically when the 12 V power
supply is switched ON and is connected to jack (J1) on the board.
The 12 V input can be subsequently power cycled using the following events:
• The power switch (push button) is pressed
• The register bit, PWR_CTL2[PWR], is set to ‘1’ using the I2C or JTAG/CCS
communication paths
On the availability of 12 V supply to the power regulators, the orderly enable of all power
supplies are sequenced using powergood of the regulators, as shown in the following
figure.
Power supplies
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