NXP Semiconductors IMXRT500HDG Guide

IMXRT500HDG
i.MX RT500 Hardware Design Guide
Rev. 0 — 15 November 2022 User guide
Document information
Information Content
Keywords IMXRT500HDG, i.MX RT500, MIMXRT595-EVK
Abstract This user guide provides details about the system hardware design to help
the users to develop their i.MX RT500 based designs

NXP Semiconductors IMXRT500HDG
i.MX RT500 Hardware Design Guide
1 Introduction
This user guide provides details about the system hardware design to help the users to
develop their i.MX RT500 based designs. Recommendations and examples from the
NXP MIMXRT595-EVK board are also included in the following section to illustrate the
concepts.
1.1 MIMXRT595 hardware design guidelines overview
This section provides an overview of MIMXRT595 hardware design guidelines and lists
the detailed description of:
•Power domains: Multiple power domains on the chip and how to filter or decouple them
•External clocks: External system clocks that are available on the chip
•Debug, trace, scan, and programming: Connections review
•Layout recommendations: Requirements for EVK layout
For more details, see Figure 1.
BOOT setting
USB
DNP
FC6_I2S/SD1/FC0_UART
FC8_I2C
MIPI BUS
PDM
SWD/JTAG/UART/I2C
RST USER KEY x2
FlexSPI1
FlexSPI0
SD0
HS SPI
GPIO
FLEX IO
ADCs
I3C0
FC1_I2S
RT595 AB
M.2 Mini
connector
QSPI NOR FLASH
IS25WP064AIBLE
QSPI NOR FLASH
MX25UM51345GXDI
00
PIN-to-PIN OPTION
PSRAM
APS6408L-OBM-BA
PSRAM
APS6408L-OBM-BA
eMMC
MTFC8GAKAJCN
HC SPI
interface
2 pins
Conn
2 pins
Conn
SD slot
MIPI-DSI
FPC conn
FlexlO_l2C
FlexlO_l2C
Pmod
Female Conn
UART I/F
SWD I/F
JTAG I/F
DMIC
Connector
2 x 6 pins
LPC-LINK
Module
Motion Sensor
FXOS8700CQ
FlexIO
2x14 socket
ARDUINO
UNO R3 socket
RGB LED
13C Connector
1x3 pins
MIMXRT595
249-pin eWLB (FOWLP)
7.0 mm x 7.0 mm, 0.4 mm pitch
Mic
8
88
4
4
Codec
WM8904
Left D amplifier
TFA9896UK
Right D amplifier
TFA9896UK
Line Out
Line In
Figure 1. MIMXRT595 block diagram
Key features:
•28FDSOI Technology
•Cortex M33
•Fusion F1 DSP
•Graphics Subsystem
•5 MB Low Leakage SRAM
•Connectivity
•Timers
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Operating characteristics:
•Power supply:
–VDDCORE: 0.6 V to 1.155 V
–VDDIO_0/1/2/4: 1.71 V to 1.89 V
–VDDIO_3: 1.71 V to 3.6 V
•Temperature range (ambient): -20 C° to +70 C°
2 Acronyms and abbreviations
Table 1 defines the acronyms and abbreviations used in this document.
Acronym Definition
BGA Ball Grid Array
CLKIN Clock-In
CMOS Complementary Metal-Oxide-Semiconductor
FOWLP Fan-Out Wafer-Level Package
GPIO General-Purpose Input/Output
HDI High Density Interconnect
ISP In-System Programming
ITM Instrumentation Trace Macrocell
LDO Low-Dropout Regulator
MCU Microcontroller Unit
MLCCs Multi-layer Ceramic Capacitors
OTP One-Time-Programmable
PCB Printed-Circuit board
PFM Pulse-Frequency Mode
PMIC Power Management IC
PWM Pulse Width Modulation
PIU Port Interface Unit
QFN Quad Flat-pack No Lead
QSPI Quad Serial Peripheral Interface
RTC Real-Time Clocks
SDIO Secure Digital I/O
SWD Serial Wire Debug
SWO Serial Wire Output
SWC Serial Wire Clock
WLCSP Wafer-Level Chip-Scale Package
WLCSP Wafer-Level Chip-Scale Package
XTAL Crystal
Table 1. Acronyms and abbreviations
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i.MX RT500 Hardware Design Guide
3 Power domains
This section provides details about the power domains on the chip and in the system.
3.1 i.MX RT500 power domains always-on, GPIO, and analog
The i.MX RT500 has several digital and analog supplies to power internal circuits and
the GPIO ports that interface to the system. Table 2 lists the power rails; minimum,
maximum, and typical voltages for each power rail.
Note: The minimum recommended filtering for each supply, including the bulk storage
and local decoupling capacitors; and a short description of the domain supply.
•VDD_AO1V8 is a low power always-on supply that powers the internal modules and
system registers that keep the chip ready to respond to low-power wake-up events.
These include the real-time clock module, general-purpose registers, the RESETN
input, and PMIC control pins.
•The chip has five separate GPIO power domains that are used to source I/O functions
around the chip. All five I/O power rails operate at 1.8 V, and one (VDDIO_3) can
operate at 3.3 V as well.
•The VDD1V8 power rail supplies on-chip analog functions.
Power rail MIN
(V)
TYP
(V)
MAX
(V)
Decoupling and bulk
capacitors (min qty)
Description
VDD_
AO1V8
1.71 1.8 1.89 1 × 0.22 μF + 1 × 1 μF 1.8 V supply for always-on
features. It includes the RTC
module, general-purpose
GPREG[7:0] registers, and the
RESETN and PMIC control
pins (LDO_ENABLE, PMIC_
IRQ_N, PMIC_MODE0, and
PMIC_MODE1).
VDDIO_0 1.71 1.8 1.89 3 × 0.22 μF + 1 × 10 μF 1.8 V power supply for GPIOs
VDDIO_1 1.71 1.8 1.89 3 × 0.22 μF + 1 × 10 μF 1.8 V power supply for GPIOs
VDDIO_2 1.71 1.8 1.89 1 × 0.22 μF + 1 × 1 μF 1.8 V power supply for GPIOs
1.71 1.8 1.89VDDIO_3
3.0 3.3 3.6
1 × 0.22 μF + 1 × 1 μF 1.8 V or 3.3 V power supply for
GPIOs
VDDIO_4 1.71 1.8 1.89 1 × 0.22 μF + 1 × 1 μF 1.8 V power supply for GPIOs
VDD1V8
VDD1V8_1
1.71 1.8 1.89 5 × 0.22 μF + 1 × 10 μF 1.8 V supply voltage for on-
chip analog functions.
VDD1V8_1 powers the On-
Chip OTP Control module.
Table 2. Power rails
3.2 i.MX RT500 power domains, ADC, and CORE logic supplies
1. The ADC operates at 1.8 V and can only measure up to the VDDA level, see in the
VDDA_ADC1V8 row of Table 3.
2. The VDDCORE is the internal core logic supply that requires a 1.0 V for Power-On and
can be changed in the application.
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The minimum voltage is 0.7 V in active mode to save power, but the level can
be reduced in retention mode. This supply requires quite a bit of decoupling
capacitance. Refer the following steps on how to apply the minimum quantity of
capacitors across the 12 of VDDCORE pins.
•When LDO_ENABLE is externally tied low, the user must boot at VDDCORE = 1.0
V or higher (low-power/normal clock mode - OTP setting - BOOT_CLK_SPEED)
or VDDCORE = 1.13 V (High-Speed clock - OTP setting - BOOT_CLK_SPEED).
Thereafter, the VDDCORE can be adjusted to the desired level.
•When LDO_ENABLE is externally tied high, the on-chip regulator to the VDDCORE
core voltage in PMC is set to the default value of 1.05 V (low-power/normal clock
mode - OTP setting - BOOT_CLK_SPEED) or 1.13 V (high-speed clock - OTP setting
- BOOT_CLK_SPEED). Thereafter, the POWER_SetLdoVoltageForFreq API
function can be used internally to configure the on-chip regulator voltage for the
VDDCORE.
•When performing any OTP read/write function, the VDDCORE voltage must be set to
1.0 V or higher when LDO_ENABLE is externally tied high or low.
3. For the ADC analog reference, VREFP is a 1.8 V reference that must be the same
level as for VDDA_ADC1V8.
Power rail MIN (V) TYP (V) MAX (V) Decoupling and
bulk capacitors
(min qty)
Description
VDDA_ADC1V8 1.71 1.8 1.89 1 × 0.22 μF 1.8 V analog supply
voltage for ADC.
VDDA_BIAS 1.71 1.8 1.89 1 × 0.22 μF + 1
× 1 μF
For ADC and
comparator input range
from 0 – 1.8 V
0.6 1.0 1.155 The minimum voltage
is 0.6 V in retention
mode, and 0.7 V in
active mode.
0.7 1.0 1.155 Power supply for
core logic may be
supplied from the on-
chip regulator or by an
off-chip PMIC.
External filter
capacitors are always
required on these pins.
For details, see the
power connection
information for
values and other
recommendations.
VDDCORE
1.0 1.0 1.155
5 × 0.22 μF + 1
× 10 μF
The minimum voltage
of 1.0 V is required for
initial power on
VREFP 1.71 1.8 1.89 1 × 0.22 μF ADC positive reference
voltage input
Table 3. ADC and CORE logic supplies
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3.3 i.MX RT500 power domains, internal regulator
The LDO_ENABLE input signal is listed in this power domain section because it is the
control signal that enables the internal VDDCORE LDO regulator when an external
VDDCORE supply is not used. This pin is pulled high to enable the internal LDO and tied
low when an external supply provides VDDCORE. Refer to Section 3.6.
Along with the minimum quantities of bulk and decoupling capacitors, we must see Note
on where to place the capacitors and parametric recommendations for the capacitors.
In the high-speed designs, which use ball-grid array packaging, the balls are soldered to
the top layer, the signals are routed on at least two layers, and the power pins are routed
on two or more other layers. The area directly below the MCU on the bottom layer is
where most, if not all, of the decoupling capacitors should be connected to the ground
and power domains.
Capacitor package size, tolerance, rated voltage, and dielectric recommendations are
presented for the three main capacitors used in the decoupling networks, see Table 4.
Capacitor information is presented in the Section 7.
Signal Description
LDO_ENABLE This input enables the on-chip regulator to
power core logic through the VDDCORE pins
when high. Tie low if an off-chip PMIC is used to
supply power to the core logic.
This pin cannot be left floating. A 100 kohm
external pull-up or 10 kohm external pull-down
resistor is recommended.
Table 4. Capacitor information
Note:
1. Decoupling and bulk capacitors must be placed on the bottom side of the PCB,
underneath the MCU for the smallest loops.
•For the 0.22 μF capacitors, use the 0201 packages, 10 V, 20 %, X5R, or X7R
•For the 1 µF capacitors, use the 0402 packages, 10 V, 10 %, X5R, or X7R
•For the 10 µF capacitors, use the 0603 packages, 16 V, 20 %, X5R, or X7R
Note: The 0805 package is acceptable.
3.4 Power domains for GPIO
Table 5 lists the GPIO in the specific VDDIO and VDD_AO1V8 domains.
VDDIO rail GPIO pins
PIO0_0 to PIO0_13
PIO1_11 to PIO1_15
PIO1_18 to PIO1_29
PIO2_14 to PIO2_15
PIO3_25 to PIO3_29
PIO4_0 to PIO4_6
VDDIO_0
PIO6_27
Table 5. Domains
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VDDIO rail GPIO pins
PIO0_14 to PIO0_19
PIO0_21 to PIO0_25
PIO0_28 to PIO0_31
PIO1_0
PIO1_3 to PIO1_7
PIO1_9 to PIO1_10
PIO2_24 to PIO2_31
PIO3_1 to PIO3_3
PIO4_11 to PIO4_17
PIO4_18
PIO5_4, PIO5_8
PIO5_15 to PIO5_18
PMIC_I2C_SCL
VDDIO_1
PMIC_I2C_SDA
PIO1_30 to PIO1_31
PIO2_0 to PIO2_8
VDDIO_2
PIO2_9 to PIO2_11
PIO4_20 to PIO4_31VDDIO_3
PIO5_0 to PIO5_3
PIO3_8 to PIO3_18VDDIO_4
PIO3_19 to PIO3_21
RESETN
LDO_ENABLE
PMIC_IRQ_N
PMIC_MODE0 and PMIC_MODE1
VDD_AO1V8
RTCXIN and RTCXOUT
Table 5. Domains...continued
•VDDIO_0, VDDIO_1, VDDIO_2, and VDDIO_4 supplies can be powered between 1.71
V to 1.89 V.
•VDDIO_3 can be powered between 1.71 V and 3.6 V.
3.5 Power-on sequence using PMIC (internal LDO disabled)
The internal and external power rails must follow a sequence to avoid start-up issues.
These sequences using a PMIC for the VDDCORE node, with the internal CORE LDO
disabled, and external supplies with the internal VDDCORE regulator enabled are similar.
1. The always-on supply must be powered first or in conjunction with the VDD1V8
supplies which power the main digital functions that initialize the MCU.
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2. PMIC mode pins are the outputs that are controlled by an always-on supply. These
pins must have external pullups to VDD_AO1V8 and get validated after several
microseconds once VDD_AO1V8 is stable.
3. The VDDA_ADC1V8 supply and VREFP reference are powered-up at the same time as
VDD1V8 or later.
4. The VDDIO rails and VDDA_BIAS are also powered at the same time as VDD1V8 or
later.
CAUTION: When VDDIO_3 is 3.0 V, there must be a delta of not more than 1.89 V
during the rampup.
5. VDDCORE is powered last by the PMIC, which handles the power sequencing.
Note: When LDO_ENABLE is externally tied low, the user must boot at VDDCORE =
1.0 V or higher (Low-power / Normal clock mode - OTP setting - BOOT_CLK_SPEED)
or VDDCORE = 1.13 V (High-Speed clock - OTP setting - BOOT_CLK_SPEED).
Thereafter, the VDDCORE can be adjusted to the desired level. The PMIC also
provides the RESETN deassertion after VDDCORE is stable.
When a PMIC is not used, enable the internal VDDCORE LDO to provide VDDCORE. The
PMC releases RESETN internally when VDDCORE is stable.
Note: For ERR050716, generally, all 1.8 V power pins are supplied by the same
regulator, so all are applied at the same relative time. Decoupling capacitor charging
delays are not considered to be significant when all the 1.8 V domains are powered at
the same time.
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VDD_AO1V8
1
2
3
4
5
PMIC_MODE0/1
VDD1V8, VVD1V8_1
VDDIO_0, 1, 2, 3, 4
VDDA_BIAS
VDDIO_3(3.3V)
VDDCORE
RESETN
VDDA_ADC1V8, VREFP
ERR050716: VDDIO_x should be
powered at same time as VDD1V8
Figure 2. Power-on sequence
The power-on sequences are shown in the Figure 2 are as follows:
1. VDD_AO1V8, VDD1V8, and VDD1V8_1 should be powered first. If using PMIC, mode
pins are pulled-up to always-on supply until mode pins are active.
2. VDDA_ADC1V8 and VREFP can be powered concurrently with VDD_AO1V8 and
VDD1V8 or later.
3. VDDIO_x and VDDA_BIAS can be powered concurrently with VDD1V8 range or later.
The delta voltage between VDDIO_3 and VDD1V8 must be 1.89 V or less when
VDDIO_3 is 3.3 V.
4. Power-up VDDCORE should not be ramped-up until after all the other supplies have
completed the rampup.
5. Hold RESETN low until VDDCORE is valid when PMIC is used. The only difference
when using internal VDDCORE LDO (LDO_ENABLE = 1) is that internal PMC releases
internal RESETN when VDDCORE is stable.
3.6 NXP PCA9420 PMIC
The NXP PCA9420 PMIC designed to be used with the i.MX RT500 and i.MX RT600
microcontrollers. This PMIC has two LDO regulators and two switch-mode regulators.
This PMIC is available in two small packages:
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•BGA-style wafer level chip scale package WLCSP
•24-pin quad flat pack, no leads QFN
The block diagram shown in Figure 3 has taken from the PCA9420 data sheet.
PCA9420
VIN
ASYS
VBAT
1-cell
Li-Ion
battery
+ (VBAT)
- (GND)
PSYS1
PGND1
LX1
SW1_OUT
PSYS2
PGND2
LX2
2.2 µH
SW2_OUT
VDDCORE
LDO1_OUT
LDO2_OUT
VBAT_BKUP
Always-on
1.8 V
Default
3.3 V
OFF
ON On-Key
button
2.2 µF
10 V
AGND1 AGND2
VBAT
Coin
battery
ON
SCL
SDA
TS
NTC
VDD_ AO1V8
Option
ADC
MODESEL0
MODESEL1
AGND3
SYSRSTn
INTB
R1
R1=R2=100-220 kΩ
R2
PMIC_IRQN
(VDD_AO1V8)
25-Bump WLCSP, 0.4 mm pitch,
2.1 mm x 2.1 mm
ASYS
Default: 1.0 V
Default: 1.8 V VDDIO_1,2,3
and/or 4
Note: A ll dir ectio ns for the arrows in the
schematic are made from t he PCA9420
pe rspective.
Short on PCB
i.MXRT
RT5xx
RT6xx
VDD1V8 and
other 1.8 V power
PMIC_I2C_SCL
(VDDIO_1)
PMIC_I2C_SDA
(VDDIO_1)
VDD_AO1V8
VDDIO_1,2,3,
and/or 4
USB1_VDD3V3
and other
3V.3V power
RESETN
(VDD_AO1V8)
PMIC_MODE0
(VDD_AO1V8)
PMIC_MODE1
(VDD_AO1V8)
Option: can be removed if an
internal pull-up R is available
on i.MXRT* device
VDDIO_1
Input supply
VBUS
GND
C1
C4
D2
E1
D1
B3 C3 E2
C2
D3
D4
E5
D5
B4
B5
A5
C5
B2
A3
A4
A2
B1
A1
If a coil cell is not used, tie
with the VBAT power domain
If the pin is not used,
leave the pin open
If the pin is not used,
leave the pin open
If the pin is not used,
leave the pin open
MODESEL1 MODESEL0
EN_MODE_SEL_BY_PIN_x=1 (x can be 0, 1, 2 or 3)
LOW (0)
HIGH (1)
LOW (0)
LOW (0)
HIGH (1) LOW (0)
HIGH (1) HIGH (1)
Output voltage setting
Mode setting 0
Mode setting 1
Mode setting 2
Mode setting 3
Can be connected to any ADC
* : Regardless of mode setting
1.5 V to 2.1 V or 2.7 V
to 3.3 V
Input current lim it (typica l): 85 mA, 255 mA, 425 mA, 595 mA,
765 mA, 935 mA, 1105 mA or disab le
Regulator Default (V)* Output range
BUCK1 1.0 (MTP)
1.8 (MTP)
1.8 (MTP)
3.3 (MTP)
0.5 V to 1.5 V and fixed
1.8 V
BUCK2
LDO1
LDO2
1.5 V to 2.1 V or 2.7 V
to 3.3 V
1.7 V to 1.9 V
Resolution
25 mV
Max current
250 mA
25 mV
25 mV
25 mV
500 mA
1 mA
250 mA
Linear charger: 0 mA to 315 mA in 5 mA steps for charge current
VIN ≤ 6 V
If VIN is greater than 6 V, the voltage
rating on the capacitor of 2.2 µF/10 V
shall be changed to a higher
voltage than a maximum voltage
in applications.
i.MXRT
RT5xx
RT6xx
E4
E3
0.47 µF
6.3 V
1 µF
6.3 V
2.2 µF
6.3 V
10 µF
6.3 V
2.2 µF
10 V
2.2 µH
10 µF
6.3 V
4.7 µF
10 V
1 µF
10 V
1 µF
10 V
Figure 3. PCA9420 simplified block diagram
•Power Management IC for low-power microcontroller applications
•Two LDO regulators and two switch-mode regulators
•5 x 5 bump WLCSP or 24-pin QFN package −EVK uses the WLCSP package
3.7 MIMXRT595-EVK PMIC supply assignments
Figure 4 focuses on the output portion of the PCA9420 PMIC, as we see the two LDO
outputs on the left and the two switching outputs on the right.
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PCA9420
LX1
SW1_OUT
PSYS2
PGND2
LX2
2.2 µH
SW2_OUT
VDDCORE
LDO1_OUT
LDO2_OUT
Always-on
1.8 V
Default
3.3 V ASYS
Default: 1.0 V
Default: 1.8 V VDDIO_1,2,3
and/or 4
VDD1V8 and
other 1.8 V power
VDD_AO1V8
VDDIO_1,2,3,
and/or 4
USB1_VDD3V3
and other
3V.3V power
E1
D1
B4
B5
A5
C5
B2
A3
i.MXRT
RT5xx
RT6xx
1 µF
6.3 V
2.2 µF
6.3 V
10 µF
6.3 V
2. 2 µF
10 V
2.2 µH
10 µF
6.3 V
Figure 4. PMIC supply
PMIC Supply Description Power rail
LDO1_OUT Low power always-on 1.8 V
supply
VDD_AO1V8
LDO2_OUT 3.3 V supply USB1_VDD3V3, VDDA_BIAS,
VDDIO_3
SW1_OUT 1.0 V core supply VDDCORE, MIPI_DSI_VDD11
SW2_OUT High current 1.8 V supply VDD1V8, VDD1V8_1, VDDIO_
0, VDDIO_1, VDDIO_2,
VDDIO_3, VDDIO_4, VDDA_
ADC1V8, VREFP
Table 6. PMIC supply
•LDO1_OUT is configured as the low power always-on supply, which also biases the
RESETN and PMIC control signal pull-up resistors.
•LDO2_OUT is configured as the main 3.3 V supply for the USB module, and the
VDDIO_3 domains.
•SW1_OUT is configured to provide the 1.0 V CORE supply, which is also used by the
MIPI_DSI module.
•SW2_OUT is the high current 1.8 V supply that powers the remaining 1.8 V domains and
loads.
Note: The SW2 _OUT operates in Pulse-Frequency Mode (PFM) under low load
conditions (less than 50 mA) for power efficiency and 1 MHz Pulse Width Modulation
(PWM) mode for higher loads. In the low load condition, PFM operation generates more
than 20 mV of ripple on this supply, which can propagate to the main oscillator and cause
a jitter. If the MCU operates under low load conditions and clock jitter is not acceptable,
an external 1.8 V LDO regulator must be used for the VDD1V8 supply.
Note: You can request specific default power supply voltages and sequences for the
PMIC and the PMIC team generates a new part number for you.
4 i.MX RT500 power domains, other power rails
Other power rails include:
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•USB 3.3 V supply
•1.1 V MIPI_DSI_VDD11 supply for the MIPI_DSI digital core (which we recommend
tying to the VDDCORE supply)
•1.8 V MIPI_DSI_VDD18 supply for the MIPI_DSI PHY
•1.8 V MIPI_DSI_VDD18_VDDA_CAP domain, which requires a stabilization capacitor
for this internal domain
•USB1_VBUS is a 3 V to 5 V signal from the USB connector, which is used to detect the
presence of an active USB cable. This is an input rather than a power rail.
•There are several internal VSS connections VSS, VSSA, MIPI_DSI_VSS, and VREFN
that must be tied to a common ground node.
Regarding the termination of unused pins, see Table 7. For more details, see Section
"Termination of unused pins" of i.MX RT500 Low-Power Crossover Processor Data Sheet
with Addendum (document IMXRT500EC).
Power rail MIN (V) TYP (V) MAX (V) Decoupling
and bulk
capacitors
(min qty)
Description
USB1_VDD3V3 3.0 3.3 3.6 1 × 0.22 μF USB1 analog 3.3 V
supply
USB1_VBUS 3.0 5.0 5.5 1 × 0.22 μF USB1_VBUS input
to validate USB
presence
MIPI_DSI_VDD11 0.85 1.1 1.155 1 × 0.22 μF MIPI DSI 1.1 V
digital core input
voltage supply.
Recommend trying
to VDDCORE
voltage.
MIPI_DSI_VDD18 1.71 1.8 1.89 1 × 0.22 μF MIPI DSI 1.8 V
PHY I/O input
voltage supply
MIPI_DSI_VDD18
_VDDA_CAP
— — 1.155 1 × 0.22 μF Internal domain
VREFN — 0 — — ADC negative
reference voltage.
Tie to GND
VSSA — 0 — — Analog negative
supply. Tie to GND
VSS — 0 — — MCU negative
supply. Tie to GND
MIPI_DSI_VSS — 0 — — MIPI_DSI_VSS. Tie
to GND
Table 7. Other power rails
5 External clocks
This section provides details about the crystal oscillators, external clock input, and
versatile CLKOUT output.
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5.1 External clocks
The main crystal oscillator (XTALIN / XTALOUT) can drive crystals from 4 MHz to 32
MHz.
The main crystal oscillator can operate in low-power or high gain modes, while the
possible frequency range is 4 MHz to 32 MHz, the practical range is 5 MHz to 26 MHz
due to limitations of the on-chip PLLs.
The Real-Time Clock (RTC) oscillator (RTCXIN / RTCXOUT) is strictly for:
•32 kHz real-time clock (RTC) that can be used as a system clock and as timer clocks
•Internal load capacitor selection 32.768 kHz crystals
It operates in low-power mode only and has internal load capacitor banks to tune the
crystal frequency, which can reduce component count.
CLKIN and CLKOUT functions:
•CLKIN input clock – alternate input clock
•CLKOUT output clock:
–Convenient output clock to measure crystal or system frequencies
–Use to tune system and RTC oscillators
5.2 Main crystal oscillator (XTALIN/XTALOUT)
The main crystal oscillator uses the dedicated XTALIN and XTALOUT pins. This high-
frequency oscillator is used to source the PLLs and internal system clocks.
For the PLL multipliers, which limit the practical range of crystal frequencies, see Table 8.
There is a limitation for the PLL crystal oscillator as it has a range from 5 MHz to 26 MHz
crystal, with a PLL multiplier range of 16 through 22, yielding a VCO frequency range of
80 MHz to 572 MHz. This oscillator has a low-power mode that starts up with a normal
gain and automatically adjusts to a lower gain to sustain oscillation. This mode provides
the lowest oscillator power dissipation but can be susceptible to noise if the system is
electrically noisy. The low-power oscillator configuration has its internal feedback resistor,
so an external feedback resistor is not necessary or recommended.
The high gain oscillator is a normal gain amplifier that does not adjust its drive level. The
high gain mode requires an external 1 M ohm feedback resistor. The high gain mode is
less susceptible to system noise but consumes more power.
Each configuration, low-power and high gain, requires external load capacitors on
the crystal pins, see Figure 5. For more details on oscillator load capacitance, refer to
Section 5.9.
This oscillator can be channeled to the CLKOUT output to measure the frequency and
trim the load capacitors as necessary. This oscillator can also be bypassed by driving an
external clock signal into the XTALIN pin.
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XTALOUTXTALIN VSS
crystal
High gain mode
CxCy
R1
Rs
OSC Module
XTALOUTXTALIN VSS
crystal
Low power mode
CxCy
Rs
OSC Module
Figure 5. High gain and low-power modes
PLL frequency (MHz) based on multiplier
Crystal
(MHz)
16 17 18 19 20 21 22
4 64 68 72 76 80 84 88
5 80 85 90 95 100 105 110
8 128 136 144 152 160 168 176
10 160 170 180 190 200 210 220
16 256 272 288 304 320 336 352
20 320 340 360 380 400 420 440
24 384 408 432 456 480 504 528
26 416 442 468 494 520 546 572
32 512 544 576 608 640 672 704
VCO range is from 80 MHz to 572 MHz.
Table 8. PLL frequency
5.3 Main crystal oscillator (XTALIN/XTALOUT), at high gain mode
The high gain mode is the default setting at reset. The oscillator requires software
configuration, so it does not start up at power-up until firmware initializes the oscillator.
The high gain mode requires the 1 M ohm feedback resistor and external load capacitors,
see Figure 6.
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XTALOUTXTALIN VSS
crystal
High gain mode
CxCy
R1
Rs
OSC Module
Figure 6. High gain mode
Note: The series resistor is in the XTALOUT leg. A small value resistance may be used
for low frequency (<8 MHz) crystals, but it is normally not needed.
While the high gain mode is capable of driving lower frequency crystals with rail-to-rail
levels, the levels are attenuated somewhat at higher frequencies. Use high gain mode
when operating in noisy environments. This is more tolerant of noise and reduces system
clock jitter.
However, the high gain mode could also have higher emissions if the oscillator is not
loaded properly. Too little load capacitance can cause higher frequency operation.
5.4 Main crystal oscillator (XTALIN/XTALOUT) at low-power mode
Low-power mode is selected with an enable bit in the oscillator control register. The low-
power configuration has an internal feedback resistor, an external feedback resistor is
not required or recommended. The low-power mode oscillator requires external load
capacitors to tune the crystal oscillator frequency. Low-Power mode is selected by setting
the LP_ENABLE bit in SYSOSCCTL0. Low-Power mode saves energy by reducing the
drive current after initial oscillation:
•Oscillation levels are around 0.8 V peak-to-peak
•Do not attempt to measure the oscillation levels
As mentioned earlier, the low-power mode starts with a normal gain drive and then
reduces the gain automatically to sustain oscillation. The gain control circuit can also
increase gain, if necessary, to sustain oscillation. While the crystal signals can be
measured in low-power mode, attaching a scope probe to either of these pins which alter
the gain characteristics, amplitude, wave shape, and frequency. In general, it is best to
avoid probing the oscillator pins (in any mode) and use the CLKOUT function to tune
the oscillator frequency. The low-power oscillator consumes microampere instead of
milliampere as in high gain mode, so power savings are significant in low-power modes,
see Figure 7.
Note: The series resistor is in the XTALOUT leg, is not recommended for the low-power
oscillator. It is a part of the pierce oscillator circuit convention.
Due to the smaller oscillation waveforms, the low-power configuration becomes more
sensitive to system noise and can produce more jitter due to the reduced amplitude.
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XTALOUTXTALIN VSS
crystal
Low power mode
CxCy
OSC Module
Rs
Figure 7. Low-power mode
5.5 Main crystal oscillator (XTALIN/XTALOUT) bypass mode
The main crystal oscillator can be bypassed with an external oscillator.
It is recommended to:
1. Connect a 1.8 V CMOS-level crystal oscillator (called XO) to the XTALIN input and
float the XTALOUT output.
2. Enable the high gain oscillator by clearing the LP_ENABLE bit in the system oscillator
control register SYSOSCCTL0.
3. Set the BYPASS_ENABLE bit in SYSOSCCTL0 to enable the bypass.
The CLKIN input, available on several GPIO pins, can also bypass the main oscillator, if
desired, without using this bypass mode.
This oscillator’s bypass mode is not compatible with temperature-compensated crystal
oscillators TCXO that have clipped sine-wave outputs. However, a clipped sine-wave
TCXO can be used without the bypass mode when the low-power oscillator is enabled.
1. Connect the TCXO output (800mVp-p minimum) to the XTALIN input and float
XTALOUT.
2. Enable the low-power oscillator by setting the LP_ENABLE bit in the system oscillator
control register, SYSOSCCTL0.
Note: Do not set the BYPASS_ENABLE bit.
The AC coupling capacitor (also called DC-cut capacitor) is TCXOs, generally it is not
needed when the low-power oscillator is used since the oscillator has its internal coupling
capacitor.
5.6 Real-time Clock (RTC) oscillator (RTCXIN/RTCXOUT)
The RTC is a low-power oscillator developed for 32.768 kHz crystals. Its output can be
gated to the system clock. For more details, see Figure 8.
•The RTC oscillator uses the dedicated RTCXIN and RTCXOUT pins.
•The RTC oscillator has an internal feedback resistor. An external feedback resistor is
not required or recommended. RTC oscillator has internal load capacitors to reduce
components. They are selected by firmware.
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•The RTC oscillator frequency can be tuned using the CLKOUT or 32KHZ_CLKOUT
output to measure the frequency.
RTCXOUTRTCXIN
XTAL
CX2 CX1
RTxxx
Figure 8. RTC oscillator
5.7 CLKIN input clock
The CLKIN input is available as a shared function on one of four GPIO pins on the i.MX
RT500, see Figure 9. The system oscillator bypass bits select the main crystal oscillator
or the CLKIN input as the source for the oscillator clock, shown as osc_clk in Figure 9.
CLKIN Port osc_out
clkin
osc_clk
00
01
SYSOSCBYPASS
Selects the main oscillator or
CLKIN as the internal
OSC_CLk input
PIO0_25
PIO2_15
PIO2_30
PIO4_1
Figure 9. osc_clk input
The clock waveform must be a Complementary Metal-Oxide-Semiconductor (CMOS) 1.8
V rail-to-rail square wave. The maximum input frequency is 50 MHz due to pin loading.
Configure CLKIN function using the appropriate FSEL field setting in the GPIO IOPCTL
register. Select CLKIN by setting the SEL field to 0b001 in SYSOSCBYPASS.
The CLKIN function is configured in the GPIO pad control register and selected as the
osc_clk with the system oscillator bypass bits.
5.8 CLKOUT output clock
The CLKOUT output is available as a shared function on one of five GPIO pins on the
i.MX RT500, see Figure 10.
The CLKOUT output can be used as a dedicated clock output to other devices, with a
wide range of source clocks and divisors as highlighted on the left side in Figure 10.
This clock output is very useful during system development to verify the frequency of the
internal system clocks and to tune the crystal oscillators, whether they use internal or
external load capacitors. The output can be disabled for production.
Note: The CLKOUT function is shared on GPIO pins which may have more loading than
dedicated outputs. Therefore, the waveshape may be attenuated or deformed at high
frequencies but is sufficient for external frequency measurements.
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Note: Higher frequency clocks may show wave deformation due to loading and drive
strength. Full drive strength can be enabled to resolve it.
CLKOUT Port
osc_clk
1m_lposc
000
001
FRO_DIV2 010
main_clk 011
dsp_main_clk 100
CLKOUTSEL0
main pll_clk
000
001
aux0 pll_clk 010
dsp pll_clk 011
aux1 pll_clk 100
audio_pll_clk 101
32k_clk 110
CLKOUTSEL1
CLKOUTDIV
CLKOUT
CLKOUT
divider
PIO0_24
PIO1_10
PIO1_19
PIO4_0
PIO2_29
Figure 10. CLKOUT port
5.9 Oscillator load capacitance
Choosing load capacitor values for a crystal oscillator is a topic that can take more time
to discuss and also to understand. First, let us look at what load capacitance is.
The load capacitance (also called CL) of a crystal is different from the load capacitor
values placed on the crystal pins (also called Cx and Cy). The crystal load capacitance is
a crystal parameter used by the vendor to manufacture and test each crystal.
Crystal vendors generally specify a range of CL values in their data sheets as
manufacturing and test conditions. For example, 32.768 kHz crystal data sheet CL values
can range from 9 pF to 12.5 pF. A customer can choose the desired value. It is the
responsibility of the customer to tune the crystal in their circuit. You must know the crystal
CL value in order to begin tuning.
Load capacitors Cx and Cy are placed from the crystal legs to the ground. While it may
look like these caps are in parallel, they are actually in series across the crystal, see
Figure 11.
aaa-046628
XOUTXIN
XTAL
CyCx
RTxxx
Oscillator
Figure 11. Load capacitance
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There are many methods to calculate load capacitance, but none are accurate. At best,
they are approximations.
We recommend using a simple calculation to determine the initial values of the external
load capacitors. Then, after placing these values on the crystal, measure the frequency
with a CLKOUT pin. The load capacitors can be increased if the frequency is higher than
expected or decreased if the frequency is lower than expected.
Definitions:
•CL - load capacitance of the crystal
•Cx, Cy - value of the load capacitors on the crystal pins
•CPin - approximate pad capacitance of each crystal pin
•CStray - stray board capacitance
Load capacitance expression:
1. Cx = Cy ≈ 2CL – CPin – 2CStray
Or
2. Cx = Cy ≈ 2(CL – CStray) – CPin
Note: It is an approximation.
Example 1: Typical 32.768 kHz crystal:
CL = 12.5 pF
CPin = 3 pF
CStray = 0 (ignore for first pass calculation)
Cx = Cy ≈ 2(12.5 pF – 0 pF) – 3 pF = 22 pF
Example 2: Small 32.768 kHz crystal:
CL = 9 pF
CPin = 3 pF
CStray = 0 (ignore for first pass calculation)
Cx = Cy ≈ 2 (9 pF – 0 pF) – 3 pF = 15 pF
Here are the definitions of the symbols used in the model and the simple calculation:
•CL is the load capacitance of the crystal that you received from the vendor.
•Cx and Cy are the physical load capacitors placed on the crystal pins.
•CPin is an approximate pad capacitance of each oscillator terminal, also called the
crystal pin of the MCU.
•CStray is the crystal industry term for the unknown board capacitance.
The load capacitance expression is derived from a standard crystal industry formula,
which involves CL and the unknown CStray parameters.
Note: The derived expression is an approximation. As a matter of fact, the industry
formula and other load capacitance calculations are also approximations, because
there are other dependencies that cannot be defined in simple models.
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Refer to Load capacitance expression 1: Let Cx and Cy be the same value. Multiply the
crystal load capacitance CL by 2, subtract the pad capacitance, and then subtract 2 x
stray capacitance.
The expression can be stated a second way as in Load capacitance expression 2. In the
Example 1, we use a 32.768 kHz crystal with a CL of 12.5 pF, the chip’s pad capacitance
of 3 pF, and ignore the stray capacitance effect for the first pass calculation. We see that
the Cx and Cy load caps should each be about 22 pF. Use this value for the load caps
and measure the frequency. This value is probably high because we disregarded stray
capacitance, so we see the improvement using smaller values. Iterate with capacitors as
necessary to get the frequency tolerance you desire.
Example 2 shows the first pass approximation for a crystal with a 9 pF CL.
The CPin can range from 3 pF to 8 pF or more depending on the chip’s package size.
Smaller packages generally have lower pin capacitance.
The CStray depends on the PCB layout and board parameters. It can be measured
on the PCB, but this does not necessarily mean that the crystal sees the same value
because the measurement is done only from pin to ground and does not include other
dependencies. The crystal industry suggests assigning an arbitrary value of 3 pF to 5 pF
to this parameter.
Given the Cpin range information and CStray arbitrary values, we see that calculating load
capacitor values with absolute accuracy is futile.
NXP recommendation (to approximate the initial load capacitor values and measure
the resulting frequency) eliminates many guesswork and tedious capacitance
measurements. So, calculate the approximate maximum load capacitance values
with this relation, choose the closest standard capacitor values, measure the resulting
CLKOUT frequency, then adjust Cx and Cy equally until the desired frequency accuracy is
attained.
Due to differences and tolerances in the components involved, it is recommended to
characterize multiple board and units (mainly MCUs and crystals) with the chosen Cx
and Cy to get a distribution for the accuracies over a population. The CLKOUT function
makes it easier and more accurate than measuring crystal signals.
Two more examples using different 24 MHz CL values Example 3 and Example 4. In
Example 3, the larger crystals have higher CL values. A typical 24 MHz crystal has a load
capacitance of 18 pF. Example 3 shows that the initial value of the load capacitors should
be 33 pF.
Attach these to the crystal and measure the resulting frequency on the enabled CLKOUT
pin.
•The frequency probably may be lower than 24 MHz.
•Decrease the capacitor values until the desired accuracy is attained.
•A smaller 24 MHz crystal package has a lower CL value.
For more details, see Example 3 and Example 4 for the calculation these crystals.
Example 3: Typical 24 MHz crystal:
CL = 18 pF
CPin = 3 pF
CStray = 0 (ignore for first pass calculation)
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