NXP Semiconductors IMXRT500HDG Guide

IMXRT500HDG
i.MX RT500 Hardware Design Guide
Rev. 0 — 15 November 2022 User guide
Document information
Information Content
Keywords IMXRT500HDG, i.MX RT500, MIMXRT595-EVK
Abstract This user guide provides details about the system hardware design to help
the users to develop their i.MX RT500 based designs

NXP Semiconductors IMXRT500HDG
i.MX RT500 Hardware Design Guide
1 Introduction
This user guide provides details about the system hardware design to help the users to
develop their i.MX RT500 based designs. Recommendations and examples from the
NXP MIMXRT595-EVK board are also included in the following section to illustrate the
concepts.
1.1 MIMXRT595 hardware design guidelines overview
This section provides an overview of MIMXRT595 hardware design guidelines and lists
the detailed description of:
•Power domains: Multiple power domains on the chip and how to filter or decouple them
•External clocks: External system clocks that are available on the chip
•Debug, trace, scan, and programming: Connections review
•Layout recommendations: Requirements for EVK layout
For more details, see Figure 1.
BOOT setting
USB
DNP
FC6_I2S/SD1/FC0_UART
FC8_I2C
MIPI BUS
PDM
SWD/JTAG/UART/I2C
RST USER KEY x2
FlexSPI1
FlexSPI0
SD0
HS SPI
GPIO
FLEX IO
ADCs
I3C0
FC1_I2S
RT595 AB
M.2 Mini
connector
QSPI NOR FLASH
IS25WP064AIBLE
QSPI NOR FLASH
MX25UM51345GXDI
00
PIN-to-PIN OPTION
PSRAM
APS6408L-OBM-BA
PSRAM
APS6408L-OBM-BA
eMMC
MTFC8GAKAJCN
HC SPI
interface
2 pins
Conn
2 pins
Conn
SD slot
MIPI-DSI
FPC conn
FlexlO_l2C
FlexlO_l2C
Pmod
Female Conn
UART I/F
SWD I/F
JTAG I/F
DMIC
Connector
2 x 6 pins
LPC-LINK
Module
Motion Sensor
FXOS8700CQ
FlexIO
2x14 socket
ARDUINO
UNO R3 socket
RGB LED
13C Connector
1x3 pins
MIMXRT595
249-pin eWLB (FOWLP)
7.0 mm x 7.0 mm, 0.4 mm pitch
Mic
8
88
4
4
Codec
WM8904
Left D amplifier
TFA9896UK
Right D amplifier
TFA9896UK
Line Out
Line In
Figure 1. MIMXRT595 block diagram
Key features:
•28FDSOI Technology
•Cortex M33
•Fusion F1 DSP
•Graphics Subsystem
•5 MB Low Leakage SRAM
•Connectivity
•Timers
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i.MX RT500 Hardware Design Guide
Operating characteristics:
•Power supply:
–VDDCORE: 0.6 V to 1.155 V
–VDDIO_0/1/2/4: 1.71 V to 1.89 V
–VDDIO_3: 1.71 V to 3.6 V
•Temperature range (ambient): -20 C° to +70 C°
2 Acronyms and abbreviations
Table 1 defines the acronyms and abbreviations used in this document.
Acronym Definition
BGA Ball Grid Array
CLKIN Clock-In
CMOS Complementary Metal-Oxide-Semiconductor
FOWLP Fan-Out Wafer-Level Package
GPIO General-Purpose Input/Output
HDI High Density Interconnect
ISP In-System Programming
ITM Instrumentation Trace Macrocell
LDO Low-Dropout Regulator
MCU Microcontroller Unit
MLCCs Multi-layer Ceramic Capacitors
OTP One-Time-Programmable
PCB Printed-Circuit board
PFM Pulse-Frequency Mode
PMIC Power Management IC
PWM Pulse Width Modulation
PIU Port Interface Unit
QFN Quad Flat-pack No Lead
QSPI Quad Serial Peripheral Interface
RTC Real-Time Clocks
SDIO Secure Digital I/O
SWD Serial Wire Debug
SWO Serial Wire Output
SWC Serial Wire Clock
WLCSP Wafer-Level Chip-Scale Package
WLCSP Wafer-Level Chip-Scale Package
XTAL Crystal
Table 1. Acronyms and abbreviations
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i.MX RT500 Hardware Design Guide
3 Power domains
This section provides details about the power domains on the chip and in the system.
3.1 i.MX RT500 power domains always-on, GPIO, and analog
The i.MX RT500 has several digital and analog supplies to power internal circuits and
the GPIO ports that interface to the system. Table 2 lists the power rails; minimum,
maximum, and typical voltages for each power rail.
Note: The minimum recommended filtering for each supply, including the bulk storage
and local decoupling capacitors; and a short description of the domain supply.
•VDD_AO1V8 is a low power always-on supply that powers the internal modules and
system registers that keep the chip ready to respond to low-power wake-up events.
These include the real-time clock module, general-purpose registers, the RESETN
input, and PMIC control pins.
•The chip has five separate GPIO power domains that are used to source I/O functions
around the chip. All five I/O power rails operate at 1.8 V, and one (VDDIO_3) can
operate at 3.3 V as well.
•The VDD1V8 power rail supplies on-chip analog functions.
Power rail MIN
(V)
TYP
(V)
MAX
(V)
Decoupling and bulk
capacitors (min qty)
Description
VDD_
AO1V8
1.71 1.8 1.89 1 × 0.22 μF + 1 × 1 μF 1.8 V supply for always-on
features. It includes the RTC
module, general-purpose
GPREG[7:0] registers, and the
RESETN and PMIC control
pins (LDO_ENABLE, PMIC_
IRQ_N, PMIC_MODE0, and
PMIC_MODE1).
VDDIO_0 1.71 1.8 1.89 3 × 0.22 μF + 1 × 10 μF 1.8 V power supply for GPIOs
VDDIO_1 1.71 1.8 1.89 3 × 0.22 μF + 1 × 10 μF 1.8 V power supply for GPIOs
VDDIO_2 1.71 1.8 1.89 1 × 0.22 μF + 1 × 1 μF 1.8 V power supply for GPIOs
1.71 1.8 1.89VDDIO_3
3.0 3.3 3.6
1 × 0.22 μF + 1 × 1 μF 1.8 V or 3.3 V power supply for
GPIOs
VDDIO_4 1.71 1.8 1.89 1 × 0.22 μF + 1 × 1 μF 1.8 V power supply for GPIOs
VDD1V8
VDD1V8_1
1.71 1.8 1.89 5 × 0.22 μF + 1 × 10 μF 1.8 V supply voltage for on-
chip analog functions.
VDD1V8_1 powers the On-
Chip OTP Control module.
Table 2. Power rails
3.2 i.MX RT500 power domains, ADC, and CORE logic supplies
1. The ADC operates at 1.8 V and can only measure up to the VDDA level, see in the
VDDA_ADC1V8 row of Table 3.
2. The VDDCORE is the internal core logic supply that requires a 1.0 V for Power-On and
can be changed in the application.
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The minimum voltage is 0.7 V in active mode to save power, but the level can
be reduced in retention mode. This supply requires quite a bit of decoupling
capacitance. Refer the following steps on how to apply the minimum quantity of
capacitors across the 12 of VDDCORE pins.
•When LDO_ENABLE is externally tied low, the user must boot at VDDCORE = 1.0
V or higher (low-power/normal clock mode - OTP setting - BOOT_CLK_SPEED)
or VDDCORE = 1.13 V (High-Speed clock - OTP setting - BOOT_CLK_SPEED).
Thereafter, the VDDCORE can be adjusted to the desired level.
•When LDO_ENABLE is externally tied high, the on-chip regulator to the VDDCORE
core voltage in PMC is set to the default value of 1.05 V (low-power/normal clock
mode - OTP setting - BOOT_CLK_SPEED) or 1.13 V (high-speed clock - OTP setting
- BOOT_CLK_SPEED). Thereafter, the POWER_SetLdoVoltageForFreq API
function can be used internally to configure the on-chip regulator voltage for the
VDDCORE.
•When performing any OTP read/write function, the VDDCORE voltage must be set to
1.0 V or higher when LDO_ENABLE is externally tied high or low.
3. For the ADC analog reference, VREFP is a 1.8 V reference that must be the same
level as for VDDA_ADC1V8.
Power rail MIN (V) TYP (V) MAX (V) Decoupling and
bulk capacitors
(min qty)
Description
VDDA_ADC1V8 1.71 1.8 1.89 1 × 0.22 μF 1.8 V analog supply
voltage for ADC.
VDDA_BIAS 1.71 1.8 1.89 1 × 0.22 μF + 1
× 1 μF
For ADC and
comparator input range
from 0 – 1.8 V
0.6 1.0 1.155 The minimum voltage
is 0.6 V in retention
mode, and 0.7 V in
active mode.
0.7 1.0 1.155 Power supply for
core logic may be
supplied from the on-
chip regulator or by an
off-chip PMIC.
External filter
capacitors are always
required on these pins.
For details, see the
power connection
information for
values and other
recommendations.
VDDCORE
1.0 1.0 1.155
5 × 0.22 μF + 1
× 10 μF
The minimum voltage
of 1.0 V is required for
initial power on
VREFP 1.71 1.8 1.89 1 × 0.22 μF ADC positive reference
voltage input
Table 3. ADC and CORE logic supplies
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3.3 i.MX RT500 power domains, internal regulator
The LDO_ENABLE input signal is listed in this power domain section because it is the
control signal that enables the internal VDDCORE LDO regulator when an external
VDDCORE supply is not used. This pin is pulled high to enable the internal LDO and tied
low when an external supply provides VDDCORE. Refer to Section 3.6.
Along with the minimum quantities of bulk and decoupling capacitors, we must see Note
on where to place the capacitors and parametric recommendations for the capacitors.
In the high-speed designs, which use ball-grid array packaging, the balls are soldered to
the top layer, the signals are routed on at least two layers, and the power pins are routed
on two or more other layers. The area directly below the MCU on the bottom layer is
where most, if not all, of the decoupling capacitors should be connected to the ground
and power domains.
Capacitor package size, tolerance, rated voltage, and dielectric recommendations are
presented for the three main capacitors used in the decoupling networks, see Table 4.
Capacitor information is presented in the Section 7.
Signal Description
LDO_ENABLE This input enables the on-chip regulator to
power core logic through the VDDCORE pins
when high. Tie low if an off-chip PMIC is used to
supply power to the core logic.
This pin cannot be left floating. A 100 kohm
external pull-up or 10 kohm external pull-down
resistor is recommended.
Table 4. Capacitor information
Note:
1. Decoupling and bulk capacitors must be placed on the bottom side of the PCB,
underneath the MCU for the smallest loops.
•For the 0.22 μF capacitors, use the 0201 packages, 10 V, 20 %, X5R, or X7R
•For the 1 µF capacitors, use the 0402 packages, 10 V, 10 %, X5R, or X7R
•For the 10 µF capacitors, use the 0603 packages, 16 V, 20 %, X5R, or X7R
Note: The 0805 package is acceptable.
3.4 Power domains for GPIO
Table 5 lists the GPIO in the specific VDDIO and VDD_AO1V8 domains.
VDDIO rail GPIO pins
PIO0_0 to PIO0_13
PIO1_11 to PIO1_15
PIO1_18 to PIO1_29
PIO2_14 to PIO2_15
PIO3_25 to PIO3_29
PIO4_0 to PIO4_6
VDDIO_0
PIO6_27
Table 5. Domains
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VDDIO rail GPIO pins
PIO0_14 to PIO0_19
PIO0_21 to PIO0_25
PIO0_28 to PIO0_31
PIO1_0
PIO1_3 to PIO1_7
PIO1_9 to PIO1_10
PIO2_24 to PIO2_31
PIO3_1 to PIO3_3
PIO4_11 to PIO4_17
PIO4_18
PIO5_4, PIO5_8
PIO5_15 to PIO5_18
PMIC_I2C_SCL
VDDIO_1
PMIC_I2C_SDA
PIO1_30 to PIO1_31
PIO2_0 to PIO2_8
VDDIO_2
PIO2_9 to PIO2_11
PIO4_20 to PIO4_31VDDIO_3
PIO5_0 to PIO5_3
PIO3_8 to PIO3_18VDDIO_4
PIO3_19 to PIO3_21
RESETN
LDO_ENABLE
PMIC_IRQ_N
PMIC_MODE0 and PMIC_MODE1
VDD_AO1V8
RTCXIN and RTCXOUT
Table 5. Domains...continued
•VDDIO_0, VDDIO_1, VDDIO_2, and VDDIO_4 supplies can be powered between 1.71
V to 1.89 V.
•VDDIO_3 can be powered between 1.71 V and 3.6 V.
3.5 Power-on sequence using PMIC (internal LDO disabled)
The internal and external power rails must follow a sequence to avoid start-up issues.
These sequences using a PMIC for the VDDCORE node, with the internal CORE LDO
disabled, and external supplies with the internal VDDCORE regulator enabled are similar.
1. The always-on supply must be powered first or in conjunction with the VDD1V8
supplies which power the main digital functions that initialize the MCU.
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2. PMIC mode pins are the outputs that are controlled by an always-on supply. These
pins must have external pullups to VDD_AO1V8 and get validated after several
microseconds once VDD_AO1V8 is stable.
3. The VDDA_ADC1V8 supply and VREFP reference are powered-up at the same time as
VDD1V8 or later.
4. The VDDIO rails and VDDA_BIAS are also powered at the same time as VDD1V8 or
later.
CAUTION: When VDDIO_3 is 3.0 V, there must be a delta of not more than 1.89 V
during the rampup.
5. VDDCORE is powered last by the PMIC, which handles the power sequencing.
Note: When LDO_ENABLE is externally tied low, the user must boot at VDDCORE =
1.0 V or higher (Low-power / Normal clock mode - OTP setting - BOOT_CLK_SPEED)
or VDDCORE = 1.13 V (High-Speed clock - OTP setting - BOOT_CLK_SPEED).
Thereafter, the VDDCORE can be adjusted to the desired level. The PMIC also
provides the RESETN deassertion after VDDCORE is stable.
When a PMIC is not used, enable the internal VDDCORE LDO to provide VDDCORE. The
PMC releases RESETN internally when VDDCORE is stable.
Note: For ERR050716, generally, all 1.8 V power pins are supplied by the same
regulator, so all are applied at the same relative time. Decoupling capacitor charging
delays are not considered to be significant when all the 1.8 V domains are powered at
the same time.
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VDD_AO1V8
1
2
3
4
5
PMIC_MODE0/1
VDD1V8, VVD1V8_1
VDDIO_0, 1, 2, 3, 4
VDDA_BIAS
VDDIO_3(3.3V)
VDDCORE
RESETN
VDDA_ADC1V8, VREFP
ERR050716: VDDIO_x should be
powered at same time as VDD1V8
Figure 2. Power-on sequence
The power-on sequences are shown in the Figure 2 are as follows:
1. VDD_AO1V8, VDD1V8, and VDD1V8_1 should be powered first. If using PMIC, mode
pins are pulled-up to always-on supply until mode pins are active.
2. VDDA_ADC1V8 and VREFP can be powered concurrently with VDD_AO1V8 and
VDD1V8 or later.
3. VDDIO_x and VDDA_BIAS can be powered concurrently with VDD1V8 range or later.
The delta voltage between VDDIO_3 and VDD1V8 must be 1.89 V or less when
VDDIO_3 is 3.3 V.
4. Power-up VDDCORE should not be ramped-up until after all the other supplies have
completed the rampup.
5. Hold RESETN low until VDDCORE is valid when PMIC is used. The only difference
when using internal VDDCORE LDO (LDO_ENABLE = 1) is that internal PMC releases
internal RESETN when VDDCORE is stable.
3.6 NXP PCA9420 PMIC
The NXP PCA9420 PMIC designed to be used with the i.MX RT500 and i.MX RT600
microcontrollers. This PMIC has two LDO regulators and two switch-mode regulators.
This PMIC is available in two small packages:
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•BGA-style wafer level chip scale package WLCSP
•24-pin quad flat pack, no leads QFN
The block diagram shown in Figure 3 has taken from the PCA9420 data sheet.
PCA9420
VIN
ASYS
VBAT
1-cell
Li-Ion
battery
+ (VBAT)
- (GND)
PSYS1
PGND1
LX1
SW1_OUT
PSYS2
PGND2
LX2
2.2 µH
SW2_OUT
VDDCORE
LDO1_OUT
LDO2_OUT
VBAT_BKUP
Always-on
1.8 V
Default
3.3 V
OFF
ON On-Key
button
2.2 µF
10 V
AGND1 AGND2
VBAT
Coin
battery
ON
SCL
SDA
TS
NTC
VDD_ AO1V8
Option
ADC
MODESEL0
MODESEL1
AGND3
SYSRSTn
INTB
R1
R1=R2=100-220 kΩ
R2
PMIC_IRQN
(VDD_AO1V8)
25-Bump WLCSP, 0.4 mm pitch,
2.1 mm x 2.1 mm
ASYS
Default: 1.0 V
Default: 1.8 V VDDIO_1,2,3
and/or 4
Note: A ll dir ectio ns for the arrows in the
schematic are made from t he PCA9420
pe rspective.
Short on PCB
i.MXRT
RT5xx
RT6xx
VDD1V8 and
other 1.8 V power
PMIC_I2C_SCL
(VDDIO_1)
PMIC_I2C_SDA
(VDDIO_1)
VDD_AO1V8
VDDIO_1,2,3,
and/or 4
USB1_VDD3V3
and other
3V.3V power
RESETN
(VDD_AO1V8)
PMIC_MODE0
(VDD_AO1V8)
PMIC_MODE1
(VDD_AO1V8)
Option: can be removed if an
internal pull-up R is available
on i.MXRT* device
VDDIO_1
Input supply
VBUS
GND
C1
C4
D2
E1
D1
B3 C3 E2
C2
D3
D4
E5
D5
B4
B5
A5
C5
B2
A3
A4
A2
B1
A1
If a coil cell is not used, tie
with the VBAT power domain
If the pin is not used,
leave the pin open
If the pin is not used,
leave the pin open
If the pin is not used,
leave the pin open
MODESEL1 MODESEL0
EN_MODE_SEL_BY_PIN_x=1 (x can be 0, 1, 2 or 3)
LOW (0)
HIGH (1)
LOW (0)
LOW (0)
HIGH (1) LOW (0)
HIGH (1) HIGH (1)
Output voltage setting
Mode setting 0
Mode setting 1
Mode setting 2
Mode setting 3
Can be connected to any ADC
* : Regardless of mode setting
1.5 V to 2.1 V or 2.7 V
to 3.3 V
Input current lim it (typica l): 85 mA, 255 mA, 425 mA, 595 mA,
765 mA, 935 mA, 1105 mA or disab le
Regulator Default (V)* Output range
BUCK1 1.0 (MTP)
1.8 (MTP)
1.8 (MTP)
3.3 (MTP)
0.5 V to 1.5 V and fixed
1.8 V
BUCK2
LDO1
LDO2
1.5 V to 2.1 V or 2.7 V
to 3.3 V
1.7 V to 1.9 V
Resolution
25 mV
Max current
250 mA
25 mV
25 mV
25 mV
500 mA
1 mA
250 mA
Linear charger: 0 mA to 315 mA in 5 mA steps for charge current
VIN ≤ 6 V
If VIN is greater than 6 V, the voltage
rating on the capacitor of 2.2 µF/10 V
shall be changed to a higher
voltage than a maximum voltage
in applications.
i.MXRT
RT5xx
RT6xx
E4
E3
0.47 µF
6.3 V
1 µF
6.3 V
2.2 µF
6.3 V
10 µF
6.3 V
2.2 µF
10 V
2.2 µH
10 µF
6.3 V
4.7 µF
10 V
1 µF
10 V
1 µF
10 V
Figure 3. PCA9420 simplified block diagram
•Power Management IC for low-power microcontroller applications
•Two LDO regulators and two switch-mode regulators
•5 x 5 bump WLCSP or 24-pin QFN package −EVK uses the WLCSP package
3.7 MIMXRT595-EVK PMIC supply assignments
Figure 4 focuses on the output portion of the PCA9420 PMIC, as we see the two LDO
outputs on the left and the two switching outputs on the right.
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