NXP Semiconductors QorIQ LS1046A User manual

1 About this document
This document provides recommendations for new designs
based on the LS1046A/LS1026A processor, which is a cost-
effective, power-efficient, and highly integrated system-on-
chip (SoC) design that extends the reach of the NXP Value
Performance line of QorIQ communications processors.
This document can also be used to debug newly-designed
systems by highlighting those aspects of a design that merit
special attention during initial system start-up.
NOTE
This document applies to the LS1046A and
LS1026A devices. For a list of functionality
differences, see the appendices in QorIQ
LS1046A Reference Manual (document
LS1046ARM).
2Before you begin
Ensure you are familiar with the following NXP collateral
before proceeding:
•QorIQ LS1046A, LS1026A Data Sheet (document
LS1046A)
•QorIQ LS1046A Reference Manual (document
LS1046ARM)
NXP Semiconductors Document Number: AN5252
Application Note Rev. 2, 06/2020
QorIQ LS1046A Design Checklist
Contents
1 About this document........................... ...................... 1
2 Before you begin............................... ........................1
3 Simplifying the first phase of design.........................2
4 Power design recommendations.......... ..................... 5
5 Interface recommendations......................................15
6 Thermal................................ ................................... 54
7 Revision history.......................... ............................ 56

3 Simplifying the first phase of design
Before designing a system with the chip, it is recommended that you familiarize yourself with the available documentation,
software, models, and tools.
This figure shows the major functional units within the LS1046A chip.
Watchpoint
Cross
Trigger
Trust Zone
Power Management
IFC, QSPI, SPI
2x DUART
64-bit
DDR4
Memory Controller
Real Time Debug
Perf
Monitor
4x I2C, GPIO
2 MB L2 - Cache
Secure Boot
8x FlexTimer
SATA 3.0
Trace
4-Lane 10 GHz SerDes
SMMUs
3x USB3.0 w/PHY
PCIe 3.0
PCIe 3.0
PCIe 3.0
SD/SDIO/eMMC
DMA
Core Complex
Accelerators and Memory Control
Basic Peripherals, Interconnect, and Debug
Networking Elements
4-Lane 10 GHz SerDes
Queue
Manager
Buffer
Manager
Parse, classify,
distribute
1G
Frame Manager
Security
Engine
(SEC)
DPAA Hardware
1/2.5/10G
1/2.5/10G
1G
32 KB
D-Cache 32 KB
I-Cache
32 KB
D-Cache 32 KB
I-Cache
32 KB
D-Cache 32 KB
I-Cache
32 KB
D-Cache 48 KB
I-Cache
1G
6x LPUART
1G
1/2.5G
CCI-400™ Coherency Fabric
Arm® Cortex®-A72
32-bit/64-bit Core
1G
Figure 1. LS1046A block diagram
This figure shows the major functional units within the LS1026A chip.
Simplifying the first phase of design
QorIQ LS1046A Design Checklist , Rev. 2, 06/2020
2 NXP Semiconductors

Watchpoint
Cross
Trigger
Trust Zone
Power Management
IFC, QSPI, SPI
2x DUART
64-bit
DDR4
Memory Controller
Real Time Debug
Perf
Monitor
4x I2C, GPIO
2 MB L2 - Cache
Secure Boot
8x FlexTimer
SATA 3.0
Trace
4-Lane 10 GHz SerDes
SMMUs
3x USB3.0 w/PHY
PCIe 3.0
PCIe 3.0
PCIe 3.0
SD/SDIO/eMMC
DMA
Core Complex
Accelerators and Memory Control
Basic Peripherals, Interconnect, and Debug
Networking Elements
4-Lane 10 GHz SerDes
Queue
Manager
Buffer
Manager
Parse, classify,
distribute
1G
Frame Manager
Security
Engine
(SEC)
DPAA Hardware
1/2.5/10G
1/2.5/10G
1G
32 KB
D-Cache 32 KB
I-Cache
32 KB
D-Cache 32 KB
I-Cache
32 KB
D-Cache 32 KB
I-Cache
32 KB
D-Cache 48 KB
I-Cache
1G
6x LPUART
1G
1/2.5G
CCI-400™ Coherency Fabric
Arm® Cortex®-A72
32-bit/64-bit Core
1G
Figure 2. LS1026A block diagram
3.1 Recommended resources
This table lists helpful tools, training resources, and documentation, some of which may be available only under a non-
disclosure agreement (NDA). Contact your local field applications engineer or sales representative to obtain a copy.
Table 1. Helpful tools and references
ID Name Location
Related collateral
LS1046ACE LS1046A Chip Errata
NOTE: This document describes the latest fixes and workarounds for the
chip. It is strongly recommended that this document be thoroughly
researched prior to starting a design with the chip.
Contact your NXP
representative
LS1046A QorIQ LS1046A, LS1026A Data Sheet www.nxp.com
LS1046AFS QorIQ LS1046A and LS1026A Communication Processors - Fact Sheet www.nxp.com
LS1046ARM QorIQ LS1046A Reference Manual www.nxp.com
LS1046APB QorIQ LS1046A Product Brief www.nxp.com
AN5125 Introduction to Device Trees - Application note
cortex_a72_
mpcore_trm
_100095_00
02_03_en
ARM® Cortex®-A72 MPCore Processor - Technical Reference Manual Attached with LS1046ARM
Table continues on the next page...
Simplifying the first phase of design
QorIQ LS1046A Design Checklist , Rev. 2, 06/2020
NXP Semiconductors 3

Table 1. Helpful tools and references (continued)
ID Name Location
AN4871 Assembly Handling and Thermal Solutions for Lidless Flip Chip Ball Grid
Array Packages
www.nxp.com
AN5097 Hardware and Layout Design Considerations for DDR4 SDRAM Memory
Interfaces - Application Note
www.nxp.com
AN4311 SerDes Reference Clock Interfacing and HSSI Measurements
Recommendations
www.nxp.com
AN5348 Using QorIQ LS1046ARDB in PCIe Endpoint Mode www.nxp.com
Software tools
CodeWarrior Development Software for ARM® v8 64-bit based QorIQ LS-
Series Processors
www.nxp.com
Software Development Kit for LS1046A www.nxp.com
Hardware tools
CodeWarrior TAP www.nxp.com
QorIQ LS Processor Probe Tips for CodeWarrior TAP www.nxp.com
QorIQ LS1046A reference design board www.nxp.com
Models
IBIS To ensure first path success, NXP strongly recommends using the IBIS
models for board-level simulations, especially for SerDes and DDR
characteristics.
Contact your NXP
representative
BSDL Use the BSDL files in board verification. Contact your NXP
representative
Flotherm Use the Flotherm model for thermal simulation. Especially without forced
cooling or constant airflow, a thermal simulation should not be skipped.
Contact your NXP
representative
Available training
- Our third-party partners are part of an extensive alliance network. More
information can be found at www.NXP.com/alliances.
www.nxp.com/alliances
- Training materials from past Smart Network Developer's Forums and NXP
Technology Forums (FTF) are also available at our website. These training
modules are a valuable resource for understanding the chip.
www.nxp.com/alliances
NOTE
Design requirements in the device datasheet supersede requirements mentioned in design
checklist and design requirements mentioned in design checklist supersede the design/
implementation of the NXP reference design (RDB) system.
3.2 Product revisions
This table lists the system version register (SVR) and ARM core main ID register (TRCIDR1) values for the various chip
silicon derivatives.
Simplifying the first phase of design
QorIQ LS1046A Design Checklist , Rev. 2, 06/2020
4 NXP Semiconductors

Table 2. Chip product revisions
Part Device
revision
ARM®
Cortex®-A72
MPCore
processor
revision
ARM core main ID
register
System version
register value
Note
LS1046A 1.0 r0p2 0x410F_D081h 0x8707_0110h Without security
LS1046AE 1.0 r0p2 0x410F_D081h 0x8707_0010h With security
LS1026A 1.0 r0p2 0x410F_D081h 0x8707_0910h Without security
LS1026AE 1.0 r0p2 0x410F_D081h 0x8707_0810h With security
4 Power design recommendations
4.1 Power pin recommendations
Table 3. Power and ground pin termination checklist
Signal name Used Not used Completed
Power
OVDD General I/O supply
IFC, SPI, GIC (IRQ 0/1/2),
Temper_Detect, System control
and power management,
SYSCLK, DDR_CLK,
DIFF_SYSCLK, GPIO2,
GPIO1, eSDHC[4-7]/VS/
DAT123_DIR/DAT0_DIR/
CMD_DIR/SYNC), Debug,
JTAG, RTC, FTM5/6/7, POR
signals
1.8 V Must remain powered
DVDD DUART, I2C, IRQ[3:10],
USB2/3_PWRFAULT,
USB2/3_DRVVBUS,
EVT_B[5:8], LPUART[1:2],
LPUART4, FTM3_CH[1:7],
FTM4_CH[1:5], FTM8,
eSDHC_CD/WP
1.8 /3.3 V Must remain powered
EVDD eSDHC supply - switchable
eSDHC_DAT[0:3],
eSDHC_CMD, eSDHC_CLK,
FTM4_CH[6:7], LPUART3,
LPUART5, LPUART6
1.8/3.3 V
dynamically
switchable
Must remain powered
LVDD Ethernet Interface 1/2, Ethernet
management interface 1
1.8/2.5 V Must remain powered
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NXP Semiconductors 5

Table 3. Power and ground pin termination checklist (continued)
Signal name Used Not used Completed
(EMI1), TSEC_1588, GPIO1,
GPIO3, FTM1/2, GIC (IRQ11)
TVDD Ethernet management interface
2 (EMI2)
1.2/1.8/2.5 V Must remain powered
G1VDD DDR4 supply 1.2 V Must remain powered
SVDD SerDes core logic and receiver
supply
0.9/1.0 V Must remain powered
XVDD SerDes transmitter supply 1.35 V Must remain powered
PROG_MTR This pin must be connected or pulled down via a resistor to ground (GND).
TA_PROG_SFP SFP fuse programming override
supply
Should only be supplied 1.8 V during secure boot
programming. For normal operation, this pin needs to
be pulled down through a resistor.
TH_VDD Thermal Monitor Unit supply 1.8 V Must remain powered
VDD Supply for cores and platform 0.9/1.0 V Must remain powered
TA_BB_VDD Low power security monitor
supply
0.9/1.0 V Must remain powered
AVDD_CGA1 CPU cluster group A PLL1
supply
1.8 V
(independent
supplies derived
from board 1.8 V)
Must remain powered
AVDD_CGA2 CPU cluster group A PLL2
supply
1.8 V
(independent
supplies derived
from board 1.8 V)
Must remain powered
AVDD_PLAT Platform PLL supply 1.8 V
(independent
supplies derived
from board 1.8 V)
Must remain powered
AVDD_D1 DDR PLL supply 1.8 V
(independent
supplies derived
from board 1.8 V)
Must remain powered
AVDD_SD1_PLL1 SerDes1 PLL 1 supply 1.35 V (filtered off
of XVDD supply)
Must remain powered (no need to
filter from XVDD)
AVDD_SD1_PLL2 SerDes1 PLL 2 supply 1.35 V (filtered off
of XVDD supply)
Must remain powered (no need to
filter from XVDD)
AVDD_SD2_PLL1 SerDes2 PLL 1 supply 1.35 V (filtered off
of XVDD supply)
Must remain powered (no need to
filter from XVDD)
AVDD_SD2_PLL2 SerDes2 PLL 2 supply 1.35 V (filtered off
of XVDD supply)
Must remain powered (no need to
filter from XVDD)
SENSEVDD VDD sense pin Sense pin, Must be connected to regulator feedback
USB_HVDD USB PHY Transceiver supply 3.3 V Tie to GND
USB_SDVDD Analog and Digital HS supply
for USBPHY
0.9/1.0 V Tie to GND
USB_SVDD Analog and Digital SS supply
for USBPHY
0.9/1.0 V Tie to GND
Table continues on the next page...
Power design recommendations
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6 NXP Semiconductors

Table 3. Power and ground pin termination checklist (continued)
Signal name Used Not used Completed
GND Core, platform and PLL ground GND Tie to GND
SD_GND SerDes core logic, transceiver
and PLL ground
GND Tie to GND
SENSEGND Ground sense pin Connect to regulator feedback
NOTE
For supported voltage/frequency/temperature range options, see the orderable part list of
QorIQ LS1046A and LS1026A Multicore Communications Processors at www.nxp.com.
If all USB power supplies are connected to GND when USB is not used, the JTAG IEEE
Std 1149.1-2001 Boundary Scan Register (BSR) will not shift contents between TDI and
TDO. USB_SVDD must be powered in order for the USB BSR cells to shift. In this case,
the USB boundary cells cannot observe or control USB pins. This affects the USB BSR
cells during EXTEST, EXTEST_PULSE, EXTEST_TRAIN, CLAMP and SAMPLE.
The only fails are related to USB IO’s when USB_SVDD is powered on, and
USB_SDVDD and USB_HVDD are powered off. If all USB power supplies are
connected to GND, the other 1149.1 JTAG or DAP debug instructions will still operate.
4.2 Power system-level recommendations
Table 4. Power design system-level checklist
Item Completed
General
Ensure to meet all of the requirements in the data sheet, including power sequencing, power down
requirements, THERMAL and MAXIMUM power dissipation, I/O power dissipation, and power on ramp rate.
Approximately 100mW is consumed per 100MHz of FMAN frequency.
Ensure the PLL filter circuit is applied to AVDD_PLAT, AVDD_CGA1, AVDD_CGA2, AVDD_D1. See the "PLL
power supply filtering" section of this table.
If SerDes is enabled, ensure the PLL filter circuit is applied to the respective AVDD_SDm_PLLnpins.
Otherwise, a filter is not required. Even if an entire SerDes module is not used, the power is still needed to
the AVDD pins. However, instead of using a filter, it needs to be connected to the XVDD rail through a 0 Ω
resistor. See the "PLL power supply filtering" section of this table.
Ensure the PLL filter circuits are placed as close to the respective AVDD_SDm_PLLnpin as possible. If
possible, a small cap for the filter should be placed directly at the pin. If no small cap for the filter is
available, consider at least a standard decoupling cap, such as 0.1 μF.
General Power supply decoupling
Because of large address and data buses and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the system, and the device itself, so this
requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer
place at least one decoupling capacitor at each VDD, TA_BB_VDD, OVDD, TVDD, EVDD, DVDD, LVDD, G1VDD,
SVDD, and XVDD pin of the device. These decoupling capacitors should receive their power from separate
VDD, TA_BB_VDD, OVDD, TVDD, EVDD, DVDD, LVDD, G1VDD, SVDD, XVDD, and GND power planes in the
PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using
a standard escape pattern. Others may surround the part.
Table continues on the next page...
Power design recommendations
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NXP Semiconductors 7

Table 4. Power design system-level checklist (continued)
Item Completed
These capacitors typically should have a value of approximately 0.1 µF. However, larger values available in
the given package, such as 10 µF for 0402 (supports 1.0 mm pitched parts) or 4.7 µF for 0201 (supports 0.8
mm pitched parts), may be used to provide both decoupling and intermediate capacitance for the power
supply design. For example, a system may have 0.1 µF at the pin, but also needs 22 µF intermediate
capacitance outside the package. Given routing escape density, it may be more beneficial to remove the 22
µF caps and replace the 0.1 µF with 4.7 µF to 10 µF 0201/0402. Thus, it allows more room for routing to
escape as an option. It is best to have one decoupling capacitor at each pin location. Only ceramic surface
mount technology (SMT) capacitors should be used to minimize lead inductance, preferably 0402 or 0603
sizes for 1 mm pitched parts and 0201 for 0.8 mm pitched parts.
As presented in the "Core and platform supply voltage filtering" section of this table, it is recommended that
there be several medium and large sized bulk storage capacitors distributed around the PCB, feeding the
VDD and other planes (for example, TVDD, EVDD, DVDD, LVDD, G1VDD, and so on), to enable quick
recharging of the smaller chip capacitors.
Provide sufficiently-sized power planes for the respective power rail. Use separate planes if possible; split
(shared) planes if necessary. If split planes are used, ensure that signals on adjacent layers do not cross
splits. Avoid splitting ground planes at all costs.
Ensure the bulk capacitors have a low ESR rating to ensure the quick response time necessary.
Ensure the bulk capacitors are connected to the power and ground planes through two vias, as necessary,
to minimize inductance.
Ensure you work directly with your power regulator vendor for best values and types of bulk capacitors. The
capacitors need to be selected to work well with the power supply to be able to handle the chip's power
requirements. Most regulators perform best with a mix of ceramic and other low ESR types, such as
OSCON, POS, and other types of capacitor technologies.
Core and platform supply voltage filtering
The VDD supply is normally derived from a high current switching power supply, which can regulate its output
voltage very accurately despite changes in current demand from the chip within the regulator's relatively low
bandwidth. Several bulk capacitors must be distributed around the PCB to supply transient current demand
above the bandwidth of the voltage regulator.
Bulk capacitors should have a low equivalent series resistance (ESR) rating to ensure the necessary
response time. They should also be connected to the power and ground planes through two vias at each
side, if necessary, to minimize inductance. However, customers should work directly with their power
regulator vendor for best values and types of bulk capacitors. Most power supply designs work well with
small ceramic caps at each pin, as discussed in the "General power supply decoupling" section of this table.
But also nearby the SoC should be intermediate caps, such as 22 µF ceramic and larger 330 to 560 µF POS
type caps, as an example. As a guideline for customers and their power regulator vendors, NXP
recommends that these bulk capacitors should be chosen to maintain the positive transient power surges to
less than VDD + 50 mV (negative transient undershoot should comply with specification of VDD - 30 mV) for
current steps of up to 50% to 100% rise and 100% to 50% of max current (based on maximum power in the
data sheet) with a slew rate of 7 A/us. These bulk decoupling capacitors will ideally supply a stable voltage
for current transients into the MHz range. See the "General power supply decoupling" section of this table
for further decoupling recommendations.
PLL supply filtering (core, platform, DDR, filtered from 1.8 V source)
All PLLs are provided with power through independent power supply pins (AVDD_PLAT, AVDD_CGA1/2, and
AVDD_D1 voltages must be derived directly from a 1.8 V voltage source, such as OVDD, through a low
frequency filter. The recommended solution for this type of PLL filtering is to provide independent filter
circuits per PLL power supply, one for each of the AVDD pins. By providing independent filters to each PLL,
the opportunity to cause noise injection from one PLL to the other is reduced. This circuit is intended to filter
noise in the PLL's resonant frequency range from a 500 kHz to 10 MHz range.
Provide independent filter circuits per PLL power supply, as illustrated in the following figure.
Where
Table continues on the next page...
Power design recommendations
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8 NXP Semiconductors

Table 4. Power design system-level checklist (continued)
Item Completed
• R = 5 Ω ± 5%
• C1 = 10 μF ± 10%, 0603 or smaller, X5R or better (X7R or C0G are fine), with ESL ≤ 0.5 nH
• C2 = 1.0 μF ± 10%, 0402 or 0201, X5R, with ESL ≤ 0.5 nH
• Low-ESL surface-mount capacitors
1.8 V source R
C1 C2
Low-ESL surface-mount capacitors
AVDD_PLAT, AVDD_D1
AVDD_CGA1, AVDD_CGA2
Note the following:
• Each AVDD pin must have its own independent filter circuit.
• Voltage for AVDD is defined at the input of the PLL supply filter and not the pin of AVDD.
• If done properly, it is possible to route directly from the capacitors to the AVDD pins, without the added
inductance of vias.
• It is recommended that an area fill or power plane split be provided for a low-impedance profile, which
helps keep nearby crosstalk noise from inducing unwanted noise.
• Place each circuit as close as possible to the specific AVDD pin being supplied to minimize noise
coupled from nearby circuits.
• Placement should be such that the smaller capacitors are nearest to the AVDD pin. If routing permits,
the smallest cap would be best located at the pin of AVDD.
•Caution: These filters are a necessary extension of the PLL circuitry and are compliant with the
device specifications. Any deviation from the recommended filters is done at the user's risk.
PLL supply filtering (SerDes, filtered from XVDD)
The AVDD_SDm_PLLnsignals provide power for the analog portions of the SerDes PLL. To ensure stability
of the internal clock, ensure the power supplied to the PLL is filtered using a circuit similar to the one shown
in the following figure. The recommended solution for PLL filtering is to provide independent filter circuits per
PLL power supply, one for each side of the AVDD pins. By providing independent filters to each PLL, the
opportunity to cause noise injection from one PLL to the other is reduced.
Note the following:
• Each AVDD must have its own independent filter circuit.
• AVDD_SDm_PLLnshould be a filtered version of XVDD.
• Voltage for AVDD is defined at the pin of AVDD. This is in contrast to the requirement, for example for
the core PLL filter such as AVDD_CGAn, which is measured at the input of the filter.
• Placement should be such that the smaller capacitors are nearest to the AVDD pin. If routing permits,
the smallest cap would be best located at the pin of AVDD.
• It is recommended that an area fill or power plane split be provided for a low-impedance profile, which
helps keep nearby crosstalk noise from inducing unwanted noise.
• A 47 µF 0805 XR5 or XR7, 4.7 µF 0603 or smaller, and 0.0033 µF 0402 or 0.0033 µF 0201 capacitor
are recommended. The size and material type are important. A 0.33 Ω ± 1% resistor is recommended.
•Caution: These filters are a necessary extension of the PLL circuitry and are compliant with the
device specifications. Any deviation from the recommended filters is done at the user's risk.
Table continues on the next page...
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NXP Semiconductors 9

Table 4. Power design system-level checklist (continued)
Item Completed
XVDD 0.33 Ω AVDD_SDm_PLLn
47 µF 4.7 µF 0.003 µF
SerDes power supply filtering
The ferrite beads should be placed in parallel to reduce voltage droop. For the linear or low-noise switching
regulator, 10 mVp-p, 50 kHz to 500 MHz is the noise goal. All traces should be kept short, wide, and direct.
Use small area fill, if possible. The goal is to lower the impedance of this net, thus lowering the noise.
SVDD may be supplied by linear or low noise switching regulator or sourced by a filtered VDD.
Two example solutions for SVDD filtering, where SVDD is sourced from VDD, linear or low noise switching
regulator, are illustrated in Figure 3 and Figure 4. Users can choose either one as they see best fit their
needs, but the primary NFM type filter has two advantages: lower DC droop and easier layout than the
ferrite bead solution.
SVDD
2.2 µF
2.2 µF
VDD or linear or
low-noise switching
regulator
Bulk
capacitors Decoupling
capacitors
NFM18PC225B1A3
GRM155R60J225KE95
Figure 3. Primary SVDD power supply filter circuit
2.2 µF 2700 PF
Bulk
capacitors Decoupling
capacitors SVDD
VDD or linear or
low-noise switching
regulator
GRM155R71H272KA01GRM155R60J225KE95
BLM18KG121TN1
Figure 4. Alternate SVDD power supply filter circuit
Note the following:
• See "Power-on ramp rate," in the data sheet for maximum SVDD power-up ramp rate.
• It is recommended that an area fill or power plane split be provided for a low-impedence profile, which
helps keep nearby crosstalk noise from inducing unwanted noise.
• Place each circuit as close as possible to the specific set of pins being supplied to minimize noise
coupled from nearby circuits.
• Located at each pin should have a decouple capacitor, such as 0.1 µF.
XVDD may be supplied by a linear or low noise switching regulator.
Two example solutions for XVDD filtering, where XVDD is sourced from a linear or low noise switching
regulator, are illustrated in Figure 5 and Figure 6. Users can choose either one as they see best fit their
needs, but the primary NFM type filter has two advantages: lower DC droop and easier layout than the
ferrite bead solution
Table continues on the next page...
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Table 4. Power design system-level checklist (continued)
Item Completed
XVDD
2.2 µF
2.2 µF
linear or
low-noise switching
regulator
Bulk
capacitors Decoupling
capacitors
NFM18PC225B1A3
GRM155R60J225KE95
Figure 5. Primary XVDD power supply filter circuit
2.2 µF 2700 PF
Bulk
capacitors Decoupling
capacitors XVDD
linear or
low-noise switching
regulator
GRM155R71H272KA01GRM155R60J225KE95
BLM18KG121TN1
Figure 6. Alternte XVDD power supply filter circuit
Note the following:
• See "Power-on ramp rate," in the data sheet for maximum XVDD power-up ramp rate.
• It is recommended that an area fill or power plane split be provided for a low-impedance profile, which
helps keep nearby crosstalk noise from inducing unwanted noise.
• Place each circuit as close as possible to the specific set of pins being supplied to minimize noise
coupled from nearby circuits.
• Located at each pin should have a decouple capacitor, such as 0.1 µF.
USB_HVDD may be supplied by a linear or low noise switching regulator, which may be the system-wide 3.3
V power supply.
Two example solutions for USB_HVDD filtering, where USB_HVDD is sourced from a linear or low noise
switching regulator, are illustrated in Figure 7 and Figure 8. Users can choose either one as they see best fit
their needs, but the primary NFM type filter has two advantages: lower DC droop and easier layout than the
ferrite bead solution.
USB_HVDD
2.2 µF
2.2 µF
3.3 V Bulk
capacitors Decoupling
capacitors
NFM18PC225B1A3
GRM155R60J225KE95
Figure 7. Primary USB_HVDD power supply filter circuit
2.2 µF 2700 PF
Bulk
capacitors Decoupling
capacitors USB_HVDD
3.3 V
GRM155R71H272KA01GRM155R60J225KE95
BLM18KG121TN1
Figure 8. Alternate USB_HVDD power supply filter circuit
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Table 4. Power design system-level checklist (continued)
Item Completed
Note the following:
• It is recommended that an area fill or power plane split be provided for a low-impedence profile, which
helps keep nearby crosstalk noise from inducing unwanted noise.
• Place each circuit as close as possible to the specific set of pins being supplied to minimize noise
coupled from nearby circuits.
• Located at each pin should have a decouple capacitor, such as 0.1 µF.
USB_SVDD and USB_SDVDD are to be filtered from the VDD power supply.
Two example solutions for USB_SVDD and USB_SDVDD filtering, where USB_SVDD and USB_SDVDD are
sourced from a filtered version of VDD, are illustrated in Figure 9, Figure 10, Figure 11 and Figure 12. Users
can choose either one as they see best fit their needs, but the primary NFM type filter has two advantages:
lower DC droop and easier layout than the ferrite bead solution.
2.2 µF
2.2 µF
VDD Bulk
capacitors Decoupling
capacitors
NFM18PC225B1A3
GRM155R60J225KE95
USB_SVDD
Figure 9. Primary USB_SVDD power supply filter circuit
2.2 µF 2700 PF
Bulk
capacitors Decoupling
capacitors USB_SVDD
VDD
GRM155R71H272KA01GRM155R60J225KE95
BLM18KG121TN1
Figure 10. Alternate USB_SVDD power supply filter circuit
2.2 µF
2.2 µF
VDD Bulk
capacitors Decoupling
capacitors
NFM18PC225B1A3
GRM155R60J225KE95
USB_SDVDD
Figure 11. Primary USB_SDVDD power supply filter circuit
2.2 µF 2700 PF
Bulk
capacitors Decoupling
capacitors USB_SDVDD
VDD
GRM155R71H272KA01GRM155R60J225KE95
BLM18KG121TN1
Figure 12. Alternate USB_SDVDD power supply filter circuit
Note the following:
Power design recommendations
QorIQ LS1046A Design Checklist , Rev. 2, 06/2020
12 NXP Semiconductors

Table 4. Power design system-level checklist
Item Completed
• It is recommended that an area fill or power plane split be provided for a low-impedence profile, which
helps keep nearby crosstalk noise from inducing unwanted noise.
• Place each circuit as close as possible to the specific set of pins being supplied to minimize noise
coupled from nearby circuits.
• Located at each pin should have a decouple capacitor, such as 0.1 µF.
4.3 Power-on and Reset recommendations
Various chip functions are initialized by sampling certain signals during the assertion of PORESET_B. These power-on reset
(POR) inputs are pulled either high or low during this period. While these pins are generally output pins during normal
operation, they are treated as inputs while PORESET_B is asserted. When PORESET_B de-asserts, the configuration pins
are sampled and latched into registers, and the pins then take on their normal output circuit characteristics.
Table 5. Reset system-level checklist
Item Completed
Ensure PORESET_B is asserted for a minimum of 1 ms after VDD ramps up.
Ensure HRESET_B is asserted for a minimum of 32 SYSCLK cycles.
In cases where a configuration pin has no default, use a 4.7 kΩ pull-up or pull-down resistor for appropriate
configuration of the pin.
Optional: An alternative to using pull-up and pull-down resistors to configure the POR pins is to use a PLD or
similar device that drives the configuration signals to the chip when PORESET_B is asserted. The PLD must
begin to drive these signals at least four SYSCLK cycles prior to the de-assertion of PORESET_B (other
than cfg_eng_use0), hold their values for at least two SYSCLK cycles after the de-assertion of
PORESET_B, and then release the pins to high impedance afterward for normal device operation
NOTE: See the applicable chip data sheet for details about reset initialization timing specifications.
Configuration settings
Ensure the settings in Configuration signals sampled at reset are selected properly.
NOTE: See the applicable chip reference manual for a more detailed description of each configuration
option.
Power sequencing
The chip requires that its power rails be applied in a specific sequence in order to ensure proper device
operation. For details, see QorIQ LS1046A, LS1026A Data Sheet" (document LS1046A).
4.3.1 Configuration signals sampled at reset
The signals that serve alternate functions as configuration input signals during system reset are summarized in this table.
Reset configuration signals are sampled at the negation of PORESET_B. However, there is a setup and hold time for these
signals relative to the rising edge of PORESET_B, as described in the QorlQ LS1046A Data Sheet (document LS1046A).
Power design recommendations
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NXP Semiconductors 13

The reset configuration signals are multiplexed with other functional signals. The values on these signals during reset are
interpreted to be logic one or zero, regardless of whether the functional signal name is defined as active-low. The reset
configuration signals have internal pull-up resistors so that if the signals are not driven, the default value is high (a one), as
shown in the table below. Some signals must be driven high or low during the reset period. For details about all the signals
that require external pull-up resistors, see the applicable device data sheet.
Table 6. LS1046A reset configuration signals
Configuration Type Functional Pins Comments
Reset configuration word (RCW) source
inputs cfg_rcw_src[0:8]
IFC_AD[8:15]
IFC_CLE
They must be set to one of the valid RCW
source input option. The 512-bit RCW
word has all the necessary configuration
information for the chip. If there is no valid
RCW in the external memory, it can be
programmed using the Code Warrior or
other programmer. The JTAG configuration
files (path: CWInstallDir
\CW4NET_v2019.01\CW_ARMv8\Config
\boards) can be used in the following
situations:
• target boards that do not have RCW
already programmed
• new board bring up
• recovering boards with blank or
damaged flash
IFC external transceiver enable polarity
select (cfg_ifc_te)
IFC_TE Default is "1"
DRAM type select (cfg_dram_type) IFC_A[21] The reset configuration pin selects the
proper IO voltage.
• 1=Reserved
• 0=DDR4 (1.2 V)
Ensure the selected value matches DDR4
General-purpose input (cfg_gpinput[0:7]) IFC_AD[0:7] Default "1111 1111", values can be
application defined
"Single Oscillator Source" clock select.
This field selects between SYSCLK
(Single ended) and DIFF_SYSCLK/
DIFF_SYSCLK_B (differential) inputs.
(cfg_eng_use0)
IFC_WE0_B 0=DIFF_SYSCLK/
DIFF_SYSCLK_B(differential)
1=SYSCLK (single ended)
Default selection is single ended SYSCLK;
"1"
"Single Oscillator Source" clock.
This field indicates whether on-chip
LVDS termination for differential clock is
enabled or disabled.
configuration (cfg_eng_use1)
IFC_OE_B 0 = Disabled (MUST make sure that
External termination pads of
DIFF_SYSCLK/DIFF_SYSCLK_B have
proper termination)
1 = Enabled (default)
Default is "1".
It is recommened to keep provision for
optional pull-down resistor on board.
"Single Oscillator Source" clock
configuration (cfg_eng_use2)
IFC_WP0_B Default is "1". Reserved.
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14 NXP Semiconductors

4.3.2 Hard-coded RCW
The hard-coded RCW can be used as an alternative method for the initial board bring-up when there is no valid RCW in the
external memory.
If a new board is using a blank flash and flash is the source of RCW, then all 0xff value from flash for RCW will put the
device in an unknown state.
There are two methods to workaround this problem:
1. Put the switches on cfg_rcw_src signals to select hard-coded RCW (0x9F, 0x9E).
2. Use the CodeWarrior tool from NXP to override RCW.
NOTE
• It is recommended to disconnect RESET_REQ_B from PORESET_B when using
hard-coded RCW as any different board configuration may push the chip to an
endless reset loop. For more information, see the hard-coded RCW options listed in
QorIQ LS1046A Reference Manual (document LS1046ARM).
• Use 0x9F for hard coded RCW when using DIFF_SYSCLK/DIFF_SYSCLK_B as
the primary clock input to LS1046A.
• For bringing-up a new board when no valid RCW or bootloader is available and
onboard flash is not supported in CodeWarrior then refer to AN12081.
5Interface recommendations
This section details the pin termination guidelines for different interfaces. In general, any unused input pin should be
terminated by a pull down unless recommended otherwise.
5.1 DDR controller recommendations
The memory interface controls main memory accesses. The LS1046A/LS1026A device supports 32-bit/64-bit (1.2 V) DDR4
SDRAM with ECC.
5.1.1 DDR SDRAM memory interface pin termination
recommendations
Table 7. DDR SDRAM memory interface pin termination checklist
Signal name IO type Used Not used Completed
D1_MALERT_B I Recommend that a weak pull-up
resistor (2-10 kΩ) for SDRAM
DDR4 or strong pull-up resistor
(50-100 Ω) for discrete/RDIMM
SDRAM DDR4, be placed on this
pin to the respective power supply.
Pull up whether used or not used.
Table continues on the next page...
Interface recommendations
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NXP Semiconductors 15

Table 7. DDR SDRAM memory interface pin termination checklist (continued)
Signal name IO type Used Not used Completed
D1_MPAR O MPAR from memory controller
should be connected to the PAR
signal at DRAM
May be left unconnected.
D1_MACT_B O Must be properly terminated to
VTT.
May be left unconnected.
D1_MA[0:13] O Must be properly terminated to
VTT.
May be left unconnected.
D1_MBA[0:1] O Must be properly terminated to
VTT.
May be left unconnected.
D1_MBG[0:1] O Must be properly terminated to
VTT.
May be left unconnected.
D1_MCAS_B2O Must be properly terminated to
VTT.
May be left unconnected.
D1_MCKE[0:1] O Must be properly terminated to
VTT.
This output is actively driven
during reset rather than being tri-
stated during reset.
May be left unconnected.
D1_MCK[0:1] O Ensure these pins are terminated
correctly.
May be left unconnected. Unused
MCK pins can be disabled using
DDRCLKDR register.
D1_MCK_B[0:1] O Ensure these pins are terminated
correctly.
May be left unconnected.
D1_MCS[0:3]_B2O Must be properly terminated to
VTT.
May be left unconnected.
D1_MDIC[0:1] IO • These pins are used for
automatic calibration of the
DDR4 IOs.
• MDIC[0] is grounded
through a 162 Ω precision
1% resistor and MDIC[1] is
connected to G1VDD
through a 162 Ω precision
1% resistor.
• For either full or half drive
strength calibration of DDR
IOs, use the same MDIC
resistor value of 162 Ω.
• The memory controller
register setting can be used
to determine if automatic
calibration is done to full or
half drive strength.
May be left unconnected.
D1_MDM[0:8] O — May be left unconnected.
D1_MDQS[0:8]_B IO — May be left unconnected.
D1_MDQS[0:8] IO — May be left unconnected.
D1_MDQ[0:63] IO — May be left unconnected.
D1_MECC[0:7] IO — May be left unconnected.
Table continues on the next page...
Interface recommendations
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16 NXP Semiconductors

Table 7. DDR SDRAM memory interface pin termination checklist (continued)
Signal name IO type Used Not used Completed
D1_MODT[0:1] O Ensure the MODT signals are
connected correctly. In general, for
dual-ranked DIMMS, the following
should all go to the same physical
memory bank:
• MODT(0), MCS(0), MCKE(0)
• MODT(1), MCS(1), MCKE(1)
For quad-ranked DIMMS, it is
recommended to obtain a data
sheet from the memory supplier to
confirm required signals. But in
general, each controller needs
MCS(0:3), MODT(0:1), and
MCKE(0:1) connected to the one
quad-ranked DIMM.
May be left unconnected.
D1_MRAS_B2O Must be properly terminated to
VTT.
May be left unconnected.
D1_MWE_B2O Must be properly terminated to
VTT.
May be left unconnected.
NOTE
1. For DDR4 bit and byte swapping rules and layout guidelines, see the application
note Hardware and Layout Design Considerations for DDR4 SDRAM Memory
Interfaces (document AN5097).
2. When using RDIMM, the CS, RAS, CAS, WE signals may need series termination
to prevent an excessive overshoot
3. When DDR4 Discrete or RDIMM DRAM is soldered on the board and two chip
selects are used, and the second chip select is bit swizzling (meaning bits mapping
from CS0 is additionally swapped in CS1 by swapping DQ0 with DQ1, DQ2 with
DQ3, DQ4 with DQ5, and DQ6 with DQ7), then bit map orders of 0x10 (2 1 3 0)
and 0x30 (6 5 7 4) are not allowed.
5.1.2 DDR system-level recommendations
Table 8. DDR system-level checklist
Item Completed
General
Data Bus inversion (DBI) signals are muxed on Data Mask (D1_MDM) signals and are optional function for
DDR4. Only one function can be used at a time.
HRESET can be used to reset unbuffered DIMM (UDIMM, SoDIMM) or discrete DRAM. For Registered
DIMM, refer AN5097
CKE termination requirment during self refresh -- In order to keep DRAM memory in a self-refresh mode, the
CKE signal must be driven low. For applications requiring LS1046A to be powered off and SDRAM memory
in self refresh, the CKE signal must be driven/pulled low during power ramp up, external to the SoC by
hardware on the board. Refer AN4531
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NXP Semiconductors 17

NOTE
Stacked memory for DDR4 are not supported.
5.2 IFC recommendations
The integrated Flash controller shares signals with QSPI flash and Flex Timer Module. The functionality of these signals is
determined by the IFC_GRP_[a]_BASE fields in the reset configuration word The LS1046A Integrated Flash Controller
(IFC), supports upto 28-bit addressing and 8- or 16-bit data widths, for a variety of devices
5.2.1 IFC pin termination recommendations
Table 9. IFC pin termination checklist
Signal name I/O type Used Not used Completed
IFC_A[16:20] O These pins must not be pulled down during power-on reset. It may be pulled
up, driven high, or if there are no externally connected devices, left in tristate.
If these pins are connected to a device that pulls down during reset, an
external pull-up is required to drive these pins to a safe state during reset.
IFC_A[21] O This pin is a reset configuration pin. It has a weak (~20 kΩ ) internal pull-up P-
FET that is enabled only when the processor is in its reset state. The pull-up
is designed such that it can be overpowered by an external 4.7 kΩ resistor.
However, if the signal is intended to be high after reset, and if there is any
device on the net that might pull down the value of the net at reset, a pull-up
or active driver is needed.
IFC_A[22:27] I/O Connect as
needed.
These pins can be left unconnected.
IFC_AD[0:15] I/O These pins are reset configuration pins. They have a weak (~20 kΩ ) internal
pull-up P-FET that is enabled only when the processor is in its reset state.
These pull-ups are designed such that it can be overpowered by an external
4.7 kΩ resistor. However, if the signal is intended to be high after reset, and if
there is any device on the net that might pull down the value of the net at
reset, a pull-up or active driver is needed.
IFC_PAR[0:1] I/O Connect as
needed.
These pins can be left unconnected.
IFC_CS[0]_B O Recommend
weak pull-up
resistors (2–10
kΩ) be placed
on these pins
to OVDD.
This pin can be left unconnected.
IFC_CS[1:3]_B O Recommend
weak pull-up
resistors (2–10
kΩ) be placed
on these pins
to OVDD.
These pins can be left unconnected.
IFC_WE[0]_B O These pins are reset configuration pins, they have a weak (~20 kΩ ) internal
pull-up P-FET that is enabled only when the processor is in its reset state.
The internal pull-ups are designed such that it can be overpowered by an
external 4.7 kΩ resistor. However, It is recommended to keep a provision for
optional pull-up and pull-down resistor on board.
IFC_OE_B O
IFC_WP[0]_B O
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18 NXP Semiconductors

Table 9. IFC pin termination checklist (continued)
Signal name I/O type Used Not used Completed
IFC_PERR_B I Connect as
needed.
This pin should be pulled high through a 2-10 kΩ resistor to
OVDD or can be left floating if configured as output via the
GPIO_GPDIR register.
IFC_BCTL O Connect as
needed.
This pin can be left unconnected.
IFC_TE O This pin is a reset configuration pin. It has a weak (~20 kΩ) internal pull-up P-
FET that is enabled only when the processor is in its reset state. This pull-up
is designed such that it can be overpowered by an external 4.7 kΩ resistor.
However, if the signal is intended to be high after reset, and if there is any
device on the net that might pull down the value of the net at reset, a pull-up
or active driver is needed.
IFC_NDDQS I/O Connect as
needed.
This pin can be left unconnected.
IFC_AVD O This pin must not be pulled down during power-on reset. It may be pulled up,
driven high, or if there are no externally connected devices, left in tristate. If
this pin is connected to a device that pulls down during reset, an external pull-
up is required to drive this pin to a safe state during reset.
IFC_CLE O This pin is a reset configuration pin. It has a weak (~20 kΩ) internal pull-up P-
FET that is enabled only when the processor is in its reset state. This pull-up
is designed such that it can be overpowered by an external 4.7 kΩ resistor.
However, if the signal is intended to be high after reset, and if there is any
device on the net that might pull down the value of the net at reset, a pull-up
or active driver is needed.
IFC_RB[0:1]_B I These pins
should be
pulled high
through a 1 kΩ
resistor to
OVDD.
These pins should be pulled high through a 1 kΩ resistor.
IFC_CLK[0:1] O Connect as
needed.
This pin can be left unconnected.
IFC_NDDDR_CLK O Connect as
needed
This pin can be left unconnected.
NOTE
The IFC interface is on OVDD power domain which is 1.8 V only.
For functional connection diagram, see the chip reference manual.
5.3 DUART pin termination recommendations
Table 10. DUART pin termination checklist
Signal name I/O type Used Not used Completed
UART1_SOUT O The functionality of these pins is
determined by the UART_BASE and
UART_EXT fields in the reset
These pins can be left unconnected.
UART1_RTS_B O
Table continues on the next page...
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NXP Semiconductors 19

Table 10. DUART pin termination checklist (continued)
Signal name I/O type Used Not used Completed
UART1_SIN I configuration word
(RCW[UART_BASE],
RCW[UART_EXT]).
These pins should be pulled high
through a 2-10 kΩ resistor to DVDD or
else programmed as GPIO and output.
UART1_CTS_B I
UART2_SOUT O These pins can be left unconnected.
UART2_RTS_B O
UART2_SIN I These pins should be pulled high
through a 2-10 kΩ resistor to DVDD or
else programmed as GPIO and output.
UART2_CTS_B I
UART3_SOUT O This pin can be left unconnected.
UART3_SIN I This pin should be pulled high through a
2-10 kΩ resistor to DVDD or else
programmed as GPIO and output.
UART4_SOUT O This pin can be left unconnected.
UART4_SIN I This pin should be pulled high through a
2-10 kΩ resistor to DVDD or else
programmed as GPIO and output.
5.4 LPUART pin termination recommendations
Table 11. LPUART pin termination checklist
Signal Name IO type Used Not Used Completed
LPUART1_CTS_B I The functionality of
LPUART1_CTS_B is determined
by the UART_EXT field in the
reset configuration word.
These pins should be pulled high
through a 2-10 kΩ resistor to
DVDD or else programmed as
GPIO and output.
LPUART[2:3]_CTS_B I The functionality of
LPUART[2:3]_CTS_B is
determined by the SDHC_EXT
field in the reset configuration
word.
These pins should be pulled high
through a 2-10 kΩ resistor to
EVDD or else programmed as
GPIOs and outputs.
LPUART1_RTS_B O The functionality of
LPUART1_RTS_B is determined
by the UART_EXT field in the
reset configuration word
RCW[UART_EXT].
Can be left floating or else
program as GPIO and output.
LPUART[2:3]_RTS_B O The functionality of
LPUART[1:3]_RTS_B is
determined by the SDHC_EXT
field in the reset configuration
word (RCW[SDHC_EXT]).
Can be left floating or else
programmed as GPIOs and
outputs.
LPUART[1:2]_SIN,
LPUART4_SIN
I The functionality of
LPUART[1:2]_SIN and
LPUART[4]_SIN is determined by
These pins should be pulled high
through a 2-10 kΩ resistor to DVDD
or else programmed as GPIOs
and outputs.
Table continues on the next page...
Interface recommendations
QorIQ LS1046A Design Checklist , Rev. 2, 06/2020
20 NXP Semiconductors