NXP Semiconductors KITFS23LDOEVM User manual

UM11879
KITFS23LDOEVM evaluation board
Rev. 2 — 25 September 2023 User manual
Document information
Information Content
Keywords FS2300, S32K144, FS2300 NXP GUI, SBC, Body and Comfort, ISO 26262
Abstract The KITFS23LDOEVM evaluation board user guide is intended for engineers involved in the
evaluation, design, implementation, and validation of FS2300 fail-safe system basis chips.

NXP Semiconductors UM11879
KITFS23LDOEVM evaluation board
Rev Date Description
v.2 20230925 •Replaced all occurences of "User mode" with "Normal mode"
•Section 1; Section 6.1; Section 6.3.2; Section 6.5.2.1.5; Section 6.5.3.2;
Section 6.5.4.1; Section 6.5.4.2; Section 6.5.6.2; Section 6.5.6.5; Section 6.5.1;
Section 7.3.2.3; Section 7.3.3.2.1: Updated text
•Updated Figure 2; Figure 3; Figure 4; Figure 10; Figure 11; Figure 21; Figure 30;
Figure 31; Figure 32; Figure 33; Figure 34; Figure 35; Figure 36; Figure 38;
Figure 39; Figure 40; Figure 41; Figure 42; Figure 43; Figure 44; Figure 45;
Figure 47; Figure 48; Figure 52; Figure 59; Figure 60; Figure 66; Figure 78;
Figure 79; Figure 80; Figure 81; Figure 83; Figure 84; Figure 85; Figure 86;
Figure 88; Figure 90
•Section 2.1; Section 3.4; Section 4.4.14: Updated link to https://www.nxp.com/
KITFS23LDOEVM
•Section 4.4: Updated Table 1; Table 2: Removed J33 row
•Section 4.4.5
–Removed "J33" from section title, updated text
–Updated Table 7
– Removed "J33" from table title
– Removed "J33-1-2" and J33 (OFF) rows
– Updated Description of "J35-1"
•Removed section titled "FS0B pullup configuration (R13/R12/C26)"
•Updated Table 12
•Section 4.4.11.2: Updated last sentence of first paragraph; replaced former figures 8,
9 , 10 with tables containing same data.
•Section 4.4.12: Updated Signals and Power supply bullet items
•Section 6.3: Updated text; Added Protocol selection bullet item
•Section 6.5: Reordered sub-sections, updated Power description
•Section 6.5.3.3: Updated text, removed figure titled "Fuse box status for an empty
part"
•Section 6.5.7: Updated "MCU Input Pins Reading window" and "MCU Output Pins
Setting window"
•Section 6.5.8, Section 6.5.9: Added note
•Section 7.3: Updated text, added Table 17
•Section 7.5: Updated set up steps
•Section 7.7.2: Changed "Import from CFG" to "Load CFG" in step 2, changed "Export
from CFG" to "Save CFG" in step 4
•Section 7.8: Updated text; updated "Programming procedure"; removed figures titled
"Programming an SPI part", "Programming a part using PROG tool", and "Loading a
TBB file to burn a part"; added Figure 92
v.1 20230223 Initial version
Revision history
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IMPORTANT NOTICE
For engineering development or evaluation purposes only
NXP provides the product under the following conditions:
This evaluation kit is for use of ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES
ONLY. It is provided as a sample IC pre-soldered to a printed-circuit board to make it easier to access
inputs, outputs and supply terminals. This evaluation board may be used with any development
system or other source of I/O signals by connecting it to the host MCU computer board via off-the-
shelf cables. This evaluation board is not a Reference Design and is not intended to represent a final
design recommendation for any particular application. Final device in an application heavily depends
on proper printed-circuit board layout and heat sinking design as well as attention to supply filtering,
transient suppression, and I/O signal quality.
The product provided may not be complete in terms of required design, marketing, and or
manufacturing related protective considerations, including product safety measures typically found
in the end device incorporating the product. Due to the open construction of the product, it is the
responsibility of the user to take all appropriate precautions for electric discharge. In order to minimize
risks associated with the customers’ applications, adequate design and operating safeguards must be
provided by the customer to minimize inherent or procedural hazards. For any safety concerns, contact
NXP sales and technical support services.
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1 Introduction
The KITFS23LDOEVM board user manual is intended for engineers involved in the evaluation, design,
implementation, and validation of the FS2300 Body and Comfort system basis chip (SBC).
The KITFS23LDOEVM board is a soldered board supporting the FS2300 fail-safe SBC with three low dropout
(LDO) regulators.
The KITFS23LDOEVM enables development on the FS2300 Body and Comfort SBC family of devices. This
document covers connecting the hardware, installing the NXP GUI software, configuring the environment, and
using the kit. It includes guidance on how to use the registers, try OTP configurations, and burn the part.
The board as delivered includes a soldered FS2320 device with empty OTP content in order to leave the
opportunity to the user to burn the OTP configuration.
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2 Finding kit resources and information on the NXP website
NXP Semiconductors provides online resources for this evaluation board and its supported device(s) on http://
www.nxp.com.
The information page for KITFS23LDOEVM board is at https://www.nxp.com/KITFS23LDOEVM. The
information page provides overview information, documentation, software and tools, parametrics, ordering
information.
2.1 Collaborate in the NXP community
The NXP community is for sharing ideas and tips, asking and answering technical questions, and receiving
input on just about any embedded design topic.
The NXP community is at http://community.nxp.com.
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3 Getting ready
Working with the KITFS23LDOEVM requires the kit contents, additional hardware, and a Windows PC
workstation with installed software.
3.1 Kit contents
The KITFS23LDOEVM kit contains the following items:
•Assembled and tested evaluation board with preprogrammed S32K144 microcontroller in an anti-static bag
•3.0 ft USB-STD A to USB-B-micro cable
•Six connectors, terminal block plug, two positions, straight, 3.81 mm
•Three connectors, terminal block plug, three positions, straight, 3.81 mm
•Jumpers mounted on board
3.2 Additional hardware
In addition to the kit contents, the following hardware is necessary or beneficial when working with this kit.
•One power supply with a range up to 40 V.
3.3 Minimum system requirements
This evaluation board requires a Windows PC workstation.
•USB-enabled computer with Windows 7 or Windows 10
•FTDI USB serial port driver (for FT230X Basic UART device)
3.4 Software
Installing software is necessary to work with the KITFS23LDOEVM evaluation board.
All listed software is available on the evaluation board's information page at https://www.nxp.com/
KITFS23LDOEVM.
•NXP GUI for automotive SBC family installation package - latest version
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4 Getting to know the hardware
The KITFS23LDOEVM kit provides an integrated platform for evaluating designs based on NXP’s FS2300 SBC.
All FS2300 features can be accessed and monitored in a test environment using NXP GUI software to access
the registers in Read and Write mode. All regulators are accessible through connectors. Nonuser signals are
mapped on test points. Digital signals (I2C, RSTB, etc.) are accessible through connectors.
4.1 Kit overview
The kit's hardware consists of the KITFS23LDOEVM evaluation board embedded with an S32K144
microcontroller, and the USB cable required to connect the board to the PC.
The KITFS23LDOEVM evaluation board features a soldered FS2300 part and allows the user to fuse the
device’s one time programmable (OTP) feature without extra tools. Connectors, jumpers, and switches on the
board can be used to configure an evaluation environment that meets specific design requirements. The board
also contains LEDs and test points that provide a means of monitoring performance in real time. An emulation
mode allows the user to test as many configurations as needed before programming the part.
The S32K144 is soldered on the bottom side of the KITFS23LDOEVM board. The role of the S32K144 is to
manage SPI or I2C communication (depending on the user’s choice) between the KITFS23LDOEVM board and
the GUI installed on the PC. The S32K144 draws power either from the USB cable connected to the PC or from
the battery supply (when not connected to the GUI).
aaa-049440
FS23
V1
VBAT
IOs
Safety IOs
CAN RX/TX
LIN RX/TX
I2C (default)/SPI
V2
V3
CAN
LIN
5.0 V from USB
S32K144
MCU
5.0 V from
VBAT or USB
UART FTDI USB
PC
with
GUI
Figure 1. Overview diagram of communication between FS23 and NXP GUI
4.2 Board features
•Phoenix (3.81 mm) male connector or Jack connector for power supply input
•Phoenix (3.81 mm) male connectors for HVLDOs
•Phoenix (3.81 mm) male connectors for CAN and LIN communication
•Phoenix (3.81 mm) male connectors for high-side drivers
•Selectable Debug mode, Test mode, and Normal mode with switches and jumpers to power up the device in
different modes
•INTB, RSTB, FS0B, LIMP0, FCCU pins
•Embedded USB to I2C/SPI protocol for easy connection to software GUI through S32K144 MCU
•Red and green LEDs to indicate signal or regulator status
•Blue LED to indicate that OTP 8 V burning voltage is set
•Header connectors for I/O configuration
•Advanced system monitoring via S32K144 MCU
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4.3 KITFS23LDOEVM featured components
Figure 2 shows the placement of connectors, configuration headers, and LEDs signaling. For information on
default jumper and switch configuration for FS2300, see Section 7.1.
Figure 2. Location of key KITFS23LDOEVM components
4.4 KITFS23LDOEVM evaluation board
This section describes the KITFS23LDOEVM evaluation board by explaining the features associated with each
jumper and switch, giving information on hardware configuration to enable these features, and providing advice
on LED signaling and test points available on the board.
Note: The silkscreen on the board gives hints on the jumper positioning depending on the functions
implemented.
The default debug configuration enables the board to be fully controlled by the S32K144 MCU (via I2C) and the
GUI. Figure 3 shows the default jumper and switch configuration for an FS2300 part.
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Figure 3. KITFS23LDOEVM default jumpers and switches configuration
Position Function Description
SW1 VIN_SEL Input voltage supply can come from battery (VIN_BAT) or from
external power supply (VIN_PHX).
SW3 HVIOx_CS Emulates a door switch as an example in cyclic sense
configuration, by default for HVIO1, possible to change to HVIO2.
SW4 VSUP_TO_WAKE1 Configures the VSUP as input for WAKE1 pin (global).
SW6 WAKEx_CS Emulates a door switch as an example in cyclic sense
configuration, by default on WAKE2, possible to change to WAKE1.
SW9 LED_SIG_SAFETY Enables LED signaling for safety pins values when ON (on bottom
side).
SW10 OTP_DCDC_EN Enables OTP DC-DC 8 V generator (see J30).
SW11 SAFETY_IO_EN Enables safety I/Os and LVIOs signal propagation between FS23
and MCU when ON (see silkscreen).
SW12 OTP_EN Enables OTP mode if OTP DC-DC enabled, else enables DBG
mode (see J30).
SW16 MCU_RST Pushing button to reset S32K144 MCU.
Table 1. Switches functions
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Position Function Description
J2 VIN_BAT Input voltage from battery via Jack connector (40 V max).
J5 V2_OUT Output for V2.
J6 VIN_PHX Input voltage from external power supply via Phoenix connector (40
V max).
J7 V3_OUT Output for V3.
J10 WAKEx_HVIOx_CONF Configuration of WAKEx and HVIOx Input/Output modes and
monitoring headers.
J12 V1_OUT Output for V1.
J16 CAN_OUT Output for CAN.
J17 HS12_OUT Output for high-side drivers HS1 and HS2.
J18 HS34_OUT Output for high-side drivers HS3 and HS4.
J20 LIN_OUT Output for LIN.
J23 FCCU2_SEL FCCU2 selection between HVIO1 or HVIO2 and monitoring
headers.
J26 VDDIO_SEL VDDIO selection between V1, V2, V3, or VDD_MCU.
J28 SPI_I2C_SEL1 MCU communication can be configured to SPI or I2C.
J29 SPI_I2C_SEL2 MCU communication can be configured to SPI or I2C.
J30 DBG_OTP_EN Enables Debug and OTP modes (see SW10 and SW12.)
J31 SPI_I2C_SEL3 MCU communication can be configured to SPI or I2C.
J32 SPI_I2C_SEL4 MCU communication can be configured to SPI or I2C.
J35 5V0_PHX_IN 5.0 V LDO power supply from Phoenix connector.
J36 MCU_SUP_SEL MCU power supply selection between 3.3 V or 5.0 V.
J37 5V0_SEL 5.0 V power supply either from USB or from LDO.
Table 2. Jumpers functions
4.4.1 VIN selection (SW1/J2/J6)
The input voltage supply can come from the battery via a Jack connector (VIN_BAT) or from an external power
supply via the Phoenix connector (VIN_PHX). Nominal VIN voltage is 12 V (40 V maximum).
Schematic label Signal name Description
SW1-1 VIN_BAT VIN input voltage supply via Jack connector.
SW1-2 VIN_OFF Board not supplied.
SW1-3 VIN_PHX VIN input voltage supply via Phoenix connector.
J2-1 VIN_BAT VIN_BAT input supply via Jack connector.
J2-2 GND Ground.
J6-1 VIN_PHX VIN_PHX input supply via Phoenix connector.
J6-2 GND Ground.
Table 3. VIN selection (SW1/J2/J6)
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4.4.2 V1, V2, V3 connectors (J12/J5/J7)
For FS2300, HVLDO1 can be configured to 3.3 V or 5.0 V, up to 100 mA with internal PMOS and up to 250 mA
with external PNP.
HVLDO2 can be configured to 3.3 V or 5.0 V, up to 100 mA current capability.
HVLDO3 is either CAN FD block supply or can be configured to 3.3 V or 5.0 V, up to 150 mA current capability.
Schematic label Signal name Description
J12-1 V1 V1 output power supply.
J12-2 GND Ground.
J5-1 V2_FB V2 output power supply.
J5-2 GND Ground.
J7-1 V3 V3 output power supply.
J7-2 GND Ground.
Table 4. V1, V2, V3 connectors (J12/J15)
4.4.3 V2 optional diode bypass (R5)
HVLDO2 has an optional protection diode against short to battery. A 0 ohm resistor R5 ON allows the user to
bypass the protection diode. R5 is ON by default.
Schematic label Description
R5-ON V2 protection diode is bypassed (local).
R5-OFF V2 is protected against short to battery by an external diode (global).
Table 5. V2 optional diode bypass (J5)
4.4.4 HVLDO1 PNP configuration (R4/R6/R7/R8)
HVLDO1 can be configured with or without PNP.
V1_E (Pin 34) and V1_B (Pin 32) are either connected to:
•V1_IN if HVLDO1 configured without external PNP
•PNP_E and PNP_B if HVLDO1 configured with external PNP
Schematic label Signal name Description
R6-ON/R7-OFF V1_IN V1_E is connected to V1_IN for HVLDO1 configuration without external PNP.
R6-OFF/R7-ON PNP_E V1_E is connected to PNP_E for HVLDO1 configuration with external PNP.
R4-ON/R8-OFF V1_IN V1_B is connected to V1_IN for HVLDO1 configuration without external PNP.
R4-OFF/R8-ON PNP_B V1_B is connected to PNP_B for HVLDO1 configuration with external PNP.
Table 6. HVLDO1 PNP configuration (R4/R6/R7/R8)
4.4.5 MCU power supply selection (J36/J37/J35)
The MCU can be supplied by 3.3 V or 5.0 V.
The green LED D21 turns ON when the MCU is supplied by VDD_MCU. The MCU can be reset by pressing
SW16.
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When VDD_MCU is supplied from onboard 5.0 V LDO (J37 in position 1-2), a distinct power supply must be
connected to J35 Phoenix connector. This way, the MCU has a distinct power supply domain from FS23 device
under evaluation.
Figure 4 describes the MCU power supply selection:
aaa-049443
PHX
5.0 V LDO12 V 1
J35
J37
5.0 V USB
GND 2
1
3J36 D21
ON when
MCU is
supplied
3.3 V LDO
ResetSW16
S32K144
MCU
3
1
2
2
Figure 4. MCU power supply selection
Schematic label Signal name Description
J36-1-2 P5V0 VDD_MCU is connected to 5.0 V (default).
J36-2-3 P3V3 VDD_MCU is connected to 3.3 V.
J37-1-2 P5V0_FROM_LDO 5.0 V power supply for VDD_MCU from LDO.
J37-2-3 P5V0_FROM_USB 5.0 V power supply for VDD_MCU from USB.
J35-1 12V_PHX_IN 12.0 V input for 5.0 V LDO supply via Phoenix connector.
J35-2 GND Ground.
Table 7. MCU power supply selection (J36/J37/J35)
4.4.6 MCU communication SPI/I2C selection (J28/J29/J31/J32)
MCU communication with FS2300 can be configured to I2C (default) or SPI.
Schematic label Signal name Description
J28-1-2 I2C_SDA I2C is selected as MCU communication protocol.
J28-2-3 SPI_CSB SPI is selected as MCU communication protocol.
J29-1-2 LVI5 LVI5 is available when I2C is selected as MCU communication protocol.
J29-2-3 SPI_MOSI SPI is selected as MCU communication protocol.
J31-1-2 I2C_SCL I2C is selected as MCU communication protocol.
J31-2-3 SPI_SCK SPI is selected as MCU communication protocol.
J32-1-2 LVO6 LVO6 is available when I2C is selected as MCU communication protocol.
J32-2-3 SPI_MISO SPI is selected as MCU communication protocol.
Table 8. MCU communication SPI/I2C selection (J28/J29/J31/J32)
4.4.7 CAN and LIN connectors (J16/J20)
The CAN transceiver is supplied internally by V3 regulator.
The LIN bus driver is supplied by VSHS supply input.
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Schematic label Signal name Description
J16-1 CANH CAN bus high.
J16-2 CANL CAN bus low.
J16-3 GND Ground.
J20-1 LIN LIN bus.
J20-2 GND Ground.
Table 9. CAN and LIN connectors (J16/J20)
4.4.8 Debug and OTP configuration (J30/SW10/SW12)
Debug mode is active when DEBUG pin (Pin 15) is set to 5 V. See Section 7.3.1. Debug mode disables the
Watchdog and sets the CAN and LIN transceivers active by default.
OTP mode is active when DEBUG pin is set to 8 V. Once in OTP mode, specific keys are necessary to enter
Test mode. See Section 7.3.2, or OTP programming process.
J30, SW10, and SW12 offer an onboard solution to set the necessary hardware context for Debug mode and
Test mode entry.
aaa-049444
100 kΩ
SW10 SW12
5.0 V USB
OTP 8 V
VBOS
DEBUG
DBG 5 V
OTP 8 V
generation FS23
J30
21
Figure 5. Debug and OTP enablement
Schematic label Signal name Description
J30-1-2 DBG_OTP_EN Jumper ON enables DBG or OTP mode depending on SW10 and
SW12 status.
SW10-1 (OFF) Open switch DC-DC disabled, no 8 V OTP generation.
SW10-2 (ON) OTP_DCDC_EN DC-DC enabled for 8 V OTP generation.
SW12-1 (OFF) Open switch OTP mode is disabled.
SW12-2 (ON) OTP_EN OTP mode is enabled if OTP DC-DC is ON. Debug mode is
enabled if OTP DC-DC is OFF.
Table 10. Debug and OTP configuration (J30/SW10/SW12)
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4.4.9 High-side driver connectors (J17/J18)
Each high-side driver (HSx) can be used to drive loads, or to perform cyclic sense when used in combination
with a high-voltage input (WAKEx or HVIOx). High-side drivers are supplied by VSHS supply voltage.
Schematic label Signal name Description
J17-1 HS2 HS2 output.
J17-2 GND Ground.
J17-3 HS1 HS1 output.
J18-1 HS4 HS4 output.
J18-2 GND Ground.
J18-3 HS3 HS3 output.
Table 11. High-side driver connectors (J17/J18)
4.4.10 VDDIO selection jumper (J26)
VDDIO selection jumper selects V1, V2, V3, or VDD_MCU for VDDIO, and links to VDDIO_SYS.
Schematic label Signal name Description
J26-1-2 V1 Set VDDIO to V1 output voltage.
J26-3-4 V2 Set VDDIO to V2 output voltage.
J26-5-6 V3 Set VDDIO to V3 output voltage.
J26-7-8 VDD_MCU Set VDDIO to VDD_MCU output voltage.
J26-9-10 VDDIO_SYS Set VDDIO_SYS to VDDIO.
Table 12. VDDIO selection jumper (J26)
4.4.11 I/Os configuration and monitoring headers
HVIOx, LVIOx, and WAKEx pins have multiple modes configurable via J23 and J10. Jumpers J23 and J10 can
also be used as monitoring headers.
aaa-049445
J23
1HVIO1
3HVIO2
5LVIO3
7LVIO4
9
2
4
FCCU2
R59
22 kΩ
6
8
10MOSI/LVI5
J10
1WAKE1_IN
3WAKE2_IN
5LIMP0_out
9WAKEx_CS_IN
11
2
4
6
7FS0B_out
WAKE1
WAKE2
MISO/LVO6
VMON_EXT8
10
12HVIOx_CS_IN
GNDGND
Figure 6. I/Os monitoring headers
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Schematic label Signal name Description
J23-1 HVIO1 HVIO1 signal access.
J23-2/4/6/8/10 FCCU2 FCCU2 signal access.
J23-3 HVIO2 HVIO2 signal access.
J23-5 LVIO3 LVIO3 signal access.
J23-7 LVIO4 LVIO4 signal access.
J23-9 MOSI/LVI5 MOSI signal access in SPI mode. LVI5 in I2C mode.
J10-1 WAKE1_IN WAKE1 input signal access.
J10-2 WAKE1 WAKE1 signal access.
J10-3 WAKE2_IN WAKE2 input signal access.
J10-4 WAKE2 WAKE2 signal access.
J10-5 LIMP0 LIMP0 signal access.
J10-6 MISO/LVO6 MISO signal access in SPI mode. LVO6 in I2C mode.
J10-7 FS0B FS0B signal access.
J10-8 VMON_EXT VMON_EXT signal access.
J10-9 WAKEx_CS_IN WAKEx cyclic sensing input signal access.
J10-10/12 GND Ground.
J10-11 HVIOx_CS_IN HVIOx cyclic sensing input signal access.
Table 13. I/O configuration and monitoring headers (J23/J10)
4.4.11.1 External voltage monitoring via VMON_EXT
The FS2300 can monitor an external regulator through VMON_EXT monitoring pin, accessible via J10-8 on
the KITFS23LDOEVM. The regulator connected to VMON_EXT must be at least 1 V to be compatible with
overvoltage and undervoltage monitoring thresholds. An external resistor bridge is used to divide the regulator
voltage if higher than 1 V, and set the middle point to 1 V. The resistor bridge value can be adjusted by using a
screwdriver on the R3 potentiometer.
aaa-049446
R2 value VMON_EXT
10 kΩ 3 V to 7 V
5.1 kΩ 2 V to 6 V
37
VMON_EXT
Middle point: 1.0 V
VMON_EXT
GND
R9
5.1 kΩ
R2
10 kΩ R3
20 kΩ
3 1
2
Figure 7. External voltage monitoring voltage divider
4.4.11.2 I/Os jumper configuration
The configuration of HVIOx, LVIOx, and WAKEx pins must be done by OTP. The hardware must be configured
depending on the chosen functionality for HVIOx, LVIOx, and WAKEx pins. The following table gives the
necessary jumper configuration for each pin-function association. A default configuration of the jumpers and
switches is given in Section 4.4, matching the default I/O configuration in blue in the table.
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Associated IO Cyclic sense Load/LED driver
HS1 Load between
J17-3 and J17-2
HVIO1 Populate R24 and R14
HS2 HVIO2 Populate R24 and R31 Load btw J17-1 and J17-2
HS3 Load between
J18-3 and J18-2
WAKE1 Populate R27 and R34
DNP R36
HS4
WAKE2 Populate R27 and R32
DNP R35
Load btw J18-1 and J18-2
Table 14. HSx configuration with corresponding resistor configuration
Cyclic sense Global input Local input
WAKE1 Populate R27 and R34
DNP R36
Populate R36 and DNP R34
Input via SW4 or J10-1
DNP R34 and R36
Input via J10-2
WAKE2 Populate R27 and R32
DNP R35
Populate R35 & DNP R32
Input via J10-3
DNP R32 and R35
Input via J10-4
Simple input Simple output Cyclic sense FCCU2 (input) LIMP1 (output) LIMP2 (output)
HVIO1 Available Available Populate
R24 and R14 J23-1-2 Available
HVIO2 Available Available Populate
R24 and R31 J23-3-4 Available
LVIO3 Available Available J23-5-6 Available
LVIO4 Available Available J23-7-8 Available
LVI5 Available if I²C Available if I²C
J23-9-10
LVO6 Available if I²C Available if I²C
Regarding J23, remove any jumper between J23-1-2 and J23-3-4 when HVIOx are used as output, or when
voltage is superior to 5 V.
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KITFS23LDOEVM evaluation board
4.4.11.3 Testing the cyclic sense function with onboard switches
HVIO1, HVIO2, WAKE1, and WAKE2 pins can be configured for cyclic sensing when coupled with their
corresponding HSx.
The KITFS23LDOEVM provides a means to emulate door switches sensing with onboard switches, as an
application example for the cyclic sense configuration.
aaa-049450
HS2 HVIOx_CS_IN HVIOx_CS
R24
C131
0.01 µF
1 2
SW3
GND GND
C132
1000 pF
DNP
GND
10 kΩ
R25
10 kΩ
Figure 8. Door switch emulation for cyclic sense configuration
Schematic label Signal name Description
SW3-1 (OFF) Open switch HVIOx senses HS2 output.
SW3-2 (ON) HVIOx_CS HVIOx senses 0 V (GND).
SW6-1 (OFF) Open switch WAKEx senses HS4 output.
SW6-2 (ON) WAKEx_CS WAKEx senses 0 V (GND).
Table 15. Cyclic sense application examples (SW3/SW6)
4.4.11.4 Setting VSUP as an input for WAKE1 pin (global)
The WAKE1 and WAKE2 pins can be configured as global input pins.
The KITFS23LDOEVM provides a means to test the global input pin configuration with onboard switches.
Switching SW4 ON configures VSUP as input for WAKE1 pin.
aaa-049451
VSUP WAKE1_IN WAKE1_GBL
C54
0.022 µF
1 2
SW4
GND
C55
0.01 µF
GND
R56
5.1 kΩ
Figure 9. Wake pins configuration as global input pins
Schematic label Signal name Description
SW4-1 (OFF) Open switch Place input on WAKE1_IN (J10-1).
SW4-2 (ON) VSUP_TO_WAKE1 VSUP configured as input for WAKE1 pin (global).
Table 16. Wake pins as global input application examples (SW4)
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KITFS23LDOEVM evaluation board
4.4.12 LED signaling
LED signaling is enabled by switches SW8/SW9 and jumper J27. The LED signaling can be turned OFF
manually at any time to avoid undesired losses and obtain more accurate current consumption measurements.
LED signaling displays the state of the following signals:
•Signals: RSTB, FS0B, INTB, LIMP0; MCU status pin (to be used during software development for debugging
purposes)
•Power: HVBUCK regulator output, HVLDOx regulator outputs
•Power supply: VBAT, MCU supply
•OTP control: Debug 5 V, OTP 8 V
Figure 10. KITFS23LDOEVM LED signaling
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KITFS23LDOEVM evaluation board
4.4.13 Test points
The KITFS23LDOEVM board has several test points that facilitate access and measurements. This section
summarizes the available test points, how they are color-coded, and whether they are a test point component
with a part number or a pad test point with no part number.
Yellow: Test loop access to safety outputs and analog signals
Red: Test loop access for power supplies and CAN/LIN bus
Black: Test loop access to GND
Figure 11. KITFS23LDOEVM test points
4.4.14 Schematic layout and bill of materials
The board layout and bill of materials for the KITFS23LDOEVM evaluation board are available at https://
www.nxp.com/KITFS23LDOEVM
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KITFS23LDOEVM evaluation board
5 Installing and configuring software tools
5.1 Flashing S32K144 MCU GUI firmware
The KITFS23LDOEVM is delivered with the S32K144 firmware already flashed.
5.2 Installing the FS23 NXP GUI software package
To install the FS2300 NXP GUI, first download or obtain the NXP GUI package, then follow the instructions
below:
1. Open the NXP GUI package. Unzip and open the 1 - NXP_GUI_Setup folder
Figure 12. GUI folder list
2. Double click NXP_GUI-version-Setup.exe to launch the application and follow the instructions.
Figure 13. NXP_GUI-version-Setup.exe
3. Click Next when the initial application setup window appears.
Figure 14. GUI setup window
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