NXP Semiconductors MC1320 Series User manual

Freescale Semiconductor
User’s Guide
© Freescale Semiconductor, Inc., 2006, 2007, 2008, 2009, 2010. All rights reserved.
Document Number: MC1320xRFCUG
Rev. 1.2, 03/2010
1 Introduction
The MC1320x RF Daughter Card (1320xRFD-A00) is used in conjunction with a microcontroller
development board for RFIC evaluation, code development, and system evaluation. The RF Daughter
Card interfaces directly to the M68EVB908GB60, RG60 and QG60 HCS08 family Microcontroller
Development Boards and to the M52235 EVB Microcontroller Development Board, but it can be adapted
to other boards that offer access to the MCU input/output ports.
The RF Daughter Card is configured with all the off-chip circuitry required for functional performance of
the MC1320x RF data modem except the MCU. The MCU interface required by the RFIC is pinned out at
the edge of the card using standard header pins. The RF interface is accomplished through an onboard PCB
antenna. Also, there is an SMT jumper that can be relocated, which will redirect the RF interface to an
on-board 50 ohm connector. The SMA connector can be used with standard coax cables for testing
purposes. Figure 1-1 shows the RF Daughter Card.
Figure 1-1. MC1320x RF Daughter Card
MC1320x RF Daughter Card
User’s Guide

MC1320x RF Daughter Card, Rev. 1.2
2Freescale Semiconductor
Introduction
Figure 1-2 shows the RF Daughter Card installed in a GB60 development board.
Figure 1-2. MC1320xRF Daughter Card In GB60 Development Board
Figure 1-3 shows the M52235 EVB development board.
Figure 1-3. M52235 EVB Development Board

Safety Information
MC1320x RF Daughter Card, Rev. 1.2
Freescale Semiconductor 3
2 Safety Information
Any modifications to this product may violate the rules of the Federal Communications Commission and
make operation of the product unlawful.
47 C.F.R. Sec. 15.21
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant
to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful
interference in a residential installation. This equipment generates uses and can radiate radio frequency
energy and, if not installed and used in accordance with the instructions, may cause harmful interference
to radio communications. However, there is no guarantee that interference will not occur in a particular
installation. If this equipment does cause harmful interference to radio or television reception, which can
be determined by turning the equipment off and on, the user is encouraged to try to correct the interference
by one or more of the following measures:
• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is
connected.
• Consult the dealer or an experienced radio/TV technician for help.
47 C.F.R. Sec.15.105(b)
This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment.
The antenna(s) used for this equipment must be installed to provide a separation distance of at least 8
inches (20cm) from all persons.
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
• This device may not cause harmful interference.
• This device must accept any interference received, including interference that may cause undesired
operation.
3 Revision History
The following table summarizes revisions to this document since the previous release (Rev 1.1).
Revision History
Location Revision
Section 6 Updated document cross reference.

MC1320x RF Daughter Card, Rev. 1.2
4Freescale Semiconductor
MC1320x MCU Interface
4 MC1320x MCU Interface
Figure 4-1 shows the typical connections between the MC1320x transceiver and a microcontroller unit
(MCU). See the MC13202/203 Reference Manual, document MC13202RM, for interface considerations.
Details about the interconnects for both the GB60 and M52235 Development boards are described in
Section 5.1, “Development Board Interconnects”.
Figure 4-1. MCU Interface Pinout
SCLK
MOSI
SS
MISO
GPIO
GPIO
IR Q
GPIO
GPIO
GPIO ATTNB
14
CEB
19
CLKO
15
GPIO1
11
GPIO2
10
GPIO3
9
GPIO4
8
GPIO7
25 GPIO5
23
GPIO6
24
IR Q B
20
MISO
18
MOSI
17
PAO_M 6
PAO_P 5
RIN_M 1
RIN_P 2
RSTB
12 RXTXEN
13
SM 7
SPICLK
16
Not Used 4
Not Used 3
XTAL1 26
XTAL2 27
VBATT
31
VDDA
32
VDDD
21
VDDINT
22
VDDLO1
29
VDDLO2
28
VDDVCO
30
GND
EP
MC13202/3
CLK
MCU

Daughter Card Description
MC1320x RF Daughter Card, Rev. 1.2
Freescale Semiconductor 5
5 Daughter Card Description
As shown in Figure 5-1 and Figure 8-1, connector J101 is the main interface to the GB60 Development
Board.TheinterfaceconnectionsdescribedinSection 5.1, “Development Board Interconnects”,fallunder
the following three broad categories:
1. Serial Peripheral Interface (SPI)
2. Control
3. Power
Figure 1-2 shows how the RF Daughter Card is mounted on the GB60 Development Board.
NOTE
Ensure that zero ohm resistor R104 is in place on the MC1320x Daughter
Card. As of this release, previous versions of the MC1320x Daughter Card
may not have R104 inserted.
NOTE
J101 Pin 1 of the MC1320x must to be connected to GB_PORT Pin 1 of the
GB60 Development Board.
As shown in Figure 5-1 and Figure 8-1, connector J102 is the main interface to the M52235 Development
Board. Figure 1-3 shows how the RF Daughter Card is mounted on the M52235 Development Board.
NOTE
J102 Pin 1 of the MC1320x must be connected to MCU_PORT Pin 1 on the
M52235 Development Board.
Figure 5-1 shows the top side of the RF Daughter Card PCB with component placement.
Figure 5-1. MC1320x Daughter Card (Top View)

MC1320x RF Daughter Card, Rev. 1.2
6Freescale Semiconductor
Daughter Card Description
Figure 5-2 shows the shows the bottom side of the RF Daughter Card PCB.
Figure 5-2. MC1320x Daughter Card (Bottom View)
5.1 Development Board Interconnects
The following sections describe the interconnects for both the GB60 and M52235 Development boards.
Table 5-1 lists the pin connections for J101 and Table 5-2 lists the pin connections for J102.
Table 5-1. J101 Pin Connections
Pin Number Pin Name Description Functionality
1,2,3,4, 6,7,8,9, 10,11,12,
15,16,17 18,21,23,
25,26,28, 29, 30,33
N/C No connection.
5 PTA2 Connects to PTA2 on GB60. ProvidesawakeupfunctiontotheMCU via Pin
22 when jumper is installed between J103 pins
1 and 2.
13 GPIO1 Connects to General Purpose
Input/Output 1 of MC1320X. When gpio_alt_en, Register 9, Bit 7 = 1, GPIO1 functions as an “Out of Idle” Indicator.
14 GPOI2 Connects to General Purpose
Input/Output 2 of MC1320X. When gpio_alt_en, Register 9, Bit 7 = 1, GPIO2 functions as a “CRC Valid” Indicator.

Daughter Card Description
MC1320x RF Daughter Card, Rev. 1.2
Freescale Semiconductor 7
19 IRQ Connects to IRQ pin of MC1320X. Allows the MC1320X to issue an IRQ to the
MCU.
20 RESET Optionally connects to RESET of
MC1320X when R101 or R102 are
installed.
Allows the MCU to reset the MC1320X.
22 PTE1/RXD1 Connects to PTE1/RXD1 of GB60. Provides awakeupfunctiontotheMCUviaPin
5 when jumper is installed between J103 pins
1 and 2.
24 XCLK/16MHz Connects to CLKO of MC1320X
when jumper is installed between
J103 pins 3 and 4.
Provides reference based on MC1320X 16
MHz reference oscillator to the MCU.
27 PTC2/BAUD
SEL Connect to PTC2/BAUD SEL of GB60.
31 RXTXEN Connect to RXTXEN of MC1320X. Allows the MCU to control the RXTXEN line of
the MC1320X.
32 RESET Connects to RESET of MC1320X. Allows the MCU to reset the MC1320X.
34 PTD5/CESI/A
TTN Connects to PTD5/CESI of GB60
when R104 is installed. Connect
directly to Pin 15 of J102.
Allowsthe MCUto wakeuptheMC1320Xfrom
Doze or Hibernate.
35 MOSI Connect to MOSI of MC1320x. SPI
36 SPSCK Connect to SPICLK of the
MC13201. SPI
37 CE Connect to CE of MC1320X. SPI
38 MISO Connects to MISO of MC1320X. SPI
39 V_IN Connects the Daughter Card to the
supply voltage output of the GB60
board.
Provides supply voltage to the Daughter Card.
Voltage must not exceed 16 Vdc. See
Section 5.1.0.3, “Power Connections”.
40 GND Connect ground on GB60 board to
ground on Daughter Card.
Table 5-1. J101 Pin Connections (continued)
Pin Number Pin Name Description Functionality

MC1320x RF Daughter Card, Rev. 1.2
8Freescale Semiconductor
Daughter Card Description
Table 5-2. J102 Pin Connections
Pin Number Pin Names Description Functionality
4, 5, 6, 7, 8, 11, 12, 14,
16, 18, 22 N/C No connection
1 V_IN Connects the Daughter Card to the
supply voltage output on the
M52235EVB.
ProvidessupplyvoltagetotheDaughterCard.
Voltage must not exceed 16 Vdc. See
Section 5.1.0.3, “Power Connections”.
2IRQ
Connects to IRQ pin of MC1320X. Allows the MC1320X to issue an IRQ to the
MCU.
3 GND Connects the ground of the RF
Daughter Card to the ground of the
M52235EVB
9 GPIO1 Connects to General Purpose
Input/Output 1 of MC1320X. When gpio_alt_en, Register 9, Bit 7 = 1, GPIO1 functions as an “Out of Idle” Indicator.
10 GPOI2 Connects to General Purpose
Input/Output 2 of MC1320X. When gpio_alt_en, Register 9, Bit 7 =1, GPIO2 functions as a “CRC Valid” Indicator.
13 RESET Connects to RESET of MC1320X
and Pin 32 of J101. Allows the MCU to reset the MC1320X.
15 PTD5/CESI Connects to ATTN of MC1320X
and Pin 34 of J101. Allows the MCU to wake up the MC1320X from Doze or Hibernate.
17 MOSI Connects to MOSI of MC1320X. SPI
19 MISO Connects to MISO of MC1320X. SPI
20 RXTXEN Connect to RXTXEN of MC1320X. Allows the MCUntrol the RXTXEN line of the
MC1320X.
21 SPICLK Connect to SPICLK of the
MC1320X SPI
23 PTE2/CE-
QSPI-CSO Connects to Pin 1 of J104 Allows Chip Enable (CE) selection. See Section 5.1.0.1, “SPI Connections”.
24 PTE2/CE-AN7 Connects to Pin 3 of J104 Allows Chip Enable (CE) selection.
See Section 5.1.0.1, “SPI Connections”.

Daughter Card Description
MC1320x RF Daughter Card, Rev. 1.2
Freescale Semiconductor 9
NOTE
In the following sections, pin numbers not in parenthesis reference the
GB60 Development Board. Pin numbers in parenthesis reference the
M52235 Development Board.
5.1.0.1 SPI Connections
J101 pins 35 through 38 (J102 pin 17, 19, 21 and 23) provide the following four wire SPI interface:
•MOSI
• SPICLK
•CE
•MISO
The MC1320x always functions as a slave device. SPI operation is described in detail in the appropriate
MC1320x Data Sheet and/or MC1320x Reference Manual.
NOTE
As it applies to the M52235 Development Board, the CE signal on (J102 Pin
23 and Pin 24) are hard wired to header J104. These pins control the
functionality of CE.
When Pin 2 and Pin 3 of J104 are shorted, CE is wired to (J102 Pin 24)
(PTE2/CE-AN7).
When Pin 1 and Pin 2 of J104 are shorted, CE is wired to (J102 Pin 23)
(PTE2/CE-QSPI_CS0).
5.1.0.2 Control Connections
• J101 Pin 19 (J102 Pin 2) is the IRQ line from the MC1320x. Connection to the MCU depends on
how the MCU services interrupts.
• J101 Pin 31 (J102 Pin 20), RXTXEN, allows the MCU to initiate transceiver functions.
• J101 Pin 34 (J102 Pin 15), ATTN, allows the MCU to wake up the MC1320x from Doze or
Hibernate low power modes.
NOTE
RXTXEN and ATTN are also available at header J105 for manual control.
• J101 Pin 24 provides the MC1320x CLKO to the MCU when a jumper is installed at J103.
• J101 Pin 32 (J102 Pin13) interfaces with the MCU to provide a Reset to the MC1320x.
• J101 Pin 5 and Pin 22 provide a wake up function to the MCU when a jumper is installed at J103.
• J101 Pin 13 and Pin 14 (J102 Pin 9 and Pin 11) provide access to the MC1320x GPIO1 and GPIO2
ports.

MC1320x RF Daughter Card, Rev. 1.2
10 Freescale Semiconductor
RF Circuit
5.1.0.3 Power Connections
J101 Pin 39 (J102 pin 1) provides the supply voltage to the RF Daughter Card. Voltage on this line should
never exceed 16.0 VDC and the nominal voltage supply should not exceed 16.0 VDC. J101 Pin 40 (J102
pin 3) is ground.
NOTE
MCU connection signals are dependent on the on-board voltage regulator.
If R105, D101, and C101 are mounted and R115 is removed, J101 Pin 39
will provide the interface supply voltage which must never exceed 3.6 V.
Nominal supply voltage should never exceed 3.4 V.
5.1.0.4 Non-MCU Connections
Header J105 provides connections to a number of MC1320x contacts for non-MCU connections. As
already stated, the RXTXEN and ATTN lines are available at J105 for external control using switches or
other hardware. The MC1320x GPIO is also available for connection to external hardware.
6RFCircuit
The MC1320x has an internal TX/RX switch. This feature allows for an external RF circuit that has a very
low component count. The MC1320x requires only a few passive components and a balun to provide an
interface to an antenna or a 50 ohm circuit. Figure 6-1 shows a schematic for only the RF portion of the
MC1320x Daughter Card.
Figure 6-1. RF Portion of 20x Daughter Card