Octavo OSD335 AM335 Series Guide

Using Ethernet with OSD335x-
AM335x System in Package
Rev.1 5/23/2019
Octavo Systems LLC
Copyright 2019
1Introduction
The Texas Instruments AM335x processor used in the OSD335x Family of System in
Package Devices supports up to two independent Gigabit Ethernet ports (10/100/1000
Mbps). This application note will help you quickly get started interfacing an Ethernet
PHY with the OSD335x, the AM335x System in Package, Family of Devices. This
document will showcase reference designs, which can be used as design examples,
make recommendations on layout, device trees and provide tips on debugging AM335x
Ethernet issues.
Notice: The information provided within this document is for informational use only.
Octavo Systems provides no guarantees or warranty to the information contained.

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Using Ethernet with OSD335x-
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Table of Contents
1Introduction ....................................................................................0
2Choosing the Right Ethernet PHY............................................................2
2.1 Reference Designs Using AM335x Ethernet............................................2
2.2 Additional Ethernet PHYs ................................................................3
3Design Example and Recommendations for Using Ethernet with the AM335x System
in Package ..........................................................................................4
3.1 Schematics.................................................................................4
3.2 Layout ......................................................................................7
3.2.1 Dual Ethernet Example ..............................................................9
4Setting up Ethernet (Device Tree) ........................................................ 11
5Debugging Tips ............................................................................... 15
5.1 Software Issues.......................................................................... 15
5.2 MAC to PHY Connections............................................................... 15
5.3 PHY to RJ45 Port Connections ........................................................ 15
5.4 Data Errors............................................................................... 16
6Revision History .............................................................................. 16

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Using Ethernet with OSD335x-
AM335x System in Package
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2Choosing the Right Ethernet PHY
The AM335x processor within the OSD335x, the AM335x System in Package, Family of
Devices contains two Ethernet MAC (Medium Access Control) peripherals that can be
used independently or together with an integrated switch. Each MAC supports MII,
RMII, RGMII and MDIO interfaces that can be used to connect to an Ethernet PHY
(Physical Layer), which in turn is connected to an Ethernet port. This allows Ethernet
cables to connect the AM335x to the rest of the network.
Ethernet PHYs are available from many different manufacturers and have a wide range
of features. The most significant features to consider when choosing an Ethernet PHY
are:
1. Power Consumption
2. Throughput/Speed –10/100/1000Mbps
3. Package type and size
4. Driver support
5. Hardware Errata
6. Ease of availability
2.1 Reference Designs Using AM335x Ethernet
Reference Designs using the AM335x Ethernet with different PHYs are listed below so
that you can choose the best fit for your requirements and jump-start your design.
1. AR8035 based OSD3358-SM-RED design from Octavo Systems –
https://octavosystems.com/files/osd3358-sm-red-eagle-files/
2. AR8035 based C-SiP RED design from Octavo Systems –
https://octavosystems.com/files/osd3358-sm-red-c-sip-eagle-files/
3. LAN8710 based SBC Reference design from Octavo Systems –
https://octavosystems.com/files/osd3358-bas-sbc-reference-design-files/
4. AR8031 based Dual Ethernet design from TI Starter Kit –
http://processors.wiki.ti.com/index.php/AM335x_StarterKit_Board_Design_Files
5. KSZ9031 based Dual Ethernet design shown in Figure 1, Figure 2, Figure 4 and
Figure 5 –design files will be published soon.

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2.2 Additional Ethernet PHYs
Below is a list of additional Ethernet PHYs from major manufacturers. This is not a
comprehensive list but can be used in case there are issues with availability of the
PHYs in the reference designs listed above.
•Texas Instruments:
http://www.ti.com/interface/ethernet/phy/overview.html
•Microchip:
https://www.microchip.com/design-centers/ethernet/ethernet-
devices/products/ethernet-phys
•Marvell:
https://www.marvell.com/transceivers/fast-ethernet-phy/
•Broadcom:
https://www.broadcom.com/products/ethernet-connectivity/
•Microsemi:
https://www.microsemi.com/product-directory/ethernet-solutions/3581-physical-
layer
For any PHY selection, we strongly recommend that you can purchase the part through
a major distributor, such as DigiKey or Mouser, and that the part has plenty of stock
available.

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AM335x System in Package
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3Design Example and Recommendations for Using Ethernet
with the AM335x System in Package
The following figures show an example of a dual AM335x Ethernet design using the
KSZ9031 Ethernet PHY to communicate with the Ethernet MAC peripherals on the
OSD335x, the AM335x System in Package, Family of Devices. The figures walk
through the schematics and layout. Reference design files for this design will be
available in the future. Please sign up for documentation updates to be notified when
they are available.
3.1 Schematics
When connecting an Ethernet PHY, you need to be aware of the default PHY
configuration pull-up / pull-down resistors. Most PHYs utilize a number of pins to set the
initial configuration of the device, such as the PHY address on the MDIO bus. It is
important that all of these configuration pins are set correctly. For example, in the figure
below, you can see the pull-up / pull-down resistors on the RX and LED interfaces that
will set the initial configuration of the PHY.

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Figure 1 - PHY 1 Ethernet Connections

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Figure 2 - PHY 2 Ethernet Connections
When creating a dual AM335x Ethernet design, it is critical that each PHY have a
different MDIO address. This will allow the single MDIO bus to communicate and
configure each PHY. Additionally, it is important to know the MDIO address of
the PHY since that will be necessary when we set up the device tree for the
Ethernet PHY.

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3.2 Layout
When laying out an Ethernet PHY, there are two different sets of connections: MAC to
PHY and PHY to RJ45 connector (i.e. the Ethernet port). The MAC to PHY connections
for the OSD335x Family of devices uses MII, RMII or RGMII. These have a bus speed
of 25 MHz, 50 MHz, 125 MHz, respectively. The PHY to RJ45 connections use
differential Ethernet signaling in the 10s to 100s of MHz depending on the Ethernet
speed required for the link.
The following are some general recommendations for Ethernet PHY layout design:
1. Use only 45o/135oangles in traces to avoid signal reflections.
2. Trace widths should be constant to maintain uniform impedance.
3. Length match TX_CLK, TXDx and RX_CLK, RXDx signals between AM335x and
Ethernet PHY. Depending on the interface type, the tolerance for length
matching becomes tighter due to the higher bus speeds
4. Length match TX+,TX- and RX+, RX- traces between Ethernet PHY and RJ45
connector/magnetics module. We have found that RJ45 connectors with an
integrated magnetic module are easier to route.
5. Keep the overall trace length between AM335x and RJ45 connector < 75mm.
6. If the RJ45 connector (with thru-hole pins) is placed on the top layer, route traces
to its pins on the bottom layer to avoid signal stubs caused by the thru-hole pins.
7. Avoid vias and layer changes for Ethernet traces.

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Figure 3 - OSD3358-SM-RED Ethernet PHY Layout Example

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AM335x System in Package
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3.2.1 Dual Ethernet Example
When laying out a dual AM335x Ethernet design, we recommend that you focus on
careful placement and routing of a single Ethernet PHY and port. Once that Ethernet
PHY and port are placed and routed to your satisfaction, the layout can be replicated
easily for the second Ethernet port. You can see an example of this in the figures below
when looking at both the signal routing and power layout.
Figure 4 - Dual Ethernet Top and Bottom Layer Example