OMAP OMAP5912 User manual

OMAP5912 Multimedia Processor
Real-Time Clock and Split Power
Reference Guide
Literature Number: SPRU782A
March 2004

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3
OMAP5912SPRU782A
Preface
Read This First
About This Manual
This document describes the real-time clock (RTC) block. The RTC is an
embedded real-time clock module directly accessible from the TIPB bus
interface.
This document also describes split power.
Notational Conventions
This document uses the following conventions.
-Hexadecimal numbers are shown with the suffix h. For example, the
following number is 40 hexadecimal (decimal 64): 40h.
Related Documentation From Texas Instruments
The following documents describe the OMAP5910 device and related
peripherals. Copies of these documents are available on the Internet at
www.ti.com. Tip: Enter the literature number in the search box provided at
www.ti.com.
OMAP5912 Multimedia Processor Device Overview and Architecture
Reference Guide (literature number SPRU748) introduces the setup,
components, and features of the OMAP5912 multimedia processor and
provides a high-level view of the device architecture.
OMAP5912 Multimedia Processor OMAP 3.2 Subsystem Reference
Guide (literature number SPRU749) introduces and briefly defines the
main features of the OMAP3.2 subsystem of the OMAP5912 multimedia
processor.
OMAP5912 Multimedia Processor DSP Sybsystem Reference Guide (lit-
erature number SPRU750) describes the OMAP5912 multimedia proc-
essor DSP subsystem. The digital signal processor (DSP) subsystem is
built around a core processor and peripherals that interface with: 1) The

Related Documentation From Texas Instruments
4OMAP5912 SPRU782A
ARM926EJS via the microprocessor unit interface (MPUI); 2) Various
standard memories via the external memory interface (EMIF); 3) Various
system peripherals via the TI peripheral bus (TIPB) bridge.
OMAP5912 Multimedia Processor Clocks Reference Guide (literature
number SPRU751) describes the clocking mechanisms of the
OMAP5912 multimedia processor. In OMAP5912, various clocks are
created from special components such as the digital phase locked loop
(DPLL) and the analog phase-locked loop (APLL).
OMAP5912 Multimedia Processor Initialization Reference Guide (litera-
ture number SPRU752) describes the reset architecture, the configura-
tion, the initialization, and the boot ROM of the OMAP5912 multimedia
processor.
OMAP5912 Multimedia Processor Power Management Reference Guide
(literature number SPRU753) describes power management in the
OMAP5912 multimedia processor. The ultralow-power device (ULPD)
generates and manages clocks and reset signals to OMAP3.2 and to
some peripherals. It controls chip-level power-down modes and handles
chip-level wake-up events. In deep sleep mode, this module is still active
to monitor wake-up events.This book describes the ULPD module and
outline architecture.
OMAP5912 Multimedia Processor Security Features Reference Guide
(literature number SPRU754) describes the security features of teh
OMAP5912 multimedia processor. The OMAP5912 security scheme re-
lies on the OMAP3.2 secure mode. The distributed security on the
OMAP3.2 platform is a Texas Instruments solution to address m-com-
merce and security issues within a mobile phone environment. The
OMAP3.2 secure mode was developed to bring hardware robustness to
the overall OMAP5912 security scheme.
OMAP5912 Multimedia Processor Direct Memory Access (DMA) Support
Reference Guide (literature number SPRU755) describes the direct
memory access support of the OMAP5912 multimedia processor. The
OMAP5912 processor has three DMAs:
JThe system DMA is embedded in OMAP3.2. It handles DMA
transfers associated with MPU and shared peripherals.
JThe DSP DMA is embedded in OMAP3.2. It handles DMA
transfers associated with DSP peripherals.
JThe generic distributed DMA (GDD) is an OMAP5912 resource
attached to the SSI peripheral. It handles only DMA transfers
associated with the SSI peripheral.

Related Documentation From Texas Instruments
5
OMAP5912SPRU782A
OMAP5912 Multimedia Processor Memory Interfaces Reference Guide
(literature number SPRU756) describes the memory interfaces of the
OMAP5912 multimedia processor.
JSDRAM (external memory interface fast, or EMIFF)
JAsynchronous and synchronous burst memory (external
memory interface slow, or EMIFS)
JNAND flash (hardware controller or software controller)
JCompactFlash on EMIFS interface
JInternal static RAM
OMAP5912 Multimedia Processor Interrupts Reference Guide (literature
number SPRU757) describes the interrupts of the OMAP5912 multime-
dia processor. Three level 2 interrupt controllers are used in
OMAP5912:
JOne MPU level 2 interrupt handler (also referred to as MPU
interrupt level 2) is implemented outside of OMAP3.2 and can
handle 128 interrupts.
JOne DSP level 2 interrupt handler (also referred to as DSP
interrupt level 2.1) is instantiated outside of OMAP3.2 and can
handle 64 interrupts.
JOne OMAP3.2 DSP level 2 interrupt handler (referenced as DSP
interrupt level 2.0) can handle 16 interrupts.
OMAP5912 Multimedia Processor Peripheral Interconnects Reference
Guide (literature number SPRU758) describes various periperal inter-
connects of the OMAP5912 multimedia processor.
OMAP5912 Multimedia Processor Timers Reference Guide (literature
number SPRU759) describes various timers of the OMAP5912 multime-
dia processor.
OMAP5912 Multimedia Processor Serial Interfaces Reference Guide (lit-
erature number SPRU760) describes the serial interfaces of the
OMAP5912 multimedia processor.
OMAP5912 Multimedia Processor Universal Serial Bus (USB) Reference
Guide (literature number SPRU761) describes the universal serial bus
(USB) host on the OMAP5912 multimedia processor. The OMAP5912
processor provides several varieties of USB functionality. Flexible multi-
plexing of signals from the OMAP5912 USB host controller, the
OMAP5912 USB function controller, and other OMAP5912 peripherals
allow a wide variety of system-level USB capabilities. Many of the
OMAP5912 pins can be used for USB-related signals or for signals from
other OMAP5912 peripherals. The OMAP5912 top-level pin multiplexing

Related Documentation From Texas Instruments
6OMAP5912 SPRU782A
controls each pin individually to select one of several possible internal pin
signal interconnections. When these shared pins are programmed for
use as USB signals, the OMAP5912 USB signal multiplexing selects how
the signals associated with the three OMAP5912 USB host ports and the
OMAP5912 USB function controller can be brought out to OMAP5912
pins.
OMAP5912 Multimedia Processor Multi-channel Buffered Serial Ports
(McBSPs) Reference Guide (literature number SPRU762) describes
the three multi-channel buffered serial ports (McBSPs) available on the
OMAP5912 device. The OMAP5912 device provides multiple high-
speed multichannel buffered serial ports (McBSPs) that allow direct in-
terface to codecs and other devices in a system.
OMAP5912 Multimedia Processor Camera Interface Reference Guide (lit-
erature number SPRU763) describes two camera inerfaces implement-
ed in the OMAP5912 multimedia processor: compact serial camera port
and camera parallel interface.
OMAP5912 Multimedia Processor Display Interface Reference Guide (lit-
erature number SPRU764) describes the display interface of the
OMAP5912 multimedia processor.
JLCD module
JLCD data conversion module
JLED pulse generator
JDisplay interface
OMAP5912 Multimedia Processor Multimedia Card (MMC/SD/SDIO) (liter-
ature number SPRU765) describes the multimedia card (MMC) interface
of the OMAP5912 multimedia processor. The multimedia card/secure
data/secure digital IO (MMC/SD/SDIO) host controller provides an inter-
face between a local host, such as a microprocessor unit (MPU) or digital
signal processor (DSP), and either an MMC or SD memory card, plus up
to four serial flash cards. The host controller handles MMC/SD/SDIO or
serial port interface (SPI) transactions with minimal local host interven-
tion.
OMAP5912 Multimedia Processor Keyboard Interface Reference Guide
(literature number SPRU766) describes the keyboard interface of the
OMAP5912 multimedia processor. The MPUIO module enables direct
I/O communication between the MPU (through the public TIPB) and ex-
ternal devices. Two types of I/O can be used: specific I/Os dedicated for
8 x 8 keyboard connection, and general-purpose I/Os.
OMAP5912 Multimedia Processor General-Purpose Interface Reference
Guide (literature number SPRU767) describes the general-purpose in-

Related Documentation From Texas Instruments
7
OMAP5912SPRU782A
terface of the OMAP5912 multimedia processor. There are four GPIO
modules in the OMAP5912. Each GPIO peripheral controls 16 dedicated
pins configurable either as input or output for general purposes. Each pin
has an independent control direction set by a programmable register.
The two−edge control registers configure events (rising edge, falling
edge, or both edges) on an input pin to trigger interrupts or wake−up re-
quests (depending on the system mode). In addition, an interrupt mask
register masks out specified pins. Finally, the GPIO peripherals provide
the set and clear capabilities on the data output registers and the inter-
rupt mask registers. After detection, all event sources are merged and
a single synchronous interrupt (per module) is generated in active mode,
whereas a unique wake−up line is issued in idle mode. Eight data output
lines of the GPIO3 are ORed together to generate a global output line at
the OMAP5912 boundary. This global output line can be used in conjunc-
tion with the SSI to provide a CMT−APE interface to the OMAP5912.
OMAP5912 Multimedia Processor VLYNQ Serial Communications Inter-
face Reference Guide (literature number SPRU768) describes the
VLYNQ of the OMAP5912 multimedia processor.
VLYNQ is a serial communications interface that enables the extension
of an internal bus segment to one or more external physical devices. The
external devices are mapped into local, physical address space and ap-
pear as if they are on the internal bus of the OMAP 5912. The external
devices must also have a VLYNQ interface. The VLYNQ module serial-
izes bus transactions in one device, transfers the serialized data be-
tween devices via a VLYNQ port, and de-serializes the transaction in the
external device.
OMAP5912 includes one VLYNQ module connected on OCPT2 target
port and OCPI initiator port. These connections are configured via a stat-
ic switch, which selects either SSI or VLYNQ module. This switch, for-
bids the simultaneous use of GDD/SSI and VLYNQ. The switch is con-
trolled by the VLYNQ_EN bit in the OMAP5912 configuration control reg-
ister (CONF_5912_CTRL).
OMAP5912 Multimedia Processor Pinout Reference Guide (literature
number SPRU769) provides the pinout of the OMAP5912 multimedia
processor. After power-up reset, the user can change the configuration
of the default interfaces. If another interface is available on top of the de-
fault, it is possible to enable a new interface for each ball by setting the
corresponding 3-bit field of the associated FUNC_MUX_CTRL register.
It is also possible to configure on-chip pullup/pulldown. This document

Trademarks
8OMAP5912 SPRU782A
also describes the various power domains so that the user can apply the
different interfaces seamlessly with external components.
OMAP5912 Multimedia Processor Window Tracer (WT) Reference Guide
(literature number SPRU770) describes the window tracer module used
to capture the memory transactions from four interfaces: EMIFF, EMIFS,
OCP-T1, and OCP-T2. This module is located in the OMAP3.2 traffic
controller (TC).
OMAP5912 Multimedia Processor Real-Time Clock Reference Guide (lit-
erature number SPRUxxx) describes the real-time clock of the
OMAP5912 multimedia processor. The real-time clock (RTC) block is an
embedded real-time clock module directly accessible from the TIPB bus
interface.
Trademarks
OMAP and the OMAP symbol are trademarks of Texas Instruments.

Contents
9
Contents
1 Overview 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Split Power Overview 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Internal Level Shifters 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Split Power Block 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Interface Block 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Backup Block 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Output Control 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Backup Signal Management 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 On-Chip Reset Generation 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Resets for OMAP5912 Device With Split Power Feature Enabled 18. . . . . . . . . . . . . . . . . .
6.2 Resets for OMAP5912 Device With Split Power Feature Not Used 18. . . . . . . . . . . . . . . . .
RTC_WAKE_INT 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Using Split Power 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 ABB Functions Incompatible With Split Power 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 ABB Functions Compatible With Split Power 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 ON to OFF Description 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 OFF to ON Description 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Interrupt Management 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 Timer Interrupt 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Alarm Interrupt 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 Oscillator Drift Compensation 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 Split Power Compatibility 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 RTC Registers 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1 Time and Calendar Registers and Time and Calendar Alarm Registers 27. . . . . . . . . . . . .
11.2 General Registers 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3 Compensation Registers 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12 Setting Time and Calendar Information 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1 Modify Time and Calendar Registers 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2 Rounding Seconds 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.1 Time and Calendar Registers 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures
10 OMAP5912 SPRU782A
Figures
1 Real-Time Clock 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Split Power System in OMAP5912 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Internal Level Shifter 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Split Power Block Diagram 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 ASIC Reset Scheme 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 PWRON_RESET Connection 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 RTC_WAKE_INT Generation 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 OMAP5912 in RESET_MODE = 1 or RTC_CTRL_REG.SPLIT_POWER = 0 20. . . . . . . . . . .
9 Startup With RTC_CTRL_REG.SPLIT_POWER = 1
for OMAP5912 RESET_MODE = 0 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 ON to OFF With SPLIT POWER = 1 for OMAP5912 RESET_MODE = 0 22. . . . . . . . . . . . . .
11 OFF to ON With RTC_CTRL_REG.SPLIT_POWER = 1
for OMAP5912 RESET_MODE = 0 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12 Periodic Interrupt 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13 Alarm Interrupt 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14 Oscillator Drift Compensation 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15 Time and Calendar Register and Time and Calendar Alarm Register Access 28. . . . . . . . . . .
16 Compensation Scheduling 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables
11
OMAP5912SPRU782A
Tables
1 Timer Interrupt Events 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 RTC Registers 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Time and Calendar Register Time Units 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Seconds Register (SECONDS_REG) 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Minutes Register (MINUTES_REG) 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Hours Register (HOURS_REG) 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Days Register (DAYS_REG) 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Months Register (MONTHS_REG) 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 Years Register (YEARS_REG) 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 Weeks Register (WEEKS_REG) 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 Reserved 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12 Alarm Seconds Register (ALARM_SECONDS_REG) 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13 Alarm Minutes Register (ALARM_MINUTES_REG) 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14 Alarm Hours Register (ALARM_HOURS_REG) 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15 Alarm Days Register (ALARM_DAYS_REG) 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16 Alarm Months Register (ALARM_MONTHS_REG) 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17 Alarm Years Register (ALARM_YEARS_REG) 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18 RTC Control Register (RTC_CTRL_REG) 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19 RTC Status Register (RTC_STATUS_REG) 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20 RTC Interrupts Register (RTC_INTERRUPTS_REG) 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21 RTC Compensation LSB Register (RTC_COMP_LSB_REG) 38. . . . . . . . . . . . . . . . . . . . . . . .
22 RTC Compensation MSB Register (RTC_COMP_MSB_REG) 39. . . . . . . . . . . . . . . . . . . . . . .
23 RTC Oscillator Register (RTC_OSC_REG) 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13
Real-Time Clock (RTC)SPRU782A
RealĆTimeĂClockĂ(RTC)
1 Overview
The real-time clock (RTC) block is an embedded real-time clock module
directly accessible from the TIPB bus interface. The basic functions of RTC
block are:
-Time information (seconds/minutes/hours) directly in binary coded
decimal (BCD) code
-Calendar information (day/month/year/day of the week) directly in BCD
code up to the year 2099
-Interrupt generation, periodically (1s/1m/1h/1d period) or at a precise time
of the day (alarm function)
-30-s time correction
-Oscillator frequency calibration
Figure 1 shows the real-time clock block.

Split Power Overview
Real-Time Clock (RTC)
14 SPRU782A
Figure 1. Real-Time Clock
Seconds Minutes Hours Days Months
counter
32-kHz
Years
Week
Alarm
Interrupt
32 kHz
Compensation Control
IRQ_ALARM
days
IRQ_ALARM
IRQ_TIMER
2 Split Power Overview
To achieve minimum consumption in the OFF state in device equipment, some
active logic elements are supplied. Those elements are the real-time clock
(RTC) and the 32-kHz oscillator (OSC32K) in the digital baseband (DBB), and
the power-on reset (POR) and the dedicated regulator in the analog baseband
(ABB). This approach is possible when using split power, which splits the core
power domain into two subdomains powered with different voltage supplies.
Internal level shifters handle the separation between the core and the active
domain.

Internal Level Shifters
15
Real-Time Clock (RTC)SPRU782A
Figure 2. Split Power System in OMAP5912
RTC
Split
power
logic
and
I/O
control
32 kHz reset and select
XO32K conf
registers
XO32K
CVDDRTC
RESET_MODE
RTC_ON_NOFF
RTC_WAKE_INT
PWRON_RESET
CLK32K_OUT
CLK32K_IN
DVDDRTC
Split power ring level shifters
OMAP5912
CLK32K
External level shifter
Internal level shifter
Direct I/O
RESERWRON_CORE
POWERDOWN
3 Internal Level Shifters
Internal level shifters are library-standard macrocells that interface two core
domains powered with two different voltage supplies.
The cell can be seen as a means to isolate one power domain from an other.
In the case where one domain is shut down. the level shifters ensure a known
state at the boundary of the two domains.
The level shifters are divided into two parts:
-UC469: Powered by the primary power supply. Because of the input signal
A, it creates Y and YZ, which are A buffered and A inverted, respectively.

Split Power Block
Real-Time Clock (RTC)
16 SPRU782A
-UC470: Powered by the secondary power supply. Because of the
differential signals, A and AZ (given by UC469), it creates the signal Y that
is equivalent to the input of UC469 but in the second core supply domain.
This cell has a PWRDN signal so that when power supply of UC469 does
not exist (input signals A and AZ are ambiguous), this cell does not have
any through-current and the output is set to 0.
Figure 3. Internal Level Shifter
Y
A
UC469
YZ
Y
A
AZ
PWRDN
UC470
CVDD CVDDRTC
PWRDN = 0 => Y=A
PWRDN =1 => Y= 0
4 Split Power Block
The split power module contains two blocks: the interface block and the
backup block. The interface block, between the core and the backup elements,
is supplied by the core power supply CVDD. The backup block contains the
RTC and some logic.

Output Control
17
Real-Time Clock (RTC)SPRU782A
Figure 4. Split Power Block Diagram
Interface block Backup block
RTC
UC469
UC469
UC469
UC469
UC469
UC469
UC470
UC470
UC470
UC470
UC470
UC470
T
I
P
B
TIPB
L
o
g
i
c
b
l
o
c
k
pwrdn
pwrdn
pwrdn
pwrdn
pwrdn
pwrdn
CLK_32kHz_CORE CTS
C
S
d
e
c
o
d
e
4.1 Interface Block
This block separates the backup elements and the ASIC core. It also contains
the UC469 and some logic. The logic allows masking of the TIPB bus signals
to avoid consumption of internal level shifters, except in RTC accesses.
4.2 Backup Block
This block contains the elements kept in OFF mode in the DBB, the RTC, the
32-kHz clock, the UC470, and the logic to force the DBB to OFF mode. The
module input/outputs are RTC_ON_NOFF, PWRON_RESET, RTC_WAKE_
INT, RESET_MODE, and POWERDOWN.
5 Output Control
To keep them from supplying the ASIC core, the split power block outputs are
forced to logical zero.

On-Chip Reset Generation
Real-Time Clock (RTC)
18 SPRU782A
5.1 Backup Signal Management
In OFF mode, only the split power module is supplied. The ON_OFF,
RTC_WAKE_INT, and PWRON_RESET signals, which control the activity
management of the DBB, are also active.
6 On-Chip Reset Generation
-If RTC_CTRL_REG.SPLIT_POWER = 0 or RESET_MODE = 1 then the
OMAP5912 is reset only by PWRON_RESET.:
-If RESET_MODE = 0 and RTC_CTRL_REG.SPLIT_POWER= 1 then
PWRON_RESET AND RTC_ON_NOFF will reset OMAP5912.:
Figure 5. ASIC Reset Scheme
PWRON_RESET RESPWRON_CORE
RTC_ON_NOFF
RESET_MODE
RTC_CTRL_REG.SPLIT_POWER
6.1 Resets for OMAP5912 Device With Split Power Feature Enabled
The RTC module and its internal real time counter are reset by
PWRON_RESET during power up. OMAP5912 ASIC gates are reset by
PWRON_RESET_CORE.
Subsequent resets are asserted with RTC_ON_NOFF. The RTC module is not
reset by the assertion of RTC_ON_NOFF. While RTC_ON_NOFF is asserted
low, the system powers down OMAP5912 ASIC gates.
6.2 Resets for OMAP5912 Device With Split Power Feature Not Used
For OMAP5912 devices that are forced during reset in reset mode 1,
PWRON_RESET_CORE is logically equal to PWRON_RESET and only to
PWRON_RESET.
For OMAP5912 devices that are forced during reset in reset mode 0
(OMAP1510 legacy) and no split power,PWRON_RESET_CORE is logically
equal to PWRON_RESET and only to PWRON_RESET.

On-Chip Reset Generation
19
Real-Time Clock (RTC)SPRU782A
Figure 6. PWRON_RESET Connection
Split power
ON_OFF
PWRON_RESET RESPWRON_CORE ULPD CHIP_RESET
Core
RESET_MODE
reset
block
RTC_WAKE_INT
The RTC_WAKE_INT pin now collects the interrupt sources used to awaken
the ULPD from deep sleep. It is gated with RTC_CTRL_REG.SPLIT_POWER
and the RTC alarm. In OFF mode the IRQ_SET is set to 0, and only the
IRQ_ALARM_EXT can generate an interrupt on the pin RTC_WAKE_INT.
With a device in ON state, both IRQ_ALARM_EXT and IRQ_SET can
generate an RTC_WAKE_INT.
The RTC_CTRL_REG.SPLIT_POWER signal generates RTC_WAKE_INT to
avoid an RTC_WAKE_INT in ON mode for the ABB.
Figure 7 shows the generation of the RTC_WAKE_INT.
In the OMAP5912 core, IRQ_SET is not used and is set to 0. RTC_WAKE_INT
is used only for the ABB.

Using Split Power
Real-Time Clock (RTC)
20 SPRU782A
Figure 7. RTC_WAKE_INT Generation
RTC
Interrupts from
MPU that awake
the ULPD : IRQ_SET
RTC_WAKE_INT
IRQ_ALARM_EXT
SPLIT_POWER
7 Using Split Power
7.1 ABB Functions Incompatible With Split Power
Do not use split power. The power cannot be cut in the core.
Figure 8. OMAP5912 in RESET_MODE = 1 or RTC_CTRL_REG.SPLIT_POWER = 0
Unknown
Unknown
Unknown
Unknown
Unknown
Don’t care
Power on Reset release
CLK32K_IN
PWRON_RESET
RTC_ON_NOFF
R
ESPWRON_CORE
CLK32K_CORE
POWERDOWN
RESET_MODE_0

Using Split Power
21
Real-Time Clock (RTC)SPRU782A
7.2 ABB Functions Compatible With Split Power
Figure 9. Startup With RTC_CTRL_REG.SPLIT_POWER = 1 for OMAP5912
RESET_MODE = 0
Main battery
insertion Start of the core 32 kHz clock
CLK_32_OUT
RTC_ON_NOFF
RESPWRON_CORE
CLK32K_CORE
RESET_MODE = 0
Figure 9 assumes that backup battery is already inserted, only the RTC power
domain is powered and that the RTC is isolated from the core
(RTC_ON_NOFF ball is held low, and SPLIT_POWER bit in RTC is set to 1).
Once ‘the main battery is plugged in, the core domain is reset by
PWRON_RESET_CORE until RTC_ON_NOFF becomes high; the isolation
mode also becomes inactive. The ULPD state machine can start.