Texas Instruments OMAP5910 User manual

OMAP5910 Dual-Core Processor
MicroWire Interface
Reference Guide
Literature Number: SPRU686
October 2003

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5OMAP5910SPRU686
Preface
Read This First
About This Manual
This serial synchronous interface can drive two serial external components.
For the external devices, this interface is compatible with the MicroWire
standard and is seen as the master.
Notational Conventions
This document uses the following conventions.
-Hexadecimal numbers are shown with the suffix h. For example, the
following number is 40 hexadecimal (decimal 64): 40h.
Related Documentation From Texas Instruments
The following documents describe the OMAP5910 device and related
peripherals. Copies of these documents are available on the Internet at
www.ti.com. Tip: Enter the literature number in the search box provided at
www.ti.com.
OMAP5910 Dual-Core Processor MPU Subsystem Reference Guide (litera-
ture number SPRU671)
OMAP5910 Dual-Core Processor DSP Subsystem Reference Guide
(literature number SPRU672)
OMAP5910 Dual-Core Processor Memory Interface Traffic Controller
Reference Guide (literature number SPRU673)
OMAP5910 Dual-Core Processor System DMA Controller Reference Guide
(literature number SPRU674)
OMAP5910 Dual-Core Processor LCD Controller Reference Guide (litera-
ture number SPRU675)
OMAP5910 Dual-Core Processor Universal Asynchronous
Receiver/Transmitter (UART) Devices Reference Guide (literature number
SPRU676)

Trademarks
6OMAP5910 SPRU686
OMAP5910 Dual-Core Processor Universal Serial Bus (USB) and Frame
Adjustment Counter (FAC) Reference Guide (literature number SPRU677)
OMAP5910 Dual-Core Processor Clock Generation and System Reset
Management Reference Guide (literature number SPRU678)
OMAP5910 Dual-Core Processor General-Purpose Input/Output (GPIO)
Reference Guide (literature number SPRU679)
OMAP5910 Dual-Core Processor MMC/SD Reference Guide (literature
number SPRU680)
OMAP5910 Dual-Core Processor Inter-Integrated Circuit (I2C) Controller
Reference Guide (literature number SPRU681)
OMAP5910 Dual-Core Processor Timer Reference Guide (literature number
SPRU682)
OMAP5910 Dual-Core Processor Inter-Processor Communication
Reference Guide (literature number SPRU683)
OMAP5910 Dual-Core Processor Camera Interface Reference Guide
(literature number SPRU684)
OMAP5905 Dual-Core Processor Multichannel Serial Interface (MCSI)
Reference Guide (literature number SPRU685)
OMAP5910 Dual-Core Processor Micro-Wire Interface Reference Guide
(literature number SPRU686)
OMAP5910 Dual-Core Processor Real-Time Clock (RTC) Reference Guide
(literature number SPRU687)
OMAP5910 Dual-Core Processor HDQ/1-Wire Interface Reference Guide
(literature number SPRU688)
OMAP5910 Dual-Core Processor PWL, PWT, and LED Peripheral
Reference Guide (literature number SPRU689)
OMAP5910 Dual-Core Processor Multichannel Buffered Serial Port (McBSP)
Reference Guide (literature number SPRU708)
Trademarks
OMAP and the OMAP symbol are trademarks of Texas Instruments.
Related Documentation From Texas Instruments / Trademarks

Contents
7SPRU686
Contents
1 MicroWire Interface 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 MicroWire Registers 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Protocol Description 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Example of Protocol Using a Serial EEPROM (XL93LC66) 21. . . . . . . . . . . . . . . . . . . . . . . .
1.3.1 Read Cycle 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2 Write Cycle 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Example of Protocol Using an LCD Controller (COP472-3) 23. . . . . . . . . . . . . . . . . . . . . . . .
1.4.1 Loading Sequence 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Example of Protocol Using the Autotransmit Mode 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Example of the Autotransmit Mode With DMA Support 26. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures
1 Block Diagram 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Behavior of a X25C02 EEPROM Read Cycle 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Behavior of a XL93LC66 EEPROM Read Cycle 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Read Cycle in the Autotransmit Mode 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
1 MicroWire Registers 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Transmit-Data Register (TDR) 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Receive-Data Register (RDR) 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Control-and-Status Register (CSR) 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Setup Register 1 (SR1) 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Setup Register 2 (SR2) 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Setup Register 3 (SR3) 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Setup Register 4 (SR4) (Read/Write) 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 Setup Register 5 (SR5) (Read/Write) 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8SPRU686

9MicroWire InterfaceSPRU686
MicroWire Interface
1 MicroWire Interface
This serial synchronous interface can drive two serial external components.
For the external devices, this interface is compatible with the MicroWire
standard and is seen as the master (see Figure 1).
A transmit DMA mode is available.
Figure 1. Block Diagram
Clock
divider
Transmit data register UWIRE.SDO
Control
logic
UWIRE.SCLK
T
IPB
Receive data register UWIRE.SDI
Control−and−status
Setup registers
UWIRE.CS[3:0]
Clock register
Clock
enable
MPUXOR_CK
register
DMA_REQ to system DMA_REQ[6:0]
Inth lvl2 (2,3) - edge
2
(16 bits)
(16 bits)
1.1 MicroWire Registers
The starting address in the peripheral range (hex) is FFFB:3000
Table 1 lists the MicroWire registers. Table 2 through Table 9
describe the individual registers.
Table 1. MicroWire Registers
Register Description R/W Size Address Offset
TDR Transmit data register W16 bits FFFB:3000 0x00
RDR Receive data register R16 bits FFFB:3000 0x00

MicroWire Interface
MicroWire Interface10 SPRU686
Table 1. MicroWire Registers (Continued)
Register OffsetAddressSizeR/WDescription
CSR Controland status register R/W 16 bits FFFB:3000 0x04
SR1 Setup register 1 R/W 16 bits FFFB:3000 0x08
SR2 Setup register 2 R/W 16 bits FFFB:3000 0x0C
SR3 Setup register 3 R/W 16 bits FFFB:3000 0x10
SR4 Setup register 4 R/W 16 bits FFFB:3000 0x14
SR5 Setup register 5 R/W 16 bits FFFB:3000 0x18
Table 2. Transmit-Data Register (TDR)
Bits Field Description Reset
Value
15−0 TD Data to transmit Undefined
Whatever its size, the word must be aligned on the most significant bit (MSB)
side.
Note:
The MSB (bit 15) is the first transmitted bit.
Table 3. Receive-Data Register (RDR)
Bits Field Description Reset
Value
15−0 RD Received data Undefined
Whatever its size, the word is aligned on the least significant bit (LSB) side.
Note:
The LSB (bit 0) is the last received bit.

MicroWire Interface
11MicroWire InterfaceSPRU686
Table 4. Control-and-Status Register (CSR)
Bits Field Value Description Reset
Value
15 RDRB RDRB bit = 1 indicates that the receive (RDR) area is full.
When the controller reads the content of the RDR, this bit
is cleared.
This bit is read only.
0
14 CSRB CSRB bit = 0 indicates that the control and status register
(CSR) is ready to receive new data.
After starting a MicroWire transfer with the CSR, this bit is
set to 1. When the corresponding action has been done,
the CSRB is reset. This bit is controlled by a MicroWire
internal state machine running on the F_INT internal clock
(12 MHz/N). If the CSR is read just after being written and
the MPU is running at a high frequency (60 MHz or 120
MHz, for instance) compared to the internal clock, the
CSRB status bit may still be low for the first read access.
The CSRB latency is 0 if the transfer was initiated by
modifying the CS_CMD bit, but it can be 0−3 cycles if
initiated by the START bit. Some suggested work-arounds
are to: (a) have a few NOPs between initiating a MicroWire
transfer and checking the CSRB status or( b) check that
the CSRB first has a high value on an initial read before it
goes low on a subsequent read.
This bit is read only.
0
13 START 1 Start a write and/or a read process.
This bit is automatically reset by the internal logic when a
write or a read process is activated.
Send the NB_BITS_WR bits (contained in TDR) to the
serial output DO. If the NB_BITS_WR is equal to zero,
then the write process is not started.
Receive the NB_BITS_RD bits from the serial input DI and
store them in the RDR.
0
12 CS_CMD 1 Set the chip-select of the selected device to its active level. 0
11−10 INDEX Index of the external device Undefined
00 CS0
01 Reserved
10 Reserved
11 CS3

MicroWire Interface
MicroWire Interface12 SPRU686
Table 4. Control-and-Status Register (CSR) (Continued)
Bits Reset
Value
DescriptionValueField
9−5 NB_BITS_WR Number of bits to transmit Undefined
4−0 NB_BITS_RD Number of bits to receive Undefined
This register sets up the serial interface for the first and the second external
components.
Table 5. Setup Register 1 (SR1)
Bits Field Value Description Reset
Value
11−6 Reserved
5 CS0_CHK Before activating a write process, determines if the
external device is ready.
Undefined
0 No check is done and the write process is immediately
executed.
1 If the DI signal is low, the interface considers the
external component busy; if the DI is high, the interface
considers that the first external component is ready and
starts the write process.
Used when the CS0 is selected.
4−3 CS0_FRQ Defines the frequency of the serial clock, SCLK, when
the CS0 is selected (F_INT is the frequency of the
internal clock to the MicroWire control logic as defined in
register SR3).
Undefined
00 F_INT/2
01 F_INT/4
10 F_INT/8
11 Reserved
2CS0CS_LVL Defines the active level of the chip-select by CS0 0