Motorola MC68340 User manual

©MOTOROLA INC., 1992
MC68340
Integrated Processor with DMA
User’s Manual
µ MOTOROLA
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PREFACE
The complete documentation package for the MC68340 consists of the MC68340UM/AD,
MC68340 Integrated Processor with DMA User’s Manual , M68000PM/AD, MC68000
Family Programmer’s Reference Manual,
and the MC68340P/D, MC68340 Integrated
Processor with DMA Product Brief
.
The
MC68340 Integrated with DMA Processor User’s Manual describes the programming,
capabilities, registers, and operation of the MC68340; the
MC68000 Family Programmer’s
Reference Manual
provides instruction details for the MC68340; and the MC68340
Integrated Processor with DMA Product Brief
provides a brief description of the MC68340
capabilities.
This user’s manual is organized as follows:
Section 1 Device Overview Section 8 Timer Modules
Section 2 Signal Descriptions Section 9 IEEE 1149.1 Test Access
Section 3 Bus Operation Port
Section 4 System Integration Module Section 10 Applications
Section 5 CPU32 Section 11 Electrical Characteristics
Section 6 DMA Controller Module Section 12 Ordering Information and
Section 7 Serial Module Mechanical Data
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11/2/95 SECTION 1: OVERVIEW UM Rev 1
MOTOROLA MC68340 USER'S MANUAL iii
TABLE OF CONTENTS
Paragraph Page
Number Title Number
Section 1
Device Overview
1.1 M68300 Family..................................................................................................1-2
1.1.1 Organization..................................................................................................1-3
1.1.2 Advantages....................................................................................................1-3
1.2 Central Processor Unit.....................................................................................1-3
1.2.1 CPU32............................................................................................................1-4
1.2.2 Background Debug Mode...........................................................................1-4
1.3 On-Chip Peripherals........................................................................................1-5
1.3.1 System Integration Module.........................................................................1-5
1.3.1.1 External Bus Interface..............................................................................1-5
1.3.1.2 System Configuration and Protection...................................................1-6
1.3.1.3 Clock Synthesizer.....................................................................................1-6
1.3.1.4 Chip Select and Wait State Generation...............................................1-6
1.3.1.5 Interrupt Handling.....................................................................................1-6
1.3.1.6 Discrete I/O Pins........................................................................................1-6
1.3.1.7 IEEE 1149.1 Test Access Port................................................................1-7
1.3.2 Direct Memory Access Module...................................................................1-7
1.3.3 Serial Module................................................................................................1-7
1.3.4 Timer Modules...............................................................................................1-8
1.4 Power Consumption Management................................................................1-8
1.5 Physical..............................................................................................................1-9
1.6 Compact Disc-Interactive................................................................................1-9
1.7 More Information...............................................................................................1-10
Section 2
Signal Descriptions
2.1 Signal Index.......................................................................................................2-2
2.2 Address Bus.......................................................................................................2-4
2.2.1 Address Bus (A23–A0)................................................................................2-4
2.2.2 Address Bus (A31–A24)..............................................................................2-4
2.3 Data Bus (D15–D0)..........................................................................................2-4
2.4 Function Codes (FC3–FC0)............................................................................2-5
2.5 Chip Selects (CS3–CS0)................................................................................2-5
2.6 Interrupt Request Level (IRQ7, IRQ6, IRQ5, IRQ3)...................................2-6
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11/2/95 SECTION 1: OVERVIEW UM Rev.1.0
iv MC68340 USER'S MANUAL MOTOROLA
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
2.7 Bus Control Signals.........................................................................................2-6
2.7.1 Data and Size Acknowledge (DSACK1, DSACK0)................................2-6
2.7.2 Address Strobe (AS)....................................................................................2-6
2.7.3 Data Strobe (DS)...........................................................................................2-7
2.7.4 Transfer Size (SIZ1, SIZ0)..........................................................................2-7
2.7.5 Read/Write (R/W)...........................................................................................2-7
2.8 Bus Arbitration Signals....................................................................................2-7
2.8.1 BusRequest(BR)..........................................................................................2-7
2.8.2 Bus Grant (BG)...............................................................................................2-7
2.8.3 Bus Grant Acknowledge (BGACK).............................................................2-7
2.8.4 Read-Modify-Write Cycle (RMC).................................................................2-8
2.9 Exception Control Signals..............................................................................2-8
2.9.1 Reset (RESET)...............................................................................................2-8
2.9.2 Halt (HALT)....................................................................................................2-8
2.9.3 Bus Error (BERR)...........................................................................................2-8
2.10 Clock Signals....................................................................................................2-8
2.10.1 System Clock (CLKOUT)............................................................................2-8
2.10.2 Crystal Oscillator (EXTAL, XTAL)...............................................................2-9
2.10.3 External Filter Capacitor (XFC)..................................................................2-9
2.10.4 Clock Mode Select (MODCK).....................................................................2-9
2.11 Instrumentation and Emulation Signals.......................................................2-9
2.11.1 Instruction Fetch (IFETCH)..........................................................................2-9
2.11.2 Instruction Pipe (IPIPE)...............................................................................2-9
2.11.3 Breakpoint (BKPT)........................................................................................2-10
2.11.4 Freeze (FREEZE)..........................................................................................2-10
2.12 DMA Module Signals.......................................................................................2-10
2.12.1 DMA Request (DREQ2, DREQ1).................................................................2-10
2.12.2 DMA Acknowledge (DACK2, DACK1)......................................................2-10
2.12.3 DMA Done (DONE2, DONE1)......................................................................2-10
2.13 Serial Module Signals.....................................................................................2-11
2.13.1 Serial Crystal Oscillator (X2, X1)...............................................................2-11
2.13.2 Serial External Clock Input (SCLK)...........................................................2-11
2.13.3 Receive Data (RxDA, RxDB).......................................................................2-11
2.13.4 Transmit Data (TxDA, TxDB).......................................................................2-11
2.13.5 Clear to Send (CTSA, CTSB).....................................................................2-11
2.13.6 Request to Send (RTSA, RTSB)................................................................2-11
2.13.7 Transmitter Ready (T≈RDYA).....................................................................2-11
2.13.8 Receiver Ready (R≈RDYA).........................................................................2-12
2.14 Timer Signals....................................................................................................2-12
2.14.1 Timer Gate (TGATE2, TGATE1)................................................................2-12
2.14.2 Timer Input (TIN2, TIN1)..............................................................................2-12
2.14.3 Timer Output (TOUT2, TOUT1)...................................................................2-12
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11/2/95 SECTION 1: OVERVIEW UM Rev 1
MOTOROLA MC68340 USER'S MANUAL v
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
2.15 Test Signals.......................................................................................................2-13
2.15.1 Test Clock (TCK)...........................................................................................2-13
2.15.2 Test Mode Select (TMS)..............................................................................2-13
2.15.3 Test Data In (TDI)..........................................................................................2-13
2.15.4 Test Data Out (TDO).....................................................................................2-13
2.16 Synthesizer Power (VCCSYN)..........................................................................2-13
2.17 System Power and Ground (VCC and GND)................................................2-13
2.18 Signal Summary...............................................................................................2-13
Section 3
Bus Operation
3.1 Bus Transfer Signals........................................................................................3-1
3.1.1 Bus Control Signals.....................................................................................3-2
3.1.2 Function Code Signals................................................................................3-3
3.1.3 Address Bus (A31–A0)................................................................................3-4
3.1.4 Address Strobe (AS)....................................................................................3-4
3.1.5 Data Bus (D15–D0)......................................................................................3-4
3.1.6 Data Strobe (DS)...........................................................................................3-4
3.1.7 Bus Cycle Termination Signals..................................................................3-4
3.1.7.1 Data Transfer and Size Acknowledge Signals
(DSACK1 and DSACK0).....................................................................3-4
3.1.7.2 Bus Error (BERR).......................................................................................3-5
3.1.7.3 Autovector (AVEC)....................................................................................3-5
3.2 Data Transfer Mechanism...............................................................................3-5
3.2.1 Dynamic Bus Sizing.....................................................................................3-5
3.2.2 Misaligned Operands...................................................................................3-7
3.2.3 Operand Transfer Cases.............................................................................3-7
3.2.3.1 Byte Operand to 8-Bit Port, Odd or Even (A0 = X)..............................3-7
3.2.3.2 Byte Operand to 16-Bit Port, Even (A0 = 0)..........................................3-8
3.2.3.3 Byte Operand to 16-Bit Port, Odd (A0 = 1)...........................................3-9
3.2.3.4 Word Operand to 8-Bit Port, Aligned.....................................................3-9
3.2.3.5 Word Operand to 16-Bit Port, Aligned...................................................3-10
3.2.3.6 Long-word Operand to 8-Bit Port, Aligned...........................................3-10
3.2.3.7 Long-Word Operand to 16-Bit Port, Aligned........................................3-12
3.2.4 Bus Operation................................................................................................3-14
3.2.5 Synchronous Operation with DSACK≈.....................................................3-14
3.2.6 Fast Termination Cycles..............................................................................3-15
3.3 Data Transfer Cycles........................................................................................3-16
3.3.1 Read Cycle.....................................................................................................3-16
3.3.2 Write Cycle.....................................................................................................3-18
3.3.3 Read-Modify-Write Cycle.............................................................................3-19
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11/2/95 SECTION 1: OVERVIEW UM Rev.1.0
vi MC68340 USER'S MANUAL MOTOROLA
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
3.4 CPU Space Cycles...........................................................................................3-21
3.4.1 Breakpoint Acknowledge Cycle.................................................................3-22
3.4.2 LPSTOP Broadcast Cycle...........................................................................3-23
3.4.3 Module Base Address Register Access....................................................3-27
3.4.4 Interrupt Acknowledge Bus Cycles............................................................3-27
3.4.4.1 Interrupt Acknowledge Cycle—Terminated Normally........................3-27
3.4.4.2 Autovector Interrupt Acknowledge Cycle.............................................3-29
3.4.4.3 Spurious Interrupt Cycle..........................................................................3-30
3.5 Bus Exception Control Cycles........................................................................3-32
3.5.1 Bus Errors.......................................................................................................3-34
3.5.2 Retry Operation.............................................................................................3-36
3.5.3 Halt Operation...............................................................................................3-38
3.5.4 Double Bus Fault..........................................................................................3-39
3.6 Bus Arbitration...................................................................................................3-40
3.6.1 Bus Request...................................................................................................3-43
3.6.2 Bus Grant........................................................................................................3-43
3.6.3 Bus Grant Acknowledge..............................................................................3-43
3.6.4 Bus Arbitration Control.................................................................................3-44
3.6.5 Show Cycles..................................................................................................3-44
3.7 Reset Operation................................................................................................3-46
Section 4
System Integration Module
4.1 Module Overview..............................................................................................4-1
4.2 Module Operation.............................................................................................4-2
4.2.1 Module Base Address Register Operation...............................................4-2
4.2.2 System Configuration and Protection Operation....................................4-3
4.2.2.1 System Configuration..............................................................................4-5
4.2.2.2 Internal Bus Monitor.................................................................................4-6
4.2.2.3 Double Bus Fault Monitor........................................................................4-6
4.2.2.4 Spurious Interrupt Monitor......................................................................4-6
4.2.2.5 Software Watchdog..................................................................................4-6
4.2.2.6 Periodic Interrupt Timer...........................................................................4-7
4.2.2.6.1 Periodic Timer Period Calculation.....................................................4-8
4.2.2.6.2 Using the Periodic Timer as a Real-Time Clock.............................4-9
4.2.2.7 Simultaneous Interrupts by Sources in the SIM40.............................4-9
4.2.3 Clock Synthesizer Operation......................................................................4-9
4.2.3.1 Phase Comparator and Filter.................................................................4-11
4.2.3.2 Frequency Divider....................................................................................4-12
4.2.3.3 Clock Control.............................................................................................4-13
4.2.4 Chip Select Operation.................................................................................4-13
4.2.4.1 Programmable Features..........................................................................4-14
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11/2/95 SECTION 1: OVERVIEW UM Rev 1
MOTOROLA MC68340 USER'S MANUAL vii
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
4.2.4.2 Global Chip Select Operation................................................................4-14
4.2.5 External Bus Interface Operation...............................................................4-15
4.2.5.1 Port A...........................................................................................................4-15
4.2.5.2 Port B...........................................................................................................4-16
4.2.6 Low-Power Stop...........................................................................................4-17
4.2.7 Freeze.............................................................................................................4-17
4.3 Programming Model.........................................................................................4-18
4.3.1 Module Base Address Register (MBAR)...................................................4-20
4.3.2 System Configuration and Protection Registers.....................................4-21
4.3.2.1 Module Configuration Register (MCR)..................................................4-21
4.3.2.2 Autovector Register (AVR).......................................................................4-23
4.3.2.3 Reset Status Register (RSR)...................................................................4-23
4.3.2.4 Software Interrupt Vector Register (SWIV)...........................................4-24
4.3.2.5 System Protection Control Register (SYPCR).....................................4-24
4.3.2.6 Periodic Interrupt Control Register (PICR)...........................................4-26
4.3.2.7 Periodic Interrupt Timer Register (PITR)...............................................4-27
4.3.2.8 Software Service Register (SWSR)......................................................4-28
4.3.3 Clock Synthesizer Control Register (SYNCR)........................................4-28
4.3.4 Chip Select Registers..................................................................................4-29
4.3.4.1 Base Address Registers..........................................................................4-30
4.3.4.2 Address Mask Registers..........................................................................4-31
4.3.4.3 Chip Select Registers Programming Example....................................4-33
4.3.5 External Bus Interface Control....................................................................4-33
4.3.5.1 Port A Pin Assignment Register 1 (PPARA1).......................................4-33
4.3.5.2 Port A Pin Assignment Register 2 (PPARA2).......................................4-34
4.3.5.3 Port A Data Direction Register (DDRA).................................................4-34
4.3.5.4 Port A Data Register (PORTA)................................................................4-34
4.3.5.5 Port B Pin Assignment Register (PPARB)............................................4-35
4.3.5.6 Port B Data Direction Register (DDRB).................................................4-35
4.3.5.7 Port B Data Register (PORTB, PORTB1)..............................................4-35
4.4 MC68340 Initialization Sequence.................................................................4-36
4.4.1 Startup............................................................................................................4-36
4.4.2 SIM40 Module Configuration.....................................................................4-36
4.4.3 SIM40 Example Configuration Code........................................................4-38
Section 5
CPU32
5.1 Overview.............................................................................................................5-1
5.1.1 Features..........................................................................................................5-2
5.1.2 Virtual Memory..............................................................................................5-2
5.1.3 Loop Mode Instruction Execution..............................................................5-3
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11/2/95 SECTION 1: OVERVIEW UM Rev.1.0
viii MC68340 USER'S MANUAL MOTOROLA
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
5.1.4 Vector Base Register....................................................................................5-4
5.1.5 Exception Handling......................................................................................5-4
5.1.6 Addressing Modes........................................................................................5-5
5.1.7 Instruction Set................................................................................................5-5
5.1.7.1 Table Lookup and Interpolate Instructions...........................................5-7
5.1.7.2 Low-Power STOP Instruction.................................................................5-7
5.1.8 Processing States.........................................................................................5-7
5.1.9 Privilege States.............................................................................................5-7
5.2 Architecture Summary.....................................................................................5-8
5.2.1 Programming Model.....................................................................................5-8
5.2.2 Registers.........................................................................................................5-10
5.3 Instruction Set....................................................................................................5-11
5.3.1 M68000 Family Compatibility.....................................................................5-11
5.3.1.1 New Instructions........................................................................................5-11
5.3.1.1.1 Low-Power Stop (LPSTOP)................................................................5-11
5.3.1.1.2 Table Lookup and Interpolation (TBL)..............................................5-12
5.3.1.2 Unimplemented Instructions...................................................................5-12
5.3.2 Instruction Format and Notation.................................................................5-12
5.3.3 Instruction Summary....................................................................................5-15
5.3.3.1 Condition Code Register.........................................................................5-20
5.3.3.2 Data Movement Instructions...................................................................5-21
5.3.3.3 Integer Arithmetic Operations.................................................................5-22
5.3.3.4 Logic Instructions......................................................................................5-24
5.3.3.5 Shift and Rotate Instructions...................................................................5-24
5.3.3.6 Bit Manipulation Instructions...................................................................5-25
5.3.3.7 Binary-Coded Decimal (BCD) Instructions..........................................5-26
5.3.3.8 Program Control Instructions..................................................................5-26
5.3.3.9 System Control Instructions....................................................................5-27
5.3.3.10 Condition Tests.........................................................................................5-29
5.3.4 Using the TBL Instructions..........................................................................5-29
5.3.4.1 Table Example 1: Standard Usage.......................................................5-30
5.3.4.2 Table Example 2: Compressed Table..................................................5-31
5.3.4.3 Table Example 3: 8-Bit Independent Variable....................................5-32
5.3.4.4 Table Example 4: Maintaining Precision..............................................5-34
5.3.4.5 Table Example 5: Surface Interpolations.............................................5-36
5.3.5 Nested Subroutine Calls.............................................................................5-36
5.3.6 Pipeline Synchronization with the NOP Instruction................................5-36
5.4 Processing States.............................................................................................5-36
5.4.1 State Transitions...........................................................................................5-37
5.4.2 Privilege Levels.............................................................................................5-37
5.4.2.1 Supervisor Privilege Level......................................................................5-37
5.4.2.2 User Privilege Level.................................................................................5-39
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11/2/95 SECTION 1: OVERVIEW UM Rev 1
MOTOROLA MC68340 USER'S MANUAL ix
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
5.4.2.3 Changing Privilege Level........................................................................5-39
5.5 Exception Processing......................................................................................5-39
5.5.1 Exception Vectors.........................................................................................5-40
5.5.1.1 Types of Exceptions.................................................................................5-41
5.5.1.2 Exception Processing Sequence..........................................................5-41
5.5.1.3 Exception Stack Frame............................................................................5-42
5.5.1.4 Multiple Exceptions..................................................................................5-42
5.5.2 Processing of Specific Exceptions............................................................5-44
5.5.2.1 Reset...........................................................................................................5-44
5.5.2.2 Bus Error.....................................................................................................5-46
5.5.2.3 Address Error.............................................................................................5-46
5.5.2.4 Instruction Traps........................................................................................5-47
5.5.2.5 Software Breakpoints...............................................................................5-47
5.5.2.6 Hardware Breakpoints.............................................................................5-48
5.5.2.7 Format Error...............................................................................................5-48
5.5.2.8 Illegal or Unimplemented Instructions..................................................5-48
5.5.2.9 Privilege Violations...................................................................................5-49
5.5.2.10 Tracing........................................................................................................5-50
5.5.2.11 Interrupts.....................................................................................................5-51
5.5.2.12 Return from Exception..............................................................................5-52
5.5.3 Fault Recovery...............................................................................................5-53
5.5.3.1 Types of Faults..........................................................................................5-55
5.5.3.1.1 Type I—Released Write Faults...........................................................5-55
5.5.3.1.2 Type II—Prefetch, Operand, RMW, and MOVEP Faults.................5-56
5.5.3.1.3 Type III—Faults During MOVEM Operand Transfer.......................5-57
5.5.3.1.4 Type IV—Faults During Exception Processing...............................5-57
5.5.3.2 Correcting a Fault.....................................................................................5-57
5.5.3.2.1 Type I—Completing Released Writes via Software.......................5-57
5.5.3.2.2 Type I—Completing Released Writes via RTE................................5-57
5.5.3.2.3 Type II—Correcting Faults via RTE....................................................5-58
5.5.3.2.4 Type III—Correcting Faults via Software..........................................5-58
5.5.3.2.5 Type III—Correcting Faults by Conversion and Restart.................5-58
5.5.3.2.6 Type III—Correcting Faults via RTE...................................................5-59
5.5.3.2.7 Type IV—Correcting Faults via Software.........................................5-59
5.5.4 CPU32 Stack Frames..................................................................................5-60
5.5.4.1 Four-Word Stack Frame..........................................................................5-60
5.5.4.2 Six-Word Stack Frame.............................................................................5-60
5.5.4.3 Bus Error Stack Frame.............................................................................5-60
5.6 Development Support......................................................................................5-63
5.6.1 CPU32 Integrated Development Support................................................5-63
5.6.1.1 Background Debug Mode (BDM) Overview........................................5-64
5.6.1.2 Deterministic Opcode Tracking Overview............................................5-64
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11/2/95 SECTION 1: OVERVIEW UM Rev.1.0
xMC68340 USER'S MANUAL MOTOROLA
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
5.6.1.3 On-Chip Hardware Breakpoint Overview.............................................5-64
5.6.2 Background Debug Mode...........................................................................5-65
5.6.2.1 Enabling BDM...........................................................................................5-65
5.6.2.2 BDM Sources............................................................................................5-66
5.6.2.2.1 External
BKPT Signal..........................................................................5-66
5.6.2.2.2 BGND Instruction..................................................................................5-66
5.6.2.2.3 Double Bus Fault..................................................................................5-66
5.6.2.3 Entering BDM............................................................................................5-66
5.6.2.4 Command Execution................................................................................5-67
5.6.2.5 BDM Registers...........................................................................................5-67
5.6.2.5.1 Fault Address Register (FAR).............................................................5-67
5.6.2.5.2 Return Program Counter (RPC).........................................................5-67
5.6.2.5.3 Current Instruction Program Counter (PCC)....................................5-67
5.6.2.6 Returning from BDM.................................................................................5-68
5.6.2.7 Serial Interface..........................................................................................5-68
5.6.2.7.1 CPU Serial Logic..................................................................................5-69
5.6.2.7.2 Development System Serial Logic....................................................5-71
5.6.2.8 Command Set...........................................................................................5-73
5.6.2.8.1 Command Format.................................................................................5-73
5.6.2.8.2 Command Sequence Diagram..........................................................5-74
5.6.2.8.3 Command Set Summary.....................................................................5-75
5.6.2.8.4 Read A/D Register (RAREG/RDREG)................................................5-76
5.6.2.8.5 Write A/D Register (WAREG/WDREG)..............................................5-77
5.6.2.8.6 Read System Register (RSREG)........................................................5-77
5.6.2.8.7 Write System Register (WSREG).......................................................5-78
5.6.2.8.8 Read Memory Location (READ).........................................................5-79
5.6.2.8.9 Write Memory Location (WRITE)........................................................5-79
5.6.2.8.10 Dump Memory Block (DUMP)............................................................5-80
5.6.2.8.11 Fill Memory Block (FILL)......................................................................5-82
5.6.2.8.12 Resume Execution (GO)......................................................................5-83
5.6.2.8.13 Call User Code (CALL)........................................................................5-83
5.6.2.8.14 Reset Peripherals (RST)......................................................................5-85
5.6.2.8.15 No Operation (NOP).............................................................................5-85
5.6.2.8.16 Future Commands................................................................................5-86
5.6.3 Deterministic Opcode Tracking..................................................................5-86
5.6.3.1 Instruction Fetch (IFETCH)......................................................................5-86
5.6.3.2 Instruction Pipe (IPIPE)...........................................................................5-87
5.6.3.3 Opcode Tracking during Loop Mode....................................................5-88
5.7 Instruction Execution Timing...........................................................................5-88
5.7.1 Resource Scheduling..................................................................................5-88
5.7.1.1 Microsequencer........................................................................................5-89
5.7.1.2 Instruction Pipeline...................................................................................5-89
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MOTOROLA MC68340 USER'S MANUAL xi
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
5.7.1.3 Bus Controller Resources.......................................................................5-89
5.7.1.3.1 Prefetch Controller................................................................................5-90
5.7.1.3.2 Write Pending Buffer............................................................................5-90
5.7.1.3.3 Microbus Controller..............................................................................5-91
5.7.1.4 Instruction Execution Overlap.................................................................5-91
5.7.1.5 Effects of Wait States................................................................................5-92
5.7.1.6 Instruction Execution Time Calculation................................................5-92
5.7.1.7 Effects of Negative Tails..........................................................................5-93
5.7.2 Instruction Stream Timing Examples........................................................5-94
5.7.2.1 Timing Example 1—Execution Overlap................................................5-94
5.7.2.2 Timing Example 2—Branch Instructions..............................................5-95
5.7.2.3 Timing Example 3—Negative Tails.......................................................5-96
5.7.3 Instruction Timing Tables............................................................................5-97
5.7.3.1 Fetch Effective Address...........................................................................5-99
5.7.3.2 Calculate Effective Address....................................................................5-100
5.7.3.3 MOVE Instruction......................................................................................5-101
5.7.3.4 Special-Purpose MOVE Instruction.......................................................5-101
5.7.3.5 Arithmetic/Logic Instructions...................................................................5-102
5.7.3.6 Immediate Arithmetic/Logic Instructions...............................................5-105
5.7.3.7 Binary-Coded Decimal and Extended Instructions............................5-106
5.7.3.8 Single Operand Instructions...................................................................5-107
5.7.3.9 Shift/Rotate Instructions...........................................................................5-108
5.7.3.10 Bit Manipulation Instructions...................................................................5-109
5.7.3.11 Conditional Branch Instructions.............................................................5-110
5.7.3.12 Control Instructions...................................................................................5-111
5.7.3.13 Exception-Related Instructions and Operations..................................5-111
5.7.3.14 Save and Restore Operations................................................................5-111
Section 6
DMA Controller Module
6.1 DMA Module Overview....................................................................................6-2
6.2 DMA Module Signal Definitions.....................................................................6-4
6.2.1 DMA Request (DREQ≈)................................................................................6-4
6.2.2 DMA Acknowledge (DACK≈)......................................................................6-4
6.2.3 DMA Done (DONE≈).....................................................................................6-4
6.3 Transfer Request Generation.........................................................................6-4
6.3.1 Internal Request Generation.......................................................................6-4
6.3.1.1 Internal Request, Maximum Rate...........................................................6-5
6.3.1.2 Internal Request, Limited Rate...............................................................6-5
6.3.2 External Request Generation.....................................................................6-5
6.3.2.1 External Burst Mode.................................................................................6-5
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xii MC68340 USER'S MANUAL MOTOROLA
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
6.3.2.2 External Cycle Steal Mode.....................................................................6-5
6.4 Data Transfer Modes........................................................................................6-6
6.4.1 Single-Address Mode..................................................................................6-6
6.4.1.1 Single-Address Read...............................................................................6-7
6.4.1.2 Single-Address Write...............................................................................6-9
6.4.2 Dual-Address Mode.....................................................................................6-12
6.4.2.1 Dual-Address Read..................................................................................6-12
6.4.2.2 Dual-Address Write..................................................................................6-14
6.5 Bus Arbitration...................................................................................................6-18
6.6 DMA Channel Operation.................................................................................6-18
6.6.1 Channel Initialization and Startup.............................................................6-18
6.6.2 Data Transfers...............................................................................................6-19
6.6.2.1 Internal Request Transfers......................................................................6-19
6.6.2.2 External Request Transfers.....................................................................6-19
6.6.3 Channel Termination...................................................................................6-20
6.6.3.1 Channel Termination...............................................................................6-20
6.6.3.2 Interrupt Operation....................................................................................6-20
6.6.3.3 Fast Termination Option..........................................................................6-20
6.7 Register Description.........................................................................................6-22
6.7.1 Module Configuration Register (MCR)......................................................6-23
6.7.2 Interrupt Register (INTR)..............................................................................6-26
6.7.3 Channel Control Register (CCR)...............................................................6-26
6.7.4 Channel Status Register (CSR).................................................................6-30
6.7.5 Function Code Register (FCR)...................................................................6-32
6.7.6 Source Address Register (SAR)................................................................6-33
6.7.7 Destination Address Register (DAR).........................................................6-33
6.7.8 Byte Transfer Counter Register (BTC)......................................................6-34
6.8 Data Packing.....................................................................................................6-35
6.9 DMA Channel Initialization Sequence.........................................................6-36
6.9.1 DMA Channel Configuration......................................................................6-36
6.9.1.1 DMA Channel Operation in Single-Address Mode............................6-37
6.9.1.2 DMA Channel Operation in Dual-Address Mode...............................6-37
6.9.2 DMA Channel Example Configuration Code..........................................6-38
Section 7
Serial Module
7.1 Module Overview..............................................................................................7-2
7.1.1 Serial Communication Channels A and B...............................................7-3
7.1.2 Baud Rate Generator Logic........................................................................7-3
7.1.3 Internal Channel Control Logic..................................................................7-3
7.1.4 Interrupt Control Logic.................................................................................7-3
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11/2/95 SECTION 1: OVERVIEW UM Rev 1
MOTOROLA MC68340 USER'S MANUAL xiii
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
7.1.5 Comparison of Serial Module to MC68681.............................................7-4
7.2 Serial Module Signal Definitions...................................................................7-4
7.2.1 Crystal Input or External Clock (X1)..........................................................7-5
7.2.2 Crystal Output (X2).......................................................................................7-5
7.2.3 External Input (SCLK)..................................................................................7-6
7.2.4 Channel A Transmitter Serial Data Output (TxDA).................................7-6
7.2.5 Channel A Receiver Serial Data Input (RxDA)........................................7-6
7.2.6 Channel B Transmitter Serial Data Output (TxDB).................................7-6
7.2.7 Channel B Receiver Serial Data Input (RxDB)........................................7-6
7.2.8 Channel A Request-To-Send (RTSA) ......................................................7-6
7.2.8.1 RTSA...........................................................................................................7-6
7.2.8.2 OP0..............................................................................................................7-6
7.2.9 Channel B Request-To-Send (RTSB).......................................................7-6
7.2.9.1 RTSB...........................................................................................................7-7
7.2.9.2 OP1..............................................................................................................7-7
7.2.10 Channel A Clear-To-Send (CTSA)...........................................................7-7
7.2.11 Channel B Clear-To-Send (CTSB)............................................................7-7
7.2.12 Channel A Transmitter Ready (T≈RDYA).................................................7-7
7.2.12.1 T≈RDYA......................................................................................................7-7
7.2.12.2 OP6..............................................................................................................7-7
7.2.13 Channel A Receiver Ready (R≈RDYA).....................................................7-7
7.2.13.1 R≈RDYA......................................................................................................7-7
7.2.13.2 FFULLA.......................................................................................................7-7
7.2.13.3 OP4..............................................................................................................7-7
7.3 Operation............................................................................................................7-8
7.3.1 Baud Rate Generator...................................................................................7-8
7.3.2 Transmitter and Receiver Operating Modes............................................7-8
7.3.2.1 Transmitter.................................................................................................7-10
7.3.2.2 Receiver......................................................................................................7-11
7.3.2.3 FIFO Stack..................................................................................................7-12
7.3.3 Looping Modes.............................................................................................7-14
7.3.3.1 Automatic Echo Mode..............................................................................7-14
7.3.3.2 Local Loopback Mode.............................................................................7-14
7.3.3.3 Remote Loopback Mode.........................................................................7-14
7.3.4 Multidrop Mode.............................................................................................7-15
7.3.5 Bus Operation................................................................................................7-17
7.3.5.1 Read Cycles...............................................................................................7-17
7.3.5.2 Write Cycles...............................................................................................7-17
7.3.5.3 Interrupt Acknowledge Cycles................................................................7-17
7.4 Register Description and Programming.......................................................7-17
7.4.1 Register Description.....................................................................................7-17
7.4.1.1 Module Configuration Register (MCR)..................................................7-19
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TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
7.4.1.2 Interrupt Level Register (ILR)..................................................................7-21
7.4.1.3 Interrupt Vector Register (IVR)................................................................7-21
7.4.1.4 Mode Register 1 (MR1)............................................................................7-22
7.4.1.5 Status Register (SR).................................................................................7-24
7.4.1.6 Clock-Select Register (CSR)..................................................................7-26
7.4.1.7 Command Register (CR).........................................................................7-27
7.4.1.8 Receiver Buffer (RB).................................................................................7-30
7.4.1.9 Transmitter Buffer (TB).............................................................................7-30
7.4.1.10 Input Port Change Register (IPCR)........................................................7-31
7.4.1.11 Auxiliary Control Register (ACR)............................................................7-32
7.4.1.12 Interrupt Status Register (ISR)................................................................7-32
7.4.1.13 Interrupt Enable Register (IER)...............................................................7-34
7.4.1.14 Input Port (IP).............................................................................................7-35
7.4.1.15 Output Port Control Register (OPCR)....................................................7-35
7.4.1.16 Output Port Data Register (OP)..............................................................7-37
7.4.1.17 Mode Register 2 (MR2)............................................................................7-37
7.4.2 Programming.................................................................................................7-40
7.4.2.1 Serial Module Initialization.....................................................................7-40
7.4.2.2 I/O Driver Example....................................................................................7-40
7.4.2.3 Interrupt Handling.....................................................................................7-40
7.5 Serial Module Initialization Sequence.........................................................7-46
7.5.1 Serial Module Configuration......................................................................7-46
7.5.2 Serial Module Example Configuration Code..........................................7-47
Section 8
Timer Modules
8.1 Module Overview..............................................................................................8-1
8.1.1 Timer and Counter Functions.....................................................................8-2
8.1.1.1 Prescaler and Counter.............................................................................8-2
8.1.1.2 Timeout Detection.....................................................................................8-2
8.1.1.3 Comparator................................................................................................8-2
8.1.1.4 Clock Selection Logic..............................................................................8-3
8.1.2 Internal Control Logic...................................................................................8-3
8.1.3 Interrupt Control Logic.................................................................................8-4
8.2 Timer Modules Signal Definitions.................................................................8-4
8.2.1 Timer Input (TIN1, TIN2)..............................................................................8-5
8.2.2 Timer Gate (TGATE1, TGATE2)................................................................8-6
8.2.3 Timer Output (TOUT1, TOUT2)...................................................................8-6
8.3 Operating Modes..............................................................................................8-6
8.3.1 Input Capture/Output Compare..................................................................8-6
8.3.2 Square-Wave Generator.............................................................................8-8
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TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
8.3.3 Variable Duty-Cycle Square-Wave Generator........................................8-9
8.3.4 Variable-Width Single-Shot Pulse Generator.........................................8-10
8.3.5 Pulse-Width Measurement..........................................................................8-12
8.3.6 Period Measurement....................................................................................8-13
8.3.7 Event Count...................................................................................................8-14
8.3.8 Timer Bypass.................................................................................................8-16
8.3.9 Bus Operation................................................................................................8-17
8.3.9.1 Read Cycles...............................................................................................8-17
8.3.9.2 Write Cycles...............................................................................................8-17
8.3.9.3 Interrupt Acknowledge Cycles................................................................8-17
8.4 Register Description.........................................................................................8-17
8.4.1 Module Configuration Register (MCR)......................................................8-18
8.4.2 Interrupt Register (IR)...................................................................................8-20
8.4.3 Control Register (CR)...................................................................................8-20
8.4.4 Status Register (SR).....................................................................................8-23
8.4.5 Counter Register (CNTR)............................................................................8-25
8.4.6 Preload 1 Register (PREL1)........................................................................8-25
8.4.7 Preload 2 Register (PREL2)........................................................................8-26
8.4.8 Compare Register (COM)............................................................................8-26
8.5 Timer Module Initialization Sequence..........................................................8-27
8.5.1 Timer Module Configuration.......................................................................8-27
8.5.2 Timer Module Example Configuration Code...........................................8-28
Section 9
IEEE 1149.1 Test Access Port
9.1 Overview.............................................................................................................9-1
9.2 TAP Controller...................................................................................................9-2
9.3 Boundary Scan Register.................................................................................9-3
9.4 Instruction Register...........................................................................................9-9
9.4.1 EXTEST (000)...............................................................................................9-10
9.4.2 SAMPLE/PRELOAD (001)..........................................................................9-10
9.4.3 BYPASS (X1X, 101).....................................................................................9-11
9.4.4 HI-Z (100).......................................................................................................9-11
9.5 MC68340 Restrictions......................................................................................9-11
9.6 Non-IEEE 1149.1 Operation...........................................................................9-12
Section 10
Applications
10.1 Minimum System Configuration...................................................................10-1
10.1.1 Processor Clock Circuitry..........................................................................10-1
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xvi MC68340 USER'S MANUAL MOTOROLA
TABLE OF CONTENTS (Concluded)
Paragraph Page
Number Title Number
10.1.2 Reset Circuitry.............................................................................................10-3
10.1.3 SRAM Interface...........................................................................................10-3
10.1.4 ROM Interface..............................................................................................10-4
10.1.5 Serial Interface............................................................................................10-4
10.2 Memory Interface Information.......................................................................10-5
10.2.1 Using an 8-Bit Boot ROM...........................................................................10-5
10.2.2 Access Time Calculations.........................................................................10-6
10.2.3 Calculating Frequency-Adjusted Output................................................10-7
10.2.4 Interfacing an 8-Bit Device to 16-Bit Memory Using
Single-Address DMA Mode..................................................................10-10
10.3 Power Consumption Considerations..........................................................10-10
10.3.1 MC68340 Power Reduction at 5V ..........................................................10-11
10.3.2 MC68340V (3.3 V) .....................................................................................10-13
Section 11
Electrical Characteristics
11.1 Maximum Rating.............................................................................................11-1
11.2 Thermal Characteristics.................................................................................11-1
11.3 Power Considerations...................................................................................11-2
11.4 AC Electrical Specification Definitions.......................................................11-2
11.5 DC Electrical Specifications.........................................................................11-5
11.6 AC Electrical Specifications Control Timing..............................................11-6
11.7 AC Timing Specifications..............................................................................11-8
11.8 DMA Module AC Electrical Specifications.................................................11-19
11.9 Timer Module Electrical Specifications......................................................11-20
11.10 Serial Module Electrical Specifications......................................................11-22
11.11 IEEE 1149.1 Electrical Specifications.........................................................11-25
Section 12
Ordering Information and Mechanical Data
12.1 Standard MC68340 Ordering Information.................................................12-1
12.2 Pin Assignment...............................................................................................12-2
12.2.1 144-Lead Ceramic Quad Flat Pack (FE Suffix).....................................12-2
12.2.2 145-Lead Plastic Pin Grid Array (RP Suffix)..........................................12-4
12.3 Package Dimensions.....................................................................................12-6
12.3.1 FE Suffix.......................................................................................................12-6
12.3.2 RP Suffix.......................................................................................................12-7
Index
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11/2/95 SECTION 1: OVERVIEW UM Rev 1
MOTOROLA MC68340 USER'S MANUAL xvii
LIST OF ILLUSTRATIONS
Figure Page
Number Title Number
1-1 Block Diagram.........................................................................................................1-1
2-1 Functional Signal Groups.....................................................................................2-1
3-1 Input Sample Window............................................................................................3-2
3-2 MC68340 Interface to Various Port Sizes..........................................................3-7
3-3 Long-Word Operand Read Timing from 8-Bit Port............................................3-11
3-4 Long-Word Operand Write Timing to 8-Bit Port.................................................3-12
3-5 Long-Word and Word Read and Write Timing—16-Bit Port...........................3-13
3-6 Fast Termination Timing........................................................................................3-15
3-7 Word Read Cycle Flowchart.................................................................................3-16
3-8 Word Write Cycle Flowchart..................................................................................3-18
3-9 Read-Modify-Write Cycle Timing.........................................................................3-19
3-10 CPU Space Address Encoding............................................................................3-21
3-11 Breakpoint Operation Flowchart..........................................................................3-24
3-12 Breakpoint Acknowledge Cycle Timing (Opcode Returned)..........................3-25
3-13 Breakpoint Acknowledge Cycle Timing (Exception Signaled)......................3-26
3-14 Interrupt Acknowledge Cycle Flowchart.............................................................3-28
3-15 Interrupt Acknowledge Cycle Timing..................................................................3-29
3-16 Autovector Operation Timing................................................................................3-31
3-17 Bus Error without DSACK≈...................................................................................3-35
3-18 Late Bus Error with DSACK≈................................................................................3-36
3-19 Retry Sequence......................................................................................................3-37
3-20 Late Retry Sequence.............................................................................................3-38
3-21 HALT Timing............................................................................................................3-39
3-22 Bus Arbitration Flowchart for Single Request....................................................3-41
3-23 Bus Arbitration Timing Diagram—Idle Bus Case..............................................3-42
3-24 Bus Arbitration Timing Diagram—Active Bus Case.........................................3-42
3-25 Bus Arbitration State Diagram..............................................................................3-45
3-26 Show Cycle Timing Diagram................................................................................3-46
3-27 Timing for External Devices Driving RESET......................................................3-47
3-28 Power-Up Reset Timing Diagram........................................................................3-48
4-1 SIM40 Module Register Block..............................................................................4-3
4-2 System Configuration and Protection Function................................................4-5
4-3 Software Watchdog Block Diagram....................................................................4-7
4-4 Clock Block Diagram for Crystal Operation.......................................................4-10
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xviii MC68340 USER'S MANUAL MOTOROLA
LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
4-5 MC68340 Crystal Oscillator..................................................................................4-10
4-6 Clock Block Diagram for External Oscillator Operation...................................4-11
4-7 Full Interrupt Request Multiplexer........................................................................4-16
4-8 SIM40 Programming Model..................................................................................4-19
5-1 CPU32 Block Diagram...........................................................................................5-3
5-2 Loop Mode Instruction Sequence.......................................................................5-3
5-3 User Programming Model.....................................................................................5-9
5-4 Supervisor Programming Model Supplement..................................................5-9
5-5 Status Register........................................................................................................5-10
5-6 Instruction Word General Format.........................................................................5-12
5-7 Table Example 1.....................................................................................................5-30
5-8 Table Example 2.....................................................................................................5-31
5-9 Table Example 3.....................................................................................................5-33
5-10 Exception Stack Frame..........................................................................................5-42
5-11 Reset Operation Flowchart....................................................................................5-45
5-12 Format $0—Four-Word Stack Frame..................................................................5-60
5-13 Format $2—Six-Word Stack Frame....................................................................5-60
5-14 Internal Transfer Count Register..........................................................................5-61
5-15 Format $C—BERR Stack for Prefetches and Operands..................................5-62
5-16 Format $C—BERR Stack on MOVEM Operand................................................5-62
5-17 Format $C—Four- and Six-Word BERR Stack..................................................5-63
5-18 In-Circuit Emulator Configuration........................................................................5-64
5-19 Bus State Analyzer Configuration.......................................................................5-64
5-20 BDM Block Diagram...............................................................................................5-65
5-21 BDM Command Execution Flowchart.................................................................5-68
5-22 Debug Serial I/O Block Diagram..........................................................................5-70
5-23 Serial Interface Timing Diagram..........................................................................5-71
5-24 BKPT Timing for Single Bus Cycle......................................................................5-72
5-25 BKPT Timing for Forcing BDM.............................................................................5-72
5-26 BKPT/DSCLK Logic Diagram..............................................................................5-72
5-27 Command-Sequence Diagram............................................................................5-75
5-28 Functional Model of Instruction Pipeline............................................................5-87
5-29 Instruction Pipeline Timing Diagram...................................................................5-88
5-30 Block Diagram of Independent Resources........................................................5-90
5-31 Simultaneous Instruction Execution....................................................................5-91
5-32 Attributed Instruction Times...................................................................................5-92
5-33 Example 1—Instruction Stream...........................................................................5-95
5-34 Example 2—Branch Taken...................................................................................5-95
5-35 Example 2—Branch Not Taken............................................................................5-96
5-36 Example 3—Branch Negative Tail......................................................................5-96
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11/2/95 SECTION 1: OVERVIEW UM Rev 1
MOTOROLA MC68340 USER'S MANUAL xix
LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
6-1 DMA Block Diagram...............................................................................................6-1
6-2 Single-Address Transfers.....................................................................................6-3
6-3 Dual-Address Transfer...........................................................................................6-3
6-4 DMA External Connections to Serial Module....................................................6-6
6-5 Single-Address Read Timing (External Burst)..................................................6-8
6-6 Single-Address Read Timing (Cycle Steal).......................................................6-9
6-7 Single-Address Write Timing (External Burst)...................................................6-10
6-8 Single-Address Write Timing (Cycle Steal).......................................................6-11
6-9 Dual-Address Read Timing (External Burst—Source Requesting)...............6-13
6-10 Dual-Address Read Timing (Cycle Steal—Source Requesting)...................6-14
6-11 Dual-Address Write Timing (External Burst—Destination Requesting)........6-16
6-12 Dual-Address Write Timing (Cycle Steal—Destination Requesting)............6-17
6-13 Fast Termination Option (Cycle Steal)................................................................6-21
6-14 Fast Termination Option (External Burst—Source Requesting)....................6-22
6-15 DMA Module Programming Model......................................................................6-23
6-16 Packing and Unpacking of Operands.................................................................6-35
7-1 Simplified Block Diagram......................................................................................7-1
7-2 External and Internal Interface Signals..............................................................7-5
7-3 Baud Rate Generator Block Diagram..................................................................7-8
7-4 Transmitter and Receiver Functional Diagram..................................................7-9
7-5 Transmitter Timing Diagram.................................................................................7-10
7-6 Receiver Timing Diagram......................................................................................7-12
7-7 Looping Modes Functional Diagram...................................................................7-15
7-8 Multidrop Mode Timing Diagram.........................................................................7-16
7-9 Serial Module Programming Model....................................................................7-19
7-10 Serial Module Programming Flowchart..............................................................7-41
8-1 Simplified Block Diagram......................................................................................8-1
8-2 Timer Functional Diagram.....................................................................................8-3
8-3 External and Internal Interface Signals..............................................................8-5
8-4 Input Capture/Output Compare Mode.................................................................8-7
8-5 Square-Wave Generator Mode............................................................................8-8
8-6 Variable Duty-Cycle Square-Wave Generator Mode......................................8-10
8-7 Variable-Width Single-Shot Pulse Generator Mode........................................8-11
8-8 Pulse-Width Measurement Mode........................................................................8-12
8-9 Period Measurement Mode..................................................................................8-14
8-10 Event Count Mode..................................................................................................8-15
8-11 Timer Module Programming Model.....................................................................8-18
9-1 Test Access Port Block Diagram..........................................................................9-2
9-2 TAP Controller State Machine..............................................................................9-3
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