ON Semiconductor NCP1239FDR2G User manual

©Semiconductor Components Industries, LLC, 2005
October, 2005 − Rev. 5 1Publication Order Number
NCP1239/D
NCP1239
Low−Standby High
Performance PWM Controller
Housed in SO−16 the NCP1239 represents a major leap toward
ultra−compact Switch Mode Power Supplies specifically tailored for
medium to high power off−line applications, e.g. notebook adapters.
The NCP1239 offers everything needed to build a rugged and efficient
power supply, including a dedicated event management to drive a
Power Factor Correction (PFC) front−end circuitry. The circuit
disables the front−end PFC stage while still in fault or standby
conditions by interrupting the PFC controller powering for improved
no−load consumption figures. As soon as normal operating mode
recovers, the NCP1239 feeds back the PFC that wakes−up.
When power demand is low, the IC automatically enters the
so−called skip−cycle mode and provides excellent efficiency at light
loads. Because this occurs at a user adjustable low peak current, no
acoustic noise takes place.
Features
•Current−Mode Operation with Internal Ramp Compensation
•Internal High−Voltage Current Source for loss−less Startup
•Adjustable Skip−Cycle Capability
•Selectable Soft−Start Period
•Internal Frequency Dithering for Improved EMI Signature
•Go−to−Standby Signal for PFC Front−Stage
•Large VCC Operation from 12.2 V to 36 V
•500 mV Overcurrent Limit
•500 mA/−800 mA Peak Current Capability
•5 V/10 mA Pinned−out Reference Voltage
•Adjustable Switching Frequency up to 250 kHz.
•Overload Protection Independent of the Auxiliary VCC
•Adjustable Over Power Compensation (NCP1239F)
•Programmable Maximum Duty Cycle (NCP1239V)
•Pb−Free Packages are Available*
Typical Applications
•High Power AC/DC Adapters for Notebooks etc.
•Offline Battery Chargers
•Telecom and PC Power Supplies
•Flyback Applications (NCP1239F) and Forward Applications
(NCP1239V)
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
NCP1239xD = Device Code
x = F or V
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
MARKING DIAGRAM
16
SO−16
FD or VD SUFFIX
CASE 751B
NCP1239xDG
AWLYWW
1
1
16
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PIN CONNECTIONS
Over Power
Limit
FB
116
CSSkip Adjust GNDSS/Timer DrvBrown−out VCC
Rt NCFault Detect NCREF5V HVGTS
Max Duty−
Cycle
FB
116
CSSkip Adjust GNDSS/Timer DrvBrown−out VCC
Rt NCFault Detect NCREF5V HVGTS
NCP1239F
NCP1239V
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION

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Figure 1. NCP1239F Typical Application Example
Cbulk
Vbulk
+
to PFC_VCC
BO
1 16
2
3
4
15
14
13
NCP1239F
OVP +
GND
Vout
Rbo1
GND
Rcomp
Cbo
5 12
6
7
8
11
10
9
Rramp
VCC
REF5V
+
REF5V (5V/10mA)
Css
Rbo2
Rt
NTC
Thermistor
Figure 2. NCP1239V Typical Application Example
Cbulk
Vbulk
+
to PFC_VCC
BO
1 16
2
3
4
15
14
13
NCP1239V
OVP Vout
Rbo1
GND
Rdmax
Cbo
5 12
6
7
8
11
10
9
Rramp
VCC
REF5V
+
REF5V (5V/10mA)
Css
Rbo2
Rt
NTC
Thermistor
D3
D4 +
GND
L2

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MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage VCC 36 V
Pins 1 to 10 (except Vref Pin) Maximum Voltage −0.3, +10 V
Maximum Voltage on Pin 16 (HV) 500 V
Thermal Resistance, Junction−to−Air, SOIC Version RJA 145 °C/W
Maximum Junction Temperature TJMAX 150 °C
Storage Temperature Range −60 to +150 °C
ESD Capability, HBM Model (All Pins except HV) 2 kV
ESD Capability Machine Model (All Pins except VCC)
Machine Model (VCC Pin) 200 160 V
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
ELECTRICAL CHARACTERISTICS (For typical values TJ= 25°C, for min/max values TJ= 0°C to +125°C, Vpin16 = 48 V,
VCC = 20 V unless otherwise noted.)
Symbol Rating Pin Min Typ Max Unit
Supply Section
VCCON Turn−on Threshold Level, VCC Going up 13 15.5 16.4 17.5 V
VCCOFF Minimum Operating Voltage after Turn−on 13 10.5 11.2 12.2 V
HYST1 Difference (VCCON − VCCOFF) 13 4.5 5.1 − V
VCCLATCH VCC Decreasing Level at which the Latch−off Phase ends 13 6.5 6.9 7.2 V
VCCRESET VCC Level at which the Internal Logic gets reset 13 − 4.0 − V
ICC1 Internal IC Consumption, no output load on Pin 12 (@IRt = 20 A)
NCP1239F
NCP1239V
13 −
−2.1 2.6 3.0 4.0
mA
ICC2a Internal IC Consumption, 1 nF output load on Pin 12
NCP1239F (65 kHz)
NCP1239V (118 kHz)
13 −
−3.1 4.2 3.8 6.5
mA
ICC2b Internal IC Consumption, 1 nF output load on Pin 12
NCP1239F (100 kHz)
NCP1239V (182 kHz)
13 −
−3.9 5.5 5.0 8.5
mA
ICC2c Internal IC Consumption, 1 nF output load on Pin 12
NCP1239F (130 kHz)
NCP1239V (236 kHz)
13 −
−4.6 6.7 5.9 9.6
mA
ICC3 Internal IC Consumption, latchoff phase
(NCP1239F and NCP1239V) 13 − 0.40 0.75 mA
Internal Startup Current Source
IC1_hv High−Voltage Current Source (sunk by Pin 16), VCC = 10 V 16 2.0 4.0 5.3 mA
IC1_VCC Startup Charge Current flowing out of the VCC Pin, VCC=10 V 13 1.8 3.6 4.5 mA
IC2 High−Voltage Current Source, VCC = 0 16 − 4.2 − mA
5 V Reference Voltage (REF5V)
REF5V Reference Voltage
@ No load on Pin 2
@ Ipin2 = 5 mA
24.7
4.6 5.0 4.9 5.2 5.1
V
Iref Current Capability 2 5.0 10 − mA

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ELECTRICAL CHARACTERISTICS (For typical values TJ= 25°C, for min/max values TJ= 0°C to +125°C, Vpin16 = 48 V,
VCC = 20 V unless otherwise noted.)
Symbol UnitMaxTypMinPinRating
Drive Output
Vcl Output Voltage Positive Clamp 12 11.5 13.6 16 V
Trise Output Voltage Rise−Time @ CL = 1 nF, 10−90% of output signal 12 − 40 − ns
Tfall Output Voltage Fall−Time @ CL = 1 nF, 10−90% of output signal 12 − 25 − ns
Vsource High State Voltage Drop @ Ipin12 = 3 mA and VCC = 12 V 12 − 2.5 3.3 V
Isource Source Current Capability (@ Vpin12 = 0 V) 12 − 500 − mA
ROL Sink Resistance @ Vpin12 =1 V 12 − 3.8 7.5 
Isink Sink Current Capability (@ Vpin12 = 10 V) 12 − 800 − mA
Oscillator
fsw Recommended Switching Frequency Range 12 25 − 250 kHz
Vosc Pin 4 Voltage @ Rt = 100 k4 − 1.6 − V
Kosc Product (Switching Frequency times the Rt Pin 4 resistance) (Note 1)
@ 65 kHz and 130 kHz (NCP1239F)
@ 118 kHz and 236 kHz (NCP1239V) 6050 11000 6500 11800 6950 12600
kHz*k
fsw Internal Modulation Swing, in percentage of fsw −±3.5 − %
Dmax Maximum Duty−Cycle 75.5 80.0 83.0 %
Current Limitation
ILimit Maximum Internal Set−Point 10 0.84 0.90 0.95 V
TDEL_CS Propagation Delay from Vpin10 > ILimit to gate turned off
(Pin 12 loaded by 1 nF) 10 − 130 220 ns
TLEB−65kHz Leading Edge Blanking Duration (Pins 9 and 10) @ 65 kHz
(NCP1239F) 9, 10 − 420 − ns
TLEB−130kHz Leading Edge Blanking Duration (Pins 9 and 10) @ 130 kHz
(NCP1239F) 9, 10 − 230 − ns
TLEB−118kHz Leading Edge Blanking Duration (Pin 10) @ 118 kHz (NCP1239V) 10 − 320 − ns
TLEB−236kHz Leading Edge Blanking Duration (Pin 10) @ 236 kHz (NCP1239V) 10 − 170 − ns
Over Power Limit (NCP1239F)
Iocp Internal Current Source of the Over Power Limit Pin
@ 1 V on Pin 5 and Vpin9 = 0.5 V
@ 2 V on Pin 5 and Vpin9 = 0.5 V
960
120 80 160 100 185
A
Vopl Over Power Limitation Threshold
@ TJ= 25°C
@ TJ= 0°C to 125°C
90.48
0.47 0.50 0.50 0.52 0.52
V
TDEL_OCP Propagation Delay from Vpin9 > Vopl to gate turned off
(Pin 12 loaded by 1 nF) 9 − 130 220 ns
Maximum Duty−Cycle (Dmax) Control (NCP1239V)
IDmax Pin 9 Current Source @ Vpin9 = 1.0 V and Vpin9 = 2.0 V 9 46 55 63 A
Dmax Maximum Duty Cycle @ 118 kHz and Vpin9 = 1.0 V 9 20 24 29 %
KDmax Dmax Coefficient @ 118 kHz and Vpin9 = 1.0 V (Note 2) 9 1.10 1.30 1.53 %/k
1. The nominal switching frequency fsw equals: fsw = KOSC/Rt. The implemented jittering makes the switching frequency continuously vary
around this nominal value ($3.5% variation).
2. KDmax is the proportionality coefficient that links the maximum duty−cycle to the Pin 9 resistor: Dmax = KDmax*Rpin9. KDmaxis defined in
the “Maximum Duty−Cycle Limitation” section of the operating description.

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ELECTRICAL CHARACTERISTICS (For typical values TJ= 25°C, for min/max values TJ= 0°C to +125°C, Vpin16 = 48 V,
VCC = 20 V unless otherwise noted.)
Symbol UnitMaxTypMinPinRating
Soft−Start and Timer
Ich Soft−Start or Jittering charge current @ Vpin6 = 2.4 V 6 60 95 110 A
Idisch Jittering Discharge Current @ Vpin6 = 2.4 V 6 77 107 137 A
Vjitter Jittering Saw−Tooth Lower Threshold 6 1.67 1.80 1.89 V
VjitterHJittering Saw−Tooth Upper Threshold 6 2.85 3.00 3.20 V
VtimerLTimer Peak Threshold 6 4.0 4.3 4.6 V
ItimerC Timer Charge Current @ Vpin6 = 3.5 V and Pin 8 open 6 3.9 5.2 6.4 A
ItimerD Timer Discharge Current @ Vpin6 = 3.5 V and Pin 8 open 6 − 400 − A
Feedback Section
Rup Internal Pullup Resistor 8 − 20 − k
Ifb Source Current @ Vpin8 = 0.5 V 8 − 200 − A
Iratio Pin 8 to current Setpoint division ratio − − 3.0 − −
Internal Ramp Compensation
Rramp Internal Resistor 10 − 32 − k
Vramp Internal Saw−Tooth Amplitude 10 − 3.2 − V
Skipping Mode and Standby Management
Rgts Pin 1 output impedance in standby state
(Pin 8 grounded, Vpin6 > 4.5 V) @ VCC = 12.5 V 1 4.0 8.0 18 k
Igts Sink Current Source in Normal Mode
@ Vpin8 = 2 V, Pin 7 open @ VCC − Vpin1=0.7 V 1 0.6 1.0 − mA
FB−skip Default Feedback Level for Skip−Cycle Operation and Standby
Detection 7 380 430 480 mV
FB_stby−out Default Feedback Level to Leave Standby 7 650 740 810 mV
Vstby−out/Vskip Ratio leave standby Setpoint to skip−cycle Setpoint 1.5 1.7 1.9 −
Rpin7 Internal Pin 7 Impedance 7 − 110 −k
Pin 7 to Skipping Setpoint ratio − 3.0 − −
Brown−Out Detection
BOthH Brown−Out Detection Upper Threshold 5 0.45 0.50 0.55 V
BOthL Brown−Out Detection Low Threshold 5 0.20 0.24 0.28 V
BOhyst Brown−Out Hysteresis 5 0.20 0.26 0.30 V
Protections
TSD Thermal Shutdown:
Thermal Shutdown Threshold
Hysteresis 140 30
°C
Vfault Fault Detection Threshold 3 2.2 2.4 2.6 V
ORDERING INFORMATION
Device Package Shipping†
NCP1239FDR2 SOIC−16 2500 / Tape & Reel
NCP1239FDR2G SOIC−16
(Pb−Free) 2500 / Tape & Reel
NCP1239VDR2 SOIC−16 2500 / Tape & Reel
NCP1239VDR2G SOIC−16
(Pb−Free) 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

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PIN FUNCTION DESCRIPTION
Pin No. Pin Name Function Pin Description
1 GTS Shuts the PFC down in
standby The standby detection block changes Pin 1 state in accordance to the mode
(standby or normal mode). Pin1 is designed to drive an external pnp transistor that
connects or disconnects the NCP1239’s VCC to the PFC’s.
2 REF5V A 5V reference voltage This pin helps to internally bias the controller but can also be used to power
surrounding logic gates for any purposes. The typical output current is 10 mA. This
voltage source is disabled during the circuit startup and latched−off phases. A
100 nF filtering capacitor must be placed between Pin 2 and ground.
3Fault Detect Enables to permanently
shutdown the part If the Pin 3 voltage exceeds 2.4 V, the circuit is permanently shut down. This pin
can be used to monitor the voltage across a thermistor in order to protect the
application from excessive heating and/or to detect an overvoltage condition.
4 Rt Timing resistor Pin 4 resistor allows a precise frequency programming. The circuit is optimized to
operate between 50 kHz and 150 kHz (NCP1239F) and between 100 kHz and
250 kHz (NCP1239V).
5 Brown−Out Brown−Out This pin receives a portion of the bulk capacitor to authorize operation above a
certain level of mains only. It also serves to elaborate an offset voltage on Pin 9
used for Over Power Compensation.
6SS/Timer Performs soft−start and
fault timeout During Power on and fault conditions, the capacitor connected to this pin ensures a
soft−start period. When a fault is detected, this pin is internally brought high by a
current source. If 4.3 V are reached, the fault is confirmed and the circuit enters an
auto−recovery burst mode, otherwise the pin goes back to a lower value and
oscillates to perform frequency jittering.
7Skip Adjust Adjust skip level By adjusting the skip−cycle level, it is possible to fight against noisy transformers
and modify the standby detection thresholds. Keep Pin 7 open to operate with the
default levels (skip threshold setpoint: 140 mV, normal mode recovery setpoint:
250 mV).
8 FB Feedback signal An opto−coupler collector pulls this pin low to regulate
9Over Power
Limit
(NCP1239F)
Enables a precise peak
current clamp and then an
accurate Over Power
Detection
This pin delivers a current proportional to Vpin5, an image of the high voltage rail.
Inserting a resistor between Pin 9 and the current sense resistor, an offset
proportional to the input voltage is built. Such offset compensates the circuit and
power switch propagation delays for an accurate power limitation in the whole input
voltage range.
9Max Duty−
Cycle
(NCP1239V)
Enables to precisely
clamp the maximum
duty−cycle.
This terminal sources a constant current. Connect a resistor between Pin 9 and
Ground to select the maximum duty−cycle.
10 CS The current sense input This pin receives the primary current information via a sense element. By inserting
a resistor in series with this pin, it becomes possible to introduce ramp
compensation.
11 Ground The IC ground −
12 Drv Drives the MOSFET By offering up to +500 mA/−800 mA peak, this pin lets you drive large Qg
MOSFET’s. It is clamped to 16 V maximum not to exceed the maximum
gate−source voltage of most power MOSFET’s.
13 VCC Supplies the controller This pin accepts up to 36 V from an auxiliary winding.
14 NC − Creepage distance.
15 NC − Creepage distance.
16 HV The high−voltage startup This pin connects to the bulk capacitor to generate the startup current.

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Figure 3. NCP1239F Internal Circuit Architecture
−
+
7
S
R
Q
Q
Vcc < 4V
450mV
5V
0.5V / 0.25V
Rt
BO
REF5V
SS / timer
PFC_Vcc
Fault
detect
Skip
adjust
Vdd
/ 3
to Skip
20k
0.9V
Oscillator
GND
32k
CS
Drv
Vcc
Vdd Regul
UVLOs
Latch
Reset
Error flag
HV
Over Power
Limit
Vdd
2.5V
Vdd
2.5V
100k
Fault
Vdd Vdd
Soft−Start
and timer
management
Stby_detect
Error_Flag
Stby
OVL
OVL
Vcc<7V
stdwn
Vstop
PWM Latch
Output
Buffer
BO_out
Jittering
Modulation
“Jittered”
Reference
Jittering
Modulation
CLK
CLK
0.5V
BO_in
Soft−Start
Ipk limit
Soft−Start
Ipk limit
Internal
Thermal
Shutdown
TSD
FB
Divider by 2
+
−
Skip
Skip
FB
Startup Phase
(Vcc<VccOFF)
1mA
Vcc
10k
Vstop
regOUT
Stby_detect
25r
15r
S
R
Q
Q
FB<Vpin1 => Skip high
FB>1.6*Vpin1 =>Stby_detect RESET
pfcOFF
pfcON
UVLO
14V
clamp
pfcON
OUTon
Ramp
Compensation 3.2V
BO_in
75 mA/V x Vpin5
LEB
LEB
+
−
+
16
15
14
13
−
+
3
1
S
R
Q
Q
6
2+
12
11
10
5
+
S
R
Q
Q
9
+
−
+
−
+
−
+
8
4

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Figure 4. NCP1239V Internal Circuit Architecture
−
+
7
S
R
Q
Q
Vcc < 4V
450mV
5V
0.5V / 0.25V
Rt
BO
REF5V
SS / timer
PFC_Vcc
Fault
detect
Skip
adjust
Vdd
/ 3
to Skip
20k
0.9V
Oscillator
GND
32k
CS
Drv
Vcc
Vdd Regul
UVLOs
Latch
Reset
Error flag
HV
Dmax
Vdd
2.5V Vdd
2.5V
100k
Fault
Vdd Vdd
Soft−Start
and timer
management
Stby_detect
Error_Flag
Stby
OVL
OVL
Vcc<7V
stdwn
Vstop
PWM Latch
Output
Buffer
BO_out
Jittering
Modulation
“Jittered”
Reference
Jittering
Modulation
CLK
CLK
BO_in
Soft−Start
Ipk limit
Soft−Start
Ipk limit
Internal
Thermal
Shutdown
TSD
FB
Divider by 2
+
−
Skip
Skip
FB
Startup Phase
(Vcc<VccOFF)
1mA
Vcc
10k
Vstop
regOUT
Stby_detect
25r
15r
S
R
Q
Q
FB<Vpin1 => Skip high
FB>1.6*Vpin1 =>Stby_detect RESET
pfcOFF
pfcON
UVLO
14V
clamp
pfcON
OUTon
Ramp
Compensation 3.2V
Idmax
LEB
+
−
+
16
15
14
13
−
+
3
1
S
R
Q
Q
6
2+
12
11
10
5
+
S
R
Q
Q
9
+
−
−
+
−
+
8
4OSC
OSC

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Figure 5. High Voltage Current Source
vs. Temperature @ VCC = 10 V Figure 6. Startup Current Sourced by VCC Pin vs. Temperature @ VCC = 10 V
TEMPERATURE (°C)
100755025−25
IC1_VCC (mA)
TEMPERATURE (°C)
125100755025
6.0
IC1_HV, (mA)
5.0
−25 0
4.0
3.0
2.0
1.0
0
5.0 4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 7. High Voltage Current Source
vs. Temperature @ VCC = 0 V
TEMPERATURE (°C)
125100755025−25
I
C2
(mA)
6.0
0
5.0
4.0
3.0
2.0
1.0
0
Figure 8. High Voltage Pin Leakage Current
vs. Temperature
12
5
TEMPERATURE (°C)
12
5
100755025
0
10
20
30
Pin16 Leakage Current (A)
40
50
60
0
Figure 9. VCC Startup Threshold
vs. Temperature
TEMPERATURE (°C)
125100755025
V
CCON
(V)
16.7
0
16.6
16.5
16.4
16.3
16.2
16.1
16.0
15.9
Figure 10. VCC Turn−Off Threshold
vs. Temperature
11.5
TEMPERATURE (°C)
1
25
100755025−25
VCCOFF (V)
0
11.4
11.3
11.2
11.1
11.0
10.9
10.8
0

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TEMPERATURE (°C)
125100755025−25
6.75
6.80
6.85
6.90
VCCLATCH (V)
6.95
0
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 11. VCC Latched−Off vs. Temperature
TEMPERATURE (°C)
12
5
100755025−25
1.6
2.2
2.8
ICC1 (mA)
Figure 12. No Load Circuit Consumption
vs. Temperature
1.8
2.0
2.4
2.6
0
TEMPERATURE (°C)
125100755025−25
2.0
2.5
3.0
3.5
4.0
I
CC2
(mA)
Figure 13. NCP1239F Circuit Consumption
(1 nF on driver Pin 12) vs. Temperature
130 kHz
4.5
5.0
100 kHz
65 kHz
0
TEMPERATURE (°C)
12
5
100755025−25
ICC2 (mA)
Figure 14. NCP1239V Circuit Consumption
(1 nF on driver Pin 12) vs. Temperature
7.3
200 kHz
130 kHz
0
6.9
6.5
6.1
5.7
5.3
4.9
4.5
4.1
3.7
3.3
260 kHz
TEMPERATURE (°C)
125100755025−25
I
CC3
(mA)
Figure 15. Latched−Off Mode Consumption
vs. Temperature
4.70
4.85
4.90
4.95
TEMPERATURE (°C)
12
5
100755025−25
REF5V (V)
4.80
0 mA
5 mA
10 mA
0.6
5.00
5.05
0
4.75
0
0.5
0.4
0.3
0.2
0.1
0
Figure 16. REF5V Voltage Source
vs. Temperature

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TEMPERATURE (°C)
125100755025−25
2.0
3.0
8.0
Vdrop (V)
TEMPERATURE (°C)
12
5
100755025−25
Rsink ()
0
5.0
6.0
4.0
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 17. Driver High State Voltage Drop
vs. Temperature Figure 18. Driver Sink Resistance vs. Temperature
3.0
00
12300
TEMPERATURE (°C)
TEMPERATURE (°C)
12
5
100755025−25
79
81
83
125100755025−25
6700
Dmax (%)
Kosc (kHz*k)
130 kHz
77
78
80
82
Figure 19. Driver Voltage Clamp vs. Temperature Figure 20. Maximum Duty Cycle vs. Temperatur
e
(NCP1239F)
Figure 21. Oscillator Kosc Parameter vs. Temperature
(K
osc
= fsw * R
pin4
) (NCP1239F)
TEMPERATURE (°C)
125100755025−25
16
Vcl CLAMP VOLTAGE (V)
65 kHz
0 0
0
TEMPERATURE (°C)
12
5
100755025
Kosc (kHz*k)
Kosc1 @ 130 kHz
Figure 22. Oscillator Kosc Parameter vs. Temperature
(K
osc
= fsw * R
pin4
) (NCP1239V)
Kosc2 @ 260 kHz
−25
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
7.0
1.0
15
14
13
12
10
11
10
6650
6600
6550
6500
6450
6400
12150
12000
11850
11700
11550
11400
11250 0

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TEMPERATURE (°C)
12
5
100755025−25
410
415
420
430
435
FBskip (mV) 425
445
450
440
0
125
40
60
80
120
140
180
TEMPERATURE (°C)
100755025−25
I
ocp
(

A)
100
160
BO = 2 V
BO = 1 V
0
TYPICAL PERFORMANCE CHARACTERISTICS
TEMPERATURE (°C)
1
25
100755025−25
0.508
Vopl (V)
Figure 23. Pin 9 Current vs. Temperature
(@ Vpin9 = 0.5 V) (NCP1239F) Figure 24. Over Power Limitation Threshold vs
.
Temperature (NCP1239F)
0
0.506
0.504
0.502
0.500
0.498
0.496
0.494
0.492
TEMPERATURE (°C)
12
5
100755025−25
BO_H (V)
0.510
TEMPERATURE (°C)
125100755025−25
FB
stby−out
(mV)
780
00
TEMPERATURE (°C)
125100755025−25
0.920
ILimit (V)
0
Figure 25. Maximum Current Setpoint vs.
Temperature Figure 26. Default Feedback Threshold for Standby Detection vs. Temperature
Figure 27. Default Feedback Level for Normal
Operation Recovery Figure 28. Brown−Out Upper Threshold vs. Temperature
0.915
0.910
0.905
0.900
0.895
0.890
0.890
0.885
0.880
770
760
750
740
730
720
710
700
0.505
0.500
0.495
0.490
0.485
0.480

NCP1239
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TYPICAL PERFORMANCE CHARACTERISTICS
TEMPERATURE (°C)
125100755025−25
0.245
BO_L (V)
0
TEMPERATURE (°C)
12
5
100755025−25
2.51
Vfault (V)
0
Figure 29. Brown−Out Low Threshold vs.
Temperature Figure 30. Fault Detect Threshold vs. Temperature
TEMPERATURE (°C)
125100755025
Dmax (%)
24.5
0
Figure 31. Maximum Duty−Cycle vs.
Temperature @ V
pin9
= 1 V (NCP1239V) Figure 32. Kdmax Coefficient vs. Temperature @ V
pin9
= 1 V (NCP1239V)
TEMPERATURE (°C)
12
5
100755025
1.35
Kdmax (%/k)
0
1.33
1.31
1.29
1.27
1.26
0.244
0.243
0.242
0.241
0.240
0.239
0.238
0.237
0.236
0.235
2.49
2.47
2.45
2.43
2.41
2.39
2.37
2.35
24.3
24.1
23.9
23.7
23.5

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14
Figure 33. Fault Management
10ms* Jittering
100ms*
fmax fmin
0.9 V
Error flag
16.4V
11.2V
Fb is ok Fault occurs here
6.9V
OVL signal
(Over−Load)
DRV
Vcc
Reset at UVLO
Fault not confirmed
PFC off PFC on
1.8V
3.0V
4.3V
PFC off
100ms*
Fault confirmed New Startup
attempt
SS / timer pin
0.9 V
Error flag 0.9 V
Error flag
Fault Management
*This time is programmed by the Pin 6 capacitor. Cpin6 = 390 nF nearly sets the following intervals:
− Soft−Start Time (Tss):7.5 ms
− Jittering Period (Tjittering): 10 ms
− Fault Detection Delay (Tdelay): 100 ms
More generally, the times approximately depend on Cpin6 as follows:
−T
ss = 7.5 ms * Cpin6 / 390 nF
−T
jittering =10 ms * Cpin6 / 390 nF
−T
delay =100 ms * Cpin6 / 390 nF

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Figure 34. Standby Detection
Jittering 10ms*
Vpin6
(SS/timer)
Fb is ok
Drv
FB
PFC running
Standby is entered Standby is left
PFC is down
Skip activity
Standby is not confirmed Standby is confirmed,
No delay
Stby_detect latch is armed
Stby_detect latch is reset
100ms* 100ms*
delay
FB−skip (Vpin7)
FB−stby−out (1.7*Vpin7)
4.3V
3.0V
1.8V
Bunches of pulses
Standby Detection
*This time is programmed by the Pin 6 capacitor. Cpin6 = 390 nF nearly sets the following intervals:
− Soft−Start Time (Tss):7.5 ms
− Jittering Period (Tjittering): 10 ms
− Fault Detection Delay (Tdelay): 100 ms
More generally, the times approximately depend on Cpin6 as follows:
−T
ss = 7.5 ms * Cpin6 / 390 nF
−T
jittering =10 ms * Cpin6 / 390 nF
−T
delay =100 ms * Cpin6 / 390 nF

NCP1239
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16
APPLICATION INFORMATION
The NCP1239 includes all necessary features to help
building a rugged and safe switch−mode power supply. The
following details the major benefits brought by
implementing the NCP1239 controller:
Current−mode operation with internal ramp
compensation: implementing peak current mode control,
the NCP1239 offers an internal ramp compensation signal
that can easily be summed up to the sensed current.
Subharmonic oscillations can thus be fought via the
inclusion of a simple resistor,
500 mV Current Sense threshold for Over Power Limit
(NCP1239F): the NCP1239 operating in current mode, the
circuit Pin 10 monitors the current to modulate its level
according to the power demand. Due to the ramp
compensation, one must generally note that the Pin 10
voltage is not the exact image of the inductor current. A
precise current limitation being essential, the NCP1239
features a separate current sense pin (Pin 9) for an accurate
overcurrent detection. The low threshold of this protection
(500 mV) avoids excessive losses in the current sense
resistor and improves the efficiency. In addition, Pin 9
sources a current that proportional to the high−voltage rail,
compensates the current−sense and turn off delays at high
line. A resistor inserted between Pin 9 and the sensing
resistor offsets the Pin 9 current−sense information to build
a precise overload protection, independent of the mains
input.
Large VCC operation: the NCP1239 offers an extended
VCC range up to 36 V, bringing greater flexibility in Flyback
or Forward applications.
Internal high−voltage startup switch: reaching low
levels of standby power represents a difficult exercise when
the controller requires an external, lossy, resistor connected
to the bulk capacitor. Due to an internal logic, the controller
disables the high−voltage current source after startup which
no longer hampers the consumption in no−load situations.
Skip−cyclecapability: a continuous flow of pulses is not
compatible with no−load standby power requirements.
Slicing the switching pattern in bunch of pulses drastically
reduces overall losses but can, in certain cases, bring
acoustic noise in the transformer. Due to a skip operation
taking place at low peak currents only, no mechanical noise
appears in the transformer. Furthermore, the skip threshold
is made programmable to allow the best trade−off between
noise and efficiency.
Standby Detect/Shutdown of the PFC front−stage: The
NCP1239 incorporates an internal logic that is able to detect
a standby situation. Pin1 state changes in accordance to the
detected mode (standby or normal mode). Simply connect a
pnp transistor between the NCP1239 VCC and the PFC
controller one and drive it using Pin 1, to enable the PFC
stage in normal mode and disable it in standby.
Soft−Start: the capacitor connected to Pin 6 provides a
soft−start sequence that precludes the main power switch
from being stressed upon startup. The same voltage is also
used to perform frequency jittering and timing for the fault
condition detection.
Major Fault Detection: the circuit detects when Pin 3
voltage exceeds 2.4 V. When this occurs, the NCP1239
considers that a major fault is present and as a consequence,
the circuit gets permanently latched−off. In this mode, the
circuit needs the VCC to go down below 4.0 V to reset, for
instance when the user un−plugs the SMPS. This capability
is mainly intended to detect an overvoltage condition or/and
an over−heating of the application that would be sensed by
a thermistor.
Brown−outdetection: by monitoring the level on Pin 5
during normal operation, the controller protects the SMPS
against low mains conditions. When the Pin 5 voltage falls
below 250 mV, the controllers stops pulsing until this level
goes back to 500 mV to prevent any instability.
Short−circuit protection: short−circuit and especially
overload protections are difficult to implement when a
strong leakage inductance affects the transformer (the
auxiliary winding level does not properly collapse…). Here,
every time the feedback pin is at its maximum (higher than
5.0 V practically), an error flag is asserted and the circuit
activates a timer that is programmed by the Pin 6 capacitor.
If Pin 6 reaches 4.3 V while the error flag is still present, the
controller stops the pulses and goes into a latch−off phase,
operating in a low−frequency burst−mode. As soon as the
fault disappears, the SMPS resumes its operation. The
latch−off phase can also be initiated, more classically, when
VCC drops below UVLO (11.2 V typical).
Adjustable frequency and Internal dithering for
improved EMI signature: Pin 4 offers a means to precisely
adjust the switching frequency through a simple resistor to
ground. Frequency operation is allowed up to 250 kHz. By
modulating the internal switching frequency with the Pin 6
saw−tooth (100 Hz with 390 nF), natural energy spread
appears and softens the controller’s EMI signature.
5.0 V reference voltage: a 5.0 V regulator is provided to
help biasing any external circuitry in the vicinity of the
controller. This reference voltage can typically supply up to
10 mA.

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17
Startup Sequence
When the power supply is first connected to the mains
outlet, the internal current source (typically 3.6 mA) is
biased and charges up the VCC capacitor. When the voltage
on this VCC capacitor reaches the VCCON level (typically
16.4 V), the current source turns off and no longer wastes
any power. At this time, the energy stored by the VCC
capacitor serves to supply the controller and the auxiliary
supply is supposed to take over before VCC collapses below
VCCOFF. Figure 35 shows the internal arrangement of this
structure:
Figure 35.
The current source brings VCC above 16.4 V and then turns o
ff
16
13
10
3.6 mA/0
CVCC Aux
HV
16.4 V /
11.2 V −
+
As soon as VCC reaches 16.4 V, driving pulses are
delivered on Pin 12 and the auxiliary winding grows up the
VCC pin. Because the output voltage is below the target (the
SMPS is starting up), the feedback pin is at its maximum
voltage. A resistor divider outputs the third of the feedback
voltage that forms the current setpoint. This setpoint is
clamped and the limitation level slowly increases until it
reaches 0.9V during the soft start time. In nominal operation,
the setpoint clamp keeps equal to 0.9 V (refer to Figure 36).
As soon as the feedback voltage is high enough to activate
the 0.9 V setpoint clamp (during the startup period but also
anytime an overload occurs), an internal error flag is
asserted, testifying that the system is pushed to the
maximum power. At that moment, a 100 ms time period
(typically, with Cpin6=390 nF that also corresponds to 7.5 ms
soft −start) starts while a logic block observes this error flag.
If the error flag keeps asserted all along the 100ms period,
then the controller assumes that the power supply really
undergoes a fault condition and immediately stops all pulses
to enter a safe burst operation. The 100 ms timer enables to
distinguish a startup phase (shorter than 100 ms) from an
overload condition. If the error flag is released before the
100 ms period has elapsed, the controller concludes that no
error is present and resets the timer to use it for other
purposes (e.g. frequency dithering).
Figure 36. Current Control
Pin 10 monitors the power switch current and compares it to the current setpoint (one third of the feedback voltage). The
current setpoint is limited by the soft−start during the power−on sequence and permanently clamped to 0.9 V In the
NCP1239F, a second pin (Pin 9) monitors the current to clamp the power.
−
+
CLK
Current Sense
Comparator
8
10
Current Sense
Over Power
Comparator
Feedback
Rramp
Rsense
Vdd
0.9 V
Vin
Overcurrents Compensation
to
Standby Management
(Skipping, GTS)
S
R
Q
Q
LEB
PWM Latch
+
−
Rcomp
+
9
Over Power
Limit
500 mV
LEB
Pin 5 (Brown−Out)
/ 3
Ramp Compensation
oscillator
Soft−Start
20k

NCP1239
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18
Figure 37 depicts the VCC evolution during a proper startup sequence, showing the state of the error flag:
*This time is programmed by the Pin 6 capacitor. Cpin6 = 390 nF nearly sets the following intervals:
− Soft−Start Time (Tss):7.5 ms
− Jittering Period (Tjittering): 10 ms
− Fault Detection Delay (Tdelay): 100 ms
More generally, the times approximately depend on Cpin6 as follows:
−T
ss = 7.5 ms * Cpin6 / 390 nF
−T
jittering =10 ms * Cpin6 / 390 nF
−T
delay =100 ms * Cpin6 / 390 nF
Figure 37.
7.5ms*
SS
Ip max
FB
Error
Flag
Timer
Full power
Skip level
VccON
VccOFF
Vcc
Latch−off phase level
Logic reset level
regulation
No error has
been confirmed
User
Powers up!
Feedback loop
reacts...

NCP1239
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19
PFC Startup Sequence
To ensure an adequate startup sequence of both PWM
section and the PFC stage, some logic and timing need to be
included as shown on the internal diagram. The key point
here is the fact that the PFC always starts after the PWM
section. As a result, the SMPS must be designed to cope with
transient universal mains operation. Why this? Because of
the light−to−heavy load transition where a case exists when
the PFC is off, the PWM in standby and the load is suddenly
applied. In this scenario, the PWM section must sustain the
entire transient period that lasts until the PFC re−starts since
it has been deactivated for standby.
The standby detection block generates an internal signal
“pfcON” that controls Pin 1 in accordance to the operation
mode:
− “pfcON” is high in normal mode and a current source
draws 1 mA from Pin 1,
− “pfcON” is low in standby to disable the 1 mA current
source. A 10 kresistor pulls up Pin 1 to VCC.
This configuration makes it ideal to drive a pnp transistor
that connects or disconnects the NCP1239 VCC to the PFC
controller one (refer to Figure 39). The “pfcON” signal is
activated following Figure 38 diagram. Let’s split this
drawing in different time periods to clearly depict signal
assertions:
Power on: during this time, VCC rises up, the VCC
capacitor being charged by the 3.6 mA current source. When
VCC exceeds VCCON (16.4 V typ.), driving pulses are
delivered to the MOSFET in an attempt to crank the power
supply. VCC collapses (because the VCC capacitor alone
delivers the energy) until sufficient auxiliary voltage is built
up in order to take over the startup sequence and thus
self−supply the controller. As long as the output voltage has
not reached its wished value, the controller pushes for the
maximum peak current. During the soft−start (7.5 ms with
390 nF on Pin 6), the maximum permissible current linearly
increases till the maximum peak setpoint is reached, the
internal 0.9 V Zener diode actively clamping the current
amplitude to (0.9 V/Rsense). During this time, the NCP1239
asserts an error flag. A maximum current condition being
observed, the circuit determines if this state results from
either a normal response (startup or a transient period) or a
fault condition. To make the difference, each time the error
flag is asserted, a 100 ms timer starts to count down. If the
error flag keeps asserted for the 100 ms period, there is a
fault and the PWM controller enters a safe, auto−recovery,
burst mode to limit the dissipated heat (see below for more
details). During the Power−on sequence, “pfcON” keeps
low to pullup Pin 1 to VCC until the error flag is down. When
the error flag is down, the power supply has entered
regulation, its auxiliary voltage is stable, then Pin 1 can turn
low (1 mA sink current) to safely allow PFC operation.
Entering Standby: when skip−cycle starts to activate, a
100 ms countdown takes place and the logic observes the
skip activity. If the skip activity is still there at the end of the
100 ms, then standby is confirmed and the NCP1239 pulls
up Pin 1 to VCC to shut down the PFC.
Leaving standby: in this case, as soon as the skip−cycle
activity disappears, the circuit immediately re−activates the
1 mA sinking current source of Pin 1, to enable the PFC:
there is no reaction delay in this situation.
Short−circuitcondition: a short circuit is detected on the
primary side by measuring the time the error flag is asserted.
As explained, if this flag is asserted longer than 100 ms, then
the PWM stops oscillating and enters a safe burst mode. In
this case, Pin 1 is pulled up to VCC and the PFC is shut down.
During the burst, it is not activated (PFC is off) until the fault
goes away and the power supply resumes operation. The
PFC being shut off in short−circuit conditions, it naturally
reduces the main MOSFET stress.
Latch−off mode: if the controller is permanently
latched−off due to a major fault (Pin 3 detection of an OVP
or an excessive external temperature), the PFC is kept off
(Pin 1 being tied to VCC).

NCP1239
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20
*This time is programmed by the Pin 6 capacitor. Cpin6 = 390 nF nearly sets the following intervals:
− Soft−Start Time (Tss):7.5 ms
− Jittering Period (Tjittering): 10 ms
− Fault Detection Delay (Tdelay): 100 ms
More generally, the times approximately depend on Cpin6 as follows:
−T
ss = 7.5 ms * Cpin6 / 390 nF
−T
jittering =10 ms * Cpin6 / 390 nF
−T
delay =100 ms * Cpin6 / 390 nF Figure 38.
Vcc
PWM
Timer
0.9V
flag
PFC
Vcc
regulation
100ms*
16.4V
11.2V
6.9V
100ms* 100ms* 100ms*
7.5ms*
SS
Short−circuit
Stby stby is left
Standby
is confirmed
Nom
Pout
Short−circuit
One Vcc cycle is skipped to
lower the burst mode duty
cycle to typically 5% in
fault conditions.
If the fault had disappeared
the SMPS would recover
normal operation