ON Semiconductor NCS36000 User manual

©Semiconductor Components Industries, LLC, 2015
December, 2015 − Rev. 3 1Publication Order Number:
NCS36000/D
NCS36000
Passive Infrared (PIR)
Detector Controller
The NCS36000 is a fully integrated mixed−signal CMOS device
designed for low−cost passive infrared controlling applications. The
device integrates two low−noise amplifiers and a LDO regulator to
drive the sensor. The output of the amplifiers goes to a window
comparator that uses internal voltage references from the regulator.
The digital control circuit processes the output from the window
comparator and provides the output to the OUT and LED pin.
Features
•3.0 − 5.75 V Operation
•−40 to 85°C
•14 Pin SOIC Package
•Integrated 2−Stage Amplifier
•Internal LDO to Drive Sensor
•Internal Oscillator with External RC
•Single or Dual Pulse Detection
•Direct Drive of LED and OUT
•This is a Pb−Free Device
Typical Applications
•Automatic Lighting (Residential and Commercial)
•Automation of Doors
•Motion Triggered Events (Animal photography)
6VREF LDO &
Voltage References
Amplifier
Circuit Window
Comparator
System
Oscillator
Digital
Control
Circuit
5OP1_P
4OP1_N
3OP1_O
2OP2_N
1OP2_O
7VSS
14VDD
13OSC
2
2
8 OUT
9 LED
10 xLED_EN
12 MODE
Figure 1. Simplified Block Diagram
14
SOIC−14
D SUFFIX
CASE 751A
1
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
PIN CONNECTIONS
(Top View)
www.onsemi.com
NCS36000G
AWLYWW
1
14
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
MARKING
DIAGRAM
1
2
3
4
5
6
7
14
13
12
11
10
9
8
OP2_O
OP2_N
OP1_O
OP1_N
OP1_P
VREF
VSS
VDD
OSC
MODE
NC
xLED_EN
LED
OUT

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2
PIN FUNCTION DESCRIPTION
Pin No. Pin Name Description
1 OP2_O Output of second amplifier
2 OP2_N Inverting input of second amplifier
3 OP1_O Output of first amplifier
4 OP1_N Inverting input of first amplifier
5 OP1_P Non−inverting input of first amplifier
6 VREF Regulated voltage reference to drive sensor
7 VSS Analog ground reference.
8 OUT CMOS output (10 mA Max)
9 LED CMOS output to drive LED (10mA Max)
10 xLED_EN Active low LED enable input
11 NC No Connect
12 MODE Pin used to select pulse count mode
13 OSC External oscillator to control clock frequency
14 VDD Analog power supply
ABSOLUTE MAXIMUM RATINGS
Rating Symbol Value Unit
Input Voltage Range (Note 1) Vin −0.3 to 6.0 V
Output Voltage Range Vout −0.3 to 6.0 V or (Vin + 0.3),
whichever is lower V
Maximum Junction Temperature TJ(max) 140 °C
Storage Temperature Range TSTG −65 to 150 °C
ESD Capability, Human Body Model (Note 2) ESDHBM 2 kV
ESD Capability, Machine Model (Note 2) ESDMM 200 V
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 3) TSLD 260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating: v150 mA per JEDEC standard: JESD78
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
THERMAL CHARACTERISTICS
Rating Symbol Value Unit
Thermal Characteristics, DFN6, 3x3.3 mm (Note 4)
Thermal Resistance, Junction−to−Air (Note 5)
Thermal Reference, Junction−to−Lead2 (Note 5) RqJA
RYJL
Will be Completed once
package and power
consumption is finalized
°C/W
Thermal Characteristics, TSOP−5 (Note 4)
Thermal Resistance, Junction−to−Air (Note 5) RqJA See note above. °C/W
4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
5. Values based on copper area of 645 mm2(or 1 in2) of 1 oz copper thickness and FR4 PCB substrate.

NCS36000
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3
OPERATING RANGES (Note 6)
Rating Symbol Min Typ Max Unit
Analog Power Supply VDD 3.0 5.0 5.75 V
Analog Ground Reference VSS 0.0 0.1 V
Supply Current (Standby, No Loads) IDD 170mA
Digital Inputs (MODE) Vih 0.7 *
VDD VDD VDD +
0.3 V
Vil VSS VDD *
0.28
Digital Output (OUT, LED) Push−Pull Output (10 mA Load) Voh 0.67 *
VDD VDD V
Vol VSS VDD *
0.3
OP1_P (Sensor Input) (Note 7) AMP 1 IN 0.1 VDD −
1.1 V
Ambient Temperature TA−40 85 °C
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
7. Guaranteed By Design (Non−tested parameter).
ELECTRICAL CHARACTERISTICS Vin = 1 V, Cin = 100 nF, Cout = 100 nF, for typical values TA= 25°C; unless otherwise noted.
Parameter Test Conditions Symbol Min Typ Max Unit
LDO Voltage Reference
Output Voltage VDD = 3.0 V to 5.75 V VREF 2.6 2.7 2.8 V
Supply Current VDD = 3.0 V to 5.75V IREF 20 50 mA
Comparator High Trip Level Vh2.413 2.5 2.588 V
Comparator Low Trip Level Vl1.641 1.7 1.760 V
Reference voltage for non−inverting input of
second amplifier Vm2.007 2.1 2.174 V
System Oscillator
Oscillator Frequency VDD = 5.0 V
R3= 220 kW
C2= 100 nF
OSC 62.5 Hz
Window Comparator
Lower Trip Threshold See Vl above
Higher Trip Threshold See Vh above
Differential Amplifiers (Amplifier Circuit)
DC Gain VDD = 5.0 V (Note 8) Av 80 dB
Common−mode Input Range VDD = 5.0 V (Note 8) CMIR 0.1 VDD −
1.1 V
Power Supply Rejection Ratio VDD = 5.0 V (Note 8) PSRR 60 dB
Output Drive Current VDD = 5.0 V (Note 8) Iout1 25 mA
POR
POR Release Voltage VPOR 1.35 2.85 V
8. Guaranteed By Design (Non−tested parameter).

NCS36000
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4
APPLICATIONS INFORMATION
Oscillator
The oscillator uses an external resistor and capacitor to set
the system clock frequency. Multiple clock frequencies can
be selected using different combinations of resistors and
capacitors. Figure 2 shows a simplifier block diagram for
the system oscillator.
+
−
+
−
OSC13
Q
Q
SET
CLR
S
R
14
VDD
Figure 2. Block Diagram of System Oscillator Circuit
LDO Regulator
The LDO regulator provides the reference voltage for the
sensor and all other analog blocks within the system. The
nominal voltage reference for the sensor is 2.7 V ±5%. An
external capacitor is needed on the VREF pin to guarantee
stability of the regulator.
Differential Amplifiers
The two differential amplifiers can be configured as a
bandpass filter to condition the PIR sensor signal for the post
digital signal processing. The cutoff frequencies and
passband gain are set by the external components. See
Figure 5.
10−1 100101
20
30
40
50
60
70
80
Figure 3. Plot Showing Typical Magnitude Response
of Differential Amplifiers When Configured as a
Bandpass Filter
Window Comparator
The window comparator compares the voltage from the
second differential amplifier to two reference voltages from
the LDO regulator. COMP_P triggers if OP2_O is greater
than the Vh voltage and COMP_N triggers if OP2_O is
lower than the Vl voltage. See Figures 4 and 5.
Vh
Vl
Vdd
Vss
Comp_P
Vdd
Vss
Comp_N
OP2_O
Vm
Figure 4. Plot Showing Functionality of Window Comparator for an Analog Input OP2_O

NCS36000
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5
1
+
−
23
+
−
4
5
G
D
VREF LDO6
Sensor dependent
components
Vm
VREF 6
Vm
Vh
Vl
Application dependent
components
+
−
Vl
Vh
OP2_O
+
−
Comp_P
Comp_N
Figure 5. Figure Showing Simplified Block Diagram of Analog Conditioning Stages
Digital Signal Processing Block (all times assume a
62.5 Hz system oscillator frequency)
The digital signaling processing block performs three
major functions.
The first function is that the device toggles LED during the
start−up sequencing at approximately two hertz regardless
of the state of the XLED_EN pin. The startup sequence lasts
for thirty seconds. During that time the OUT pin is held low
regardless of the state of OP2_O.
The second function of the digital signal processing block
is to insure a certain glitch width is seen before OUT is
toggled. The digital signal processing block is synchronous
with the system oscillator frequency and therefore the
deglitch time is related to when the comparators toggle
within the oscillator period. A signal width less than two
clock period is guaranteed to be deglitched as a zero. A
signal width of greater than three clock cycles is guaranteed
to be de−glitched. It should be noted that down−sampling
can occur if sufficient anti−aliasing is not performed at the
input of the circuit (OPI_P) or if noise is injected into the
amplifiers, an example would be a noisy power supply.
The third function of the digital signal processing block is
to recognize different pulse signatures coming from the
window comparator block. The device is equipped with two
pulse recognition routines. Single pulse mode (MODE tied
to VSS) will trigger the OUT pin if either comparator toggles
and the deglitch time is of the appropriate length. (See
Figure 6). Dual pulse mode (MODE tied to VDD) requires
two pulses with each pulse coming from the opposite
comparator to occur within a timeout window of five
seconds or 312 clock cycles (See Figure 7). If the adjacent
pulses occur outside the timeout window then the digital
processing block will restart the pulse recognition routine.
xLED_EN Pin
The xLED_EN pin enables the LED output driver when
motion has been detected. If xLED_EN is tied high the LED
pin will not toggle after motion is detected. If the xLED_EN
is tied low the LED pin will toggle when motion is detected.
During start-up the LED pin will toggle irrespective of how
the xLED_EN pin is tied. (See Figure 6).
Figure 6. Timing Diagram for Single−Pulse Mode Detection
TSP< 3T
CLK
OP 2_O
VH= 2,5V
TSP > 3T
CLK
OUT
120 TCLK
4TCLK
VL= 1,7V
VM= 2,1V

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6
Figure 7. Timing Diagram for Dual−Pulse Mode Detection
OUT
120 TCLK
3TCLK
1TCLK
OP 2_O
VH= 2,5V
VL= 1,7V
VM= 2,1V
TSP< 3T
CLK TSP > 3T
CLK
TDP< 360 T
CLK
TSP > 3T
CLK
LED
OUT
OP2_O
OP2_N
OP1_O
OP1_N
OP1_P
VREF
VSS
xLED_EN
nc
VDD
OSC
MODE
1
2
3
4
5
6
7
14
13
12
11
10
9
8
G
D
Sensor dependent
components
Power Supply /
AC to DC Rectifier
R1
R2
R3 R4
C1
C2
C3
C4
C6 C5
R5
D1
R7
C7
J1 J2
R6
Microcontroller
Figure 8. Typical Application Diagram Using NCS36000
R1 = 10 kWC1 = 33 mFJ1 (Jumper for xLED_EN)
R2 = 560 kWC2 = 10 nF J2 (Jumper for Mode Select)
R3 = 10 kWC3 = 33 mFD1 (LED)
R4 = 560 kWC4 = 10 nF
R5 = 43 kWC5 = 100 nF
R6 = 1 kWC6 = 100 nF
R7 = 220 kWC7 = 100 nF
9. R1, C1, R2, C2, R3, C3, R4, C4 setup bandpass filter characteristics. With components as shown above the passband gain is approximately
70 dB with the 3 dB cutoff frequency of the filter at approximately 700 mHz and 20 Hz.
10.R4 can be replaced by a potentiometer to adjust sensitivity of system. Note dynamically changing R4 will also change the pole location for
the second amplifier.
11.R5 and C5 are sensor dependant components and R6 may need to be adjusted to guarantee the AMP 1 IN parameter outlined within the
Operating Ranges section of this document.
12.R7 and C7 may be adjusted to change the oscillator frequency. R7 may not be smaller than 50 kW.

NCS36000
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7
ORDERING INFORMATION
Device Package Shipping†
NCS36000DG SOIC−14
(Pb−Free) 55 Units / Rail
NCS36000DRG SOIC−14
(Pb−Free) 3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

NCS36000
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8
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE J NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
−B−
G
P7 PL
14 8
7
1
M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
−T−
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
__ __
7.04
14X
0.58
14X
1.52
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
7X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
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copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special,consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
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Phone: 81−3−5817−1050
NCS36000/D
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