On semiconductor Fairchild fan302hl Instruction Manual

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AN-6094

Design Guideline for Flyback Charger Using FAN302HL/UL

1. Introduction

More than half of the external power supplies produced

are used for portable electronics such as laptops, cellular

phones, and MP3 players that require constant output

voltage and current regulation for battery charging. For

applications requiring precise Constant Current (CC)

regulation, current sensing in the secondary side is always

necessary, which results in sensing loss. For power

supply designers faced with stringent energy-efficiency

regulations, output current sensing is a design challenge.

The advanced PWM controller FAN302HL/UL can

alleviate the burden of meeting international energy

efficiency regulations in charger designs. The

FAN302HL/UL family uses a proprietary primary-side

regulation (PSR) technique where the output current is

precisely estimated with only the information in the

primary side of the transformer and controlled with an

internal compensation circuit. This removes the output

current sensing loss and eliminates all external current-

control circuitry, facilitating a higher efficiency power

supply design without incurring additional costs. A

Green-Mode function with an extremely low operating

current (200 µA) in Burst Mode maximizes the light-load

efficiency, enabling conformance to worldwide Standby

Mode efficiency guidelines.

This application note presents practical design

considerations for flyback battery chargers employing the

FAN302HL/UL. It includes instructions for designing the

transformer and output filter, selecting the components,

and implementing Constant Current (CC) / Constant

Voltage (CV) control. The design procedure is verified

through an experimental prototype converter using

FAN302UL. Figure 1 shows a typical application circuit

of a flyback converter using the FAN302HL/UL.

AC Line

DL1

SNB

Bias

TL431

Fuse

DL2

VDD

GATE

GND

FAN302HL/UL

4 5

NC 7

GATE

VS1

VS2

VDD

Bridge

Figure 1. Typical Application Circuit

AN-6094

Rev. 1.0.0 • 9/27/12 2

2. Operation Principle

2-1 Constant-Voltage Regulation Operation

Figure 2 shows the internal PWM control circuit of

FAN302. The constant voltage (CV) regulation is

implemented in the same way as the conventional isolated

power supply, where the output voltage is sensed using

voltage divider and compared with the internal 2.5 V

reference of the shut regulator (KA431) to generate a

compensation signal. The compensation signal is

transferred to the primary side using an opto-coupler and

applied to the PWM comparator (PWM.V) through

attenuator Av to determine the duty cycle.

CC regulation is implemented internally without directly

sensing the output current. The output current estimator

reconstructs output current information (VCCR) using the

transformer primary-side current and diode current

discharge time. VCCR is then compared with a reference

voltage (2.5 V) by an internal error amplifier and generates

a VEA.I signal to determine the duty cycle.

VEA.I and VEA.V are compared with an internal sawtooth

waveform (VSAW) by PWM comparators PWM.I and

PWM.V, respectively, to determine the duty cycle. As seen

in Figure 2, the outputs of two comparators (PWM.I and

PWM.V) are combined with the OR gate and used as a

reset signal of flip-flop to determine the MOSFET turn-off

instant. The lower signal, VEA.V and VEA.I, determines the

duty cycle, as shown in Figure 3. During CV regulation,

VEA.V determines the duty cycle while VEA.I is saturated to

HIGH. During CC regulation, VEA.I determines the duty

cycle while VEA.V is saturated to HIGH.

Figure 2. Internal PWM Control Circuit

Figure 3. PWM Operation for CC and CV

Output Current Estimation

Figure 4 shows the key waveform of a flyback converter

operating in Discontinuous Conduction Mode (DCM),

where the secondary side diode current reaches zero before

the next switching cycle begins. Since the output current

estimator of FAN302 is designed for DCM operation, the

power stage should be designed such that DCM is

guaranteed for the entire operating range. The output

current is obtained by averaging the triangular output diode

current area over a switching cycle, as calculated by:

AVG DIS

OD PK

II I

== ⋅

(1)

where IPK is the peak value of the primary-side current;

NP and NS are the number of turns of the transformer,

primary side and secondary side, respectively; tDIS is the

diode current discharge time; and tsis switching period.

PK S

⋅

AVG

⋅

Figure 4. Key Waveforms of DCM Flyback Converter

AN-6094

Rev. 1.0.0 • 9/27/12 3

3. Design Consideration

Figure 5. Operation Range of Charger with CC/CV

A battery charger power supply with CC output requires

more design consideration than the conventional power

supply with a fixed output voltage. In CC operation, the

output voltage changes according to the charging

condition of battery. The supply voltage for the PWM

controller (VDD), which is usually obtained from the

auxiliary winding of the transformer, changes with the

output voltage. Thus, the allowable VDD operation range

determines the output voltage variation range in CC

regulation. FAN302 has a wide supply voltage (VDD)

operation range from 5 V up to 26.5 V, which allows

stable CC regulation even with output voltage lower than

a quarter of its nominal value.

Another important design consideration for CC operation

is that the transformer should be designed to guarantee

DCM operation over the whole operation range since the

output current can be properly estimated only in DCM, as

described in Section 2. As seen in Figure 5, the MOSFET

conduction time (tON) decreases as output voltage

decreases in CC Mode, which is proportional to the square

root of the output voltage. Meanwhile, the diode current

discharge time (tDIS) increases as the output voltage

decreases, which is inversely proportional to the output

voltage. Since the increase of tDIS is dominant over the

decrease of tON in determining the sum of tON and tDIS, the

sum of tON and tDIS tends to increases as output voltage

decreases. When the sum of tON and tDIS are same as the

switching period, the converter enters CCM. FAN302 has

a frequency-reduction function to prevent CCM operation

by extending the switching period as the output voltage

drops, as illustrated in Figure 6. The output voltage is

indirectly sensed by sampling the transformer winding

voltage (VSH) around the end of diode current discharge

time, as illustrated in Figure 4. The frequency-reduction

profile is designed such that the on-time remains almost

constant even when the output voltage drops in CC Mode.

CCG

−

Figure 6. Frequency Reduction in CC Mode

AN-6094

Rev. 1.0.0 • 9/27/12 4

4. Design Procedure

In this section, a design procedure is presented using the

Figure 1 as a reference. An offline charger with 6 W / 5 V

output has been selected as a design example. The design

specifications are:

Line Voltage Range: 90~264 VAC and 60 Hz

Nominal Output Voltage and Current: 5 V/1.2 A

Output Voltage Ripple: Less than 100 mV

Minimum Output Voltage in CC Mode: 25% of

Nominal Output (1.25 V)

Maximum Switching Frequency: 140 kHz

Figure 7. Output Voltage and Current Operating Area

[STEP-1] Estimate the Efficiencies

The charger application has output voltage and current

that change over a wide range, as shown in Figure 7,

depending on the charging status of the battery. Thus, the

efficiencies and input powers of various operating

conditions should be specified to optimize the power stage

design. The critical operating points for design:

Operating Point A, where the output voltage and

current reach maximum value (nominal output

voltage and current).

Operating Point B, where the frequency drop is

initiated to maintain DCM operation.

Operating Point C, where the output has its

minimum voltage in CC Mode.

Typically, low line is the worst case for the transformer

design since the largest duty cycle occurs at the minimum

input voltage condition. As a first step, the following

parameters should be estimated for low line.

Estimated overall efficiency for operating points A, B,

and C (EFF@A, EFF@B, and EFF@C): The overall power

conversion efficiency should be estimated to calculate

the input power and maximum DC link voltage ripple.

If no reference data is available, use the typical

efficiencies in Table 1.

Estimated primary-side efficiency (EFF.P) and

secondary-side efficiency (EFF.S) for operating point A,

B, and C. Figure 8 shows the definition of primary-

side and secondary-side efficiencies. The primary-side

efficiency is for the power transferred from the AC

line to the transformer primary side. The secondary-

side efficiency is for the power transferred from the

transformer primary side to the power supply output.

Since the rectifier diode forward voltage drop does not

change much with its voltage rating, the conduction loss

of output rectifier diode tends to be dominant for a low

output voltage application. Therefore, the distribution of

primary-side and secondary-side efficiencies changes with

the output voltage. With a given transformer efficiency,

the secondary- and primary-side efficiency, ignoring the

diode switching loss, are given as:

FF S FF TX N

EEVV

≅⋅

+(2)

FF P FF FF S

EEE=(3)

where EFF.TX is transformer efficiency, typically

0.95~0.98%; VO

Nis the nominal output voltage; and

VFis the rectifier diode forward-voltage drop.

Table 1. Typical Efficiency of Flyback Converter

Output

Voltage

Typical Efficiency at Minimum

Line Voltage

Universal Input European Input

3.3 ~ 6 V 65 ~ 70% 67 ~ 72%

6 ~ 12 V 70 ~ 77% 72 ~ 79%

12 ~ 24 V 77 ~ 82% 79 ~ 84%

Figure 8. Primary-Side and Secondary-Side Efficiency

With the estimated overall efficiency, the input power at

operating point A is given as:

IN A FF A

=(4)

where VO

Nand IO

Nare the nominal output voltage and

current, respectively.

AN-6094

Rev. 1.0.0 • 9/27/12 5

The input power of transformer at operating point A is

given as:

IN T A FF S A

(5)

To reduce the switching frequency as the output voltage

drops in CC Mode for maintaining DCM operation, the

output voltage needs to be sensed. FAN302 senses the

output voltage indirectly by sampling auxiliary winding

voltage just before the diode conduction finishes, as

explained with Figure 4 in Section 2. Since the switching

frequency starts decreasing as VSsampling voltage drops

below 2.15 V, as illustrated in Figure 6, the output voltage

at operating point B can be obtained as:

@..

2.15 ()

OB O FSH FSH

SH A

VVVV

=⋅+ −

(6)

where VSH@A is the VSsampling voltage at operating

point A, which is typically designed as 2.5 V and VF.SH

is the rectifier diode forward voltage drop at the VS

sampling instant (85% of diode conduction time), which

is typically about 0.1 V. Note that VF.SH is less than a

third of VFsince the Vs voltage sampling occurs when

the diode current is very small.

The overall efficiency at operating point B, where the

frequency reduction starts, can be estimated as:

OB OF

FF B FF A N

OB F O

VVV

≅⋅ ⋅

(7)

Note that the efficiency changes as the output voltage

drops in CC Mode. The efficiency should be also

estimated for each operating point (B and C).

The secondary-side efficiency at operating point B can be

estimated as:

.@ .@

OB OF

FF S B FF S A N

OB F O

VVV

≅⋅ ⋅

(8)

Then, the power supply input power and transformer input

power at operating point B are given as:

OB O

IN B FF B

⋅

(9)

OB O

IN T B FF S B

⋅

(10)

The overall efficiency at operating point C can be

approximated as:

OC OF

FF C FF N

OC F O

VVV

≅⋅ ⋅

(11)

where VO@C is the minimum output voltage for CC

Mode at operating point C.

The secondary-side efficiency at operating point C can be

estimated as:

.@ .@

OC OF

FF S C FF S A N

OC F O

VVV

≅⋅ ⋅

(12)

Then, the power supply input power and transformer input

power at operating point C are given as:

OC O

IN C FF C

⋅

=(13)

OC O

IN T C FF S C

⋅

=(14)

(Design Example)

To maximize efficiency, a low-voltage-drop Schottky

diode whose forward voltage drop is 0.35 V is selected.

Assuming the overall efficiency is 73% and the

transformer efficiency is 97% at operating point A

(nominal output voltage and current) for low line, the

secondary-side efficiency is obtained as:

.@ . 0.907

FF S A FF TX N

≅⋅ =

Then, the input powers of the power supply and

transformer at operating point A are obtained as:

68.22

0.73

IN A FF A

PIW

===

66.62

0.907

IN T A FF S A

PEW===

The efficiencies at operating point B are:

0.722

OB OF

FF B FF A N

OB F O

VVV

≅⋅ ⋅ =

.@ .@

0.896

OB OF

FF S B FF S A N

OB F O

VVV

≅⋅ ⋅ =

Then, the input powers of the power supply and

transformer at operating point B are obtained as:

7.07

OBO

IN B FF B

PIW

5.69

OBO

IN T B FF S B

PIW

The primary-side and secondary-side efficiencies at the

operating point C are calculated as:

0.610

OC OF

FF C FF A N

OC F O

VVV

≅⋅ ⋅ =

.@ .@

0.758

OC OF

FF S C FF S A N

OC F O

VVV

≅⋅ ⋅ =

Then, the input powers of the power supply and

transformer at operating point C are obtained as:

2.46

OC O

IN C FF C

PIW

=⋅=

1.98

OC O

IN T C FF S C

PIW

⋅

AN-6094

Rev. 1.0.0 • 9/27/12 6

[STEP-2] Determine the DC Link Capacitor

(CDL) and the DC Link Voltage Range

It is typical to select the DC link capacitor as 2-3 µF per

watt of input power for universal input range (90-

264 VAC) and 1 µF per watt of input power for European

input range (195~265 Vrms). With the DC link capacitor

chosen, the minimum DC link voltage is obtained as:

min min 2

(1 )

2( )

NA ch

DL A LINE DL L

−

=⋅ − ⋅(15)

where VLINE

min is the minimum line voltage; CDL is the

DC link capacitor; fLis the line frequency; and Dch is

the DC link capacitor charging duty ratio defined as

shown in Figure 9, which is typically about 0.2.

The maximum DC link voltage is given as:

max max

DL LINE

VV=⋅ (16)

where VLINE

max is the maximum line voltage.

The minimum DC link voltage and its ripple change with

input power. The minimum input DC link voltage at

operating point B is given as:

min min 2

(1 )

2( )

NB ch

DL B LINE DL L

−

=⋅ − ⋅(17)

The minimum input DC link voltage at operating point C

is given as:

min min 2

(1 )

2( )

NC ch

DL C LINE DL L

−

=⋅ − ⋅(18)

Figure 9. DC Link Voltage Waveforms

(Design Example) By choosing two 6.8 µF capacitors

in parallel for the DC link capacitor, the minimum and

maximum DC link voltages for each condition are

obtained as:

min min 2

(1 )

2( )

8.22(1 0.2)

2 (90) 90

2 6.8 10 60

IN A ch

DL A LINE DL L

−

=⋅ − ⋅

−

=⋅ − =

⋅× ⋅

max 2 264 373

VV=⋅ =

min min 2

(1 )

2( )

7.07(1 0.2)

2(90) 96

26.8 10 60

NB ch

DL B LINE DL L

−

=⋅ − ⋅

−

=⋅ − =

⋅× ⋅

min min 2

(1 )

2( )

2.46(1 0.2)

2 (90) 117

26.8 10 60

NC ch

DL C LINE DL L

−

=⋅ − ⋅

−

=⋅ − =

⋅× ⋅

[STEP-3] Determine Transformer Turns

Ratio

Figure 10 shows the MOSFET drain-to-source voltage

waveforms. When the MOSFET is turned off, the sum of

the input DC link voltage (VDL) and the output voltage

reflected to the primary side is imposed across the

MOSFET, calculated as:

maxnom

SDLRO

VVV=+

(19)

where VRO is reflected output voltage, defined as:

()

OOF

VVV

=+ (20)

where NPand NSare number of turns for the primary

side and secondary side, respectively.

When the MOSFET is turned on; the output voltage,

together with input voltage reflected to the secondary, are

imposed across the secondary-side rectifier diode

calculated as:

maxnom N

DL O

VVV

=+ (21)

As observed in Equations (19), (20), and (21); increasing

the transformer turns ratio (NP/ NS) increases voltage

stress on the MOSFET while reducing voltage stress on

the rectifier diode. Therefore, the NP/ NSshould be

determined by the trade-off between the MOSFET and

diode voltage stresses.

The transformer turns ratio between the auxiliary winding

and the secondary winding (NA / NS) should be

determined by considering the allowable IC supply

voltage (VDD) range. The VDD voltage varies with load

condition, as shown in Figure 11, where the minimum

VDD typically occurs at minimum load condition. Due to

the voltage overshoot of the auxiliary winding voltage

caused by the transformer leakage inductance; the VDD at

operating point C tends to be higher than the VDD at

minimum load condition.

The VDD at minimum load condition is obtained as:

min ()

DOFFA

VVVV

≅+−

(22)

where VFA is the diode forward-voltage drop of the

auxiliary winding diode.

The transformer turns ratio should be determined such

that VDD

min is higher than the VDD UVLO voltage, such as:

max

()

AOF FAUVLO MRGN

NVV V V V

N+−> +

(23)

Since the VDD

min is related to standby power consumption,

smaller NA/ NSleads to lower standby power

consumption. However, 2~3 V margin (VMRGN) should be

AN-6094

Rev. 1.0.0 • 9/27/12 7

added in to Equation (23), considering the VDD ripple

caused by Burst Mode operation at no-load condition.

NVV

N+

()

POF

NVV

N+

Figure 10. Voltage Stress on MOSFET and Diode

Figure 11. VDD and Winding Voltage

(Design Example)

For a 700 V MOSFET to have 35% margin on VDS

nom,

the reflected output voltage should be:

373 0.65 700 455

nom

DS RO

VV V

=+< ×=

∴<

Setting VRO=71 V, NP/ NSis obtained as:

71 13.27

( ) 5.35

SoF

NVV

===

Then, the voltage stress of diode is obtained as:

max 33.13

nom S

DDLO

VVVV

=+=

The allowable minimum VDD is 5.3 V, considering the

tolerances of UVLO. Considering voltage ripple on VDD

caused by burst operation at no-load condition, a 2 V

margin is added for VDD voltage calculation at no-load

condition, calculated as:

min max

()

(5 0.35) 0.7 5.3 2

D O F FA UVLO MRGN

VVVVVV

=+−> +

+−>+

1.5

∴>

To minimize the power consumption of the IC by

minimizing VDD at no-load condition, NA/ NSis

determined as 1.6.

[STEP-4] Design the Transformer

Figure 12 shows the MOSFET conduction time (tON),

diode current discharge time (tDIS), and diode non-

conduction time (tOFF). For the transformer design, first

determine how much non-conduction time (tOFF) is used in

DCM operation. The diode current discharge time

increases as the output voltage drops in CC Mode. Even

though tON decreases as output voltage drops, tON is

proportional to the square root of the output voltage, while

tDIS is inversely proportional to the output voltage. Thus,

the sum of tON and tDIS tends to increase, which reduces

the tOFF, forcing the flyback converter with a fixed

switching frequency into CCM operation as the output

voltage drops.

Thus, operating point B, where the frequency reduction

starts, is the worst case for determining the non-

conduction time (tOFF), as illustrated in Figure 12. tOFF

should be large enough to cover the transformer variation

and frequency hopping. However, too large tOFF increases

RMS current of the primary side current. It is typical to

set tOFF as 15-20% of the switching period.

AN-6094

Rev. 1.0.0 • 9/27/12 8

Once the tOFF is determined at operating point B, the

MOSFET conduction time is obtained as:

@min

(1 )

SOFFB

ON B DL B

POB F

−

+⋅ +

(24)

Then, the transformer primary-side inductance can be

calculated as:

min 2

()

DL B ON B

IN T B

⋅

=⋅

(25)

Once the transformer primary-side inductance is

determined, DCM operation at operating point C should

be checked. To prevent CCM operation, FAN302

decreases the switching frequency as the output voltage

drops, as illustrated in Figure 13. The switching frequency

at the minimum output voltage is obtained as:

(2.15 )

OC FSH

SC S SHA N

SH O F SH

ff V

VVV

=− − ⋅

Δ+

(26)

where ΔfS/ ΔVSH is 64 kHz / V for UL version and

38 kHz / V for HL version, and VF.SH is the rectifier

diode forward voltage drop at the VSsampling instant

(85% of diode conduction time).

Then, the MOSFET conduction time at operating point C

is given as:

@min

NT C m

ON C DL C S C

tVf

=(27)

The non-conduction time at operating point C is given as:

min

1(1 )

DL C

OFF C ON C

SC P OC F

NV V

=− +⋅

(28)

The non-conduction time should be larger than 15% of

switching period, considering the transformer variation

and frequency hopping.

Figure 12. Variation of tON, tD, and tOFF

Figure 13. Frequency Reduction in CC Mode

Once the transformer primary-side inductance is obtained,

the maximum peak drain current can be calculated at the

nominal output condition (operating point A) as:

NT A

DS mS

ILf

=⋅(29)

The minimum number of turns for the transformer

primary side to avoid the core saturation is given by:

min

mDS

at e

NBA

=(30)

where AE is the cross-sectional area of the core in m2

and Bsat is the saturation flux density in Tesla. Figure 14

shows the typical characteristics of a ferrite core from

TDK (PC40). Since the saturation flux density (Bsat)

decreases as the temperature rises, the high temperature

characteristics should be considered, especially for

charger application in an enclosed case. If there is no

reference data, use Bsat=0.25~0.3T. With the turns ratio

obtained in STEP-3, determine the proper integer for Ns

such that the resulting NPis larger than NPmin obtained

from Equation (30).

Figure 14. Typical B-H Curves of Ferrite Core

(TDK/PC40)

AN-6094

Rev. 1.0.0 • 9/27/12 9

(Design Example) By setting the non conduction time at

operating point B as 1.6 µs, the MOSFET conduction

time is obtained as:

@min

1/ 2.15

(1 )

SOFFB

ON B DL B

POB F

NV V

−

+⋅ +

The transformer primary-side inductance is calculated

as:

min 2

()

527

DL B ON B

IN T B

⋅

=⋅=

Assuming VSH@A is 2.5 V, the switching frequency at the

minimum output voltage is obtained as:

(2.15 2.5 )

OC FSH

SC S N

SH O F SH

VVV

kHz

=− − ⋅

Δ+

The MOSFET conduction time at minimum output

voltage is obtained as:

@min

11.84

IN T C m

ON C DL C S C

The non-conduction time at minimum output voltage:

min

1(1 )

10.33

DL C

OFF C ON C

SC P OC F

NV V

=− +⋅

The peak drain current at maximum load condition is

given as:

2423

IN T A

DS mS

ImA

⋅

EE12.5 core is selected for the transformer. The

minimum number of turns for the transformer primary

side to avoid the core saturation is given by:

min

527 10 0.423 63.5

0.3 12.88 10

mDS

Psat e

NBA

−

×⋅

⋅×

Determine the proper integer for Ns such that the

resulting Npis larger than Npmin ; given as:

min

13.27

13.27 5 66

=×

=×=>

The auxiliary winding turns, NA, is obtained as:

1.6 5 8

=×=×=

[STEP-5] Set the Output Current and VS

Sensing Resistor

The nominal output current is determined by the sensing

resistor value and transformer turns ratio as:

PCCR

CS N

RNI K

=×(31)

where VCCR is 2.43 V and K=12 and 10.5 V for UL and

HL, respectively.

The voltage divider RVS1 and RVS2 should be determined

so that VSis about 2.5 V at 85% of diode current

conduction time as:

()

VS O F SH

VS S SH A

RVV

RNV

=−

(32)

The FAN302 indirectly senses input voltage using the VS

pin current while the MOSFET is turned on, as illustrated

in Figure 15. Since the VS pin voltage is clamped at 0.7 V

when the MOSFET is turned on, the current flowing out

of the VS pin is approximately proportional to the input

voltage, calculated as:

12 1

10.7

(0.7)

AADL

VS ON DL

VS VS P VS

NNV

NRRNR

=+ +≅ (33)

Figure 15. VS Pin Current Sensing

FAN302 modulates the minimum on-time of the

MOSFET such that it reduces as input voltage increases,

as shown Figure 16. This allows smaller minimum on

time for high-line condition, ensuring Burst Mode

operation occurs at almost the same power level

regardless of line voltage variation. The VScurrent needs

to be higher than 150 µA.

Increasing the minimum on-time by increasing RVS1 and

RVS2 allows FAN302 to enter Burst Mode at a higher

power level. This reduces the standby power consumption

by increasing power delivered to the output per switching.

However, this also increases the output voltage ripple by

increasing the time interval between switching bundles in

Burst Mode. Thus, the minimum on-time should be

determined by a trade-off between standby power

consumption and output voltage ripple. When selecting

RVS1 and RVS2, 150 µA is the VS current level to consider

seriously. If the VS current is lower than 150 µA, ton_min

won’t be larger.

This manual suits for next models

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