EVBUM2822/D
www.onsemi.com
3
BOARD DESCRIPTION AND TEST SETUP
Figure 3. NCP1680 Evaluation Board along with a Daughter Card Featuring Fast Leg Switches
The evaluation motherboard and daughter card are shown
in Figure 3. The motherboard includes multiple I/O
connectors and test points to simplify instrumentation and
waveform capture during the evaluation process. A brief
description and pinout of the I/O connectors is shown in
Table 2, and a listing of the test points plus the respective
circuit node is shown in Table 3.
There are some key points worth mentioning regarding
the I/O connectors and test points:
•The pins labeled GND and VOUT_RTN are NOT
electrically common. GND and VOUT_RTN are
physically separated by the ZCD resistor and the user
should take precaution to not short these two nodes
together. For example, the ground lead of an
Earth−connected oscilloscope probe should not be
simultaneously connected to both GND and
VOUT_RTN.
•The EVB requires an external VCC bias supply. It is
recommended to connect this bias supply at the J3
connector or across the TP8−TP10 test points. The
recommended operating range for VCC is 12–18 V with
a current sourcing capability greater than 10 mA. Once
the EVB has been enabled, VCC can fall as low as 9 V
before the NCP1680 UVLO circuit disables the
controller. A VCC voltage greater than 20 V will trip the
EVB over−voltage protection (OVP) and latch off the
controller.
•J6 – AC Input connector is pinned out for a 3−wire AC
input connection. However, the chassis GND connection
is not required and can be left open. The user should
determine the appropriate input connection based on their
application requirements.
•J10 – SKIP header should be open to allow normal
operation of the EVB. Placing a jumper across the J10
header will force the EVB into Skip/Standby mode
operation, described later.
•J11 – Inrush current limiter (ICL) bypass is populated by
default. If the user wishes to operate the NCP1680 EVB
with an ICL then J11 must be removed before populating
the ICL at REF DES RT2.
•J12 – Daughter card interface is not keyed. User should
take precaution that the daughter card is correctly oriented
into J12. Furthermore, user must take precaution that the
daughter card is never inserted or removed while VCC is
applied to the motherboard, doing so can damage EVB.
Table 2. I/O CONNECTOR DESCRIPTIONS
REF DES Function Pinout
J1, J7, J8, J9 GND Peg 1. GND
J2 DC Output
Voltage
1. VOUT_RTN
2. N/C
3. VOUT
J3 VCC 1. VCC
2. GND
J4 PFCOK Skip
Interface
1. CNTRL Signal
2. GND
J6 AC Input
Voltage
1. AC Line
2. Chassis GND
3. AC Neutral
J10 SKIP Control
Header
1. CNTRL
2. GND
J11 Inrush Current
Limit Bypass
1. VOUT_NTC
2. VOUT
J12 Daughter Card
Interface
1−6: VOUT_NTC
7−12: VBRIDGE
13−18: PWRGND
19−28: N/C
29−32: GND
33−34: PWML/LIN
35−36: PWMH/HIN
37−38: VCC
