TENX TECHNOLOGY TM57PA40 User manual

Advance
Information
tenx technology, inc.
Preliminary Rev 1.3, 2009/10/19
TM57PA20/
TM57PA40
8 Bit Microcontroller
User Manual
Tenx reserves the right to change or
discontinue this product without notice.
tenx technology inc.

Advance Information UM-TM57PA20&40_E
8 Bit Microcontroller
1tenx technology, inc.
Preliminary Rev 1.3, 2009/10/19
CONTENTS
FEATURES.......................................................................................................................... 3
BLOCK DIAGRAM .............................................................................................................. 4
PIN ASSIGNMENT .............................................................................................................. 4
FUNCTIONAL DESCRIPTION............................................................................................. 6
1. CPU Core ..................................................................................................................... 6
1.1 Clock Scheme and Instruction Cycle ................................................................... 6
1.2 Addressing Mode................................................................................................. 6
1.3 Programming Counter (PC) and Stack ................................................................ 7
1.4 ALU and Working (W) Register ........................................................................... 7
1.5 STATUS Register ................................................................................................ 7
1.6 Interrupt ............................................................................................................... 8
2. Chip Operation Mode.................................................................................................... 9
2.1 Reset ................................................................................................................... 9
2.2 System Configuration Register (SYSCFG) .......................................................... 9
2.3 PROM Re-use ................................................................................................... 10
2.4 Power-Down Mode ............................................................................................ 10
3. Peripheral Functional Block ........................................................................................ 11
3.1 Watchdog(WDT) / Wakeup(WKT) Timer ........................................................... 11
3.2 Timer0: 8-bit Timer/Counter with Pre-scale (PSC) ............................................ 12
3.3 Timer1: 8-bit Timer with Pre-scale (PSC) .......................................................... 13
3.4 8+2 bit PWM...................................................................................................... 14
3.5 12-bit ADC ......................................................................................................... 16
3.6 System Clock Oscillator..................................................................................... 18
3.7 BUZZER Output ................................................................................................ 19
4. I/O Port ....................................................................................................................... 21
4.1 PA0-2................................................................................................................. 21
4.2 PA3-6, PB0-1, PD0-7 ........................................................................................ 22
4.3 PA7.................................................................................................................... 22
MEMORY MAP .................................................................................................................. 23
F-Plane ........................................................................................................................... 23
R-Plane........................................................................................................................... 25
INSTRUCTION SET........................................................................................................... 27
ELECTRICAL CHARACTERISTICS ................................................................................. 39
1. Absolute Maximum Ratings ....................................................................................... 39
2. DC Characteristics..................................................................................................... 39
3. Clock Timing .............................................................................................................. 40
4. Reset Timing Characteristics..................................................................................... 40
5. LVR Circuit Characteristics........................................................................................ 40
6. ADC Electrical Characteristics ................................................................................... 40

Advance Information UM-TM57PA20&40_E
8 Bit Microcontroller
2tenx technology, inc.
Preliminary Rev 1.3, 2009/10/19
PACKAGING INFORMATION ........................................................................................... 42
20-DIP Package Dimension ....................................................................................... 42
20-SOP Package Dimension...................................................................................... 43
20-SSOP Package Dimension ................................................................................... 44
16-DIP Package Dimension ....................................................................................... 45
16-SOP Package Dimension...................................................................................... 46
16-SSOP Package Dimension ................................................................................... 47
8-DIP Package Dimension ......................................................................................... 48
8-SOP Package Dimension........................................................................................ 49

Advance Information UM-TM57PA20&40_E
8 Bit Microcontroller
3tenx technology, inc.
Preliminary Rev 1.3, 2009/10/19
FEATURES
1. ROM: 4K x 14 bits OTP or 2K x 14 bits TTP™ (Two Time Programmable ROM)
2. RAM: 184 x 8 bits
3. STACK: 6 Levels
4. I/O ports: Three Programmable I/O ports (Max. 18 pins)
5. Timer0/Counter: 8-bit timer/counter with divided by 1~256 pre-scale option
6. Timer1: 8-bit auto-reloadable timer with divided by 1~256 pre-scale option
7. Two 8+2 bit PWM channels capable of 1024 duty resolution
8. 12-bit ADC with 8 channel input
9. Buzzer output
10. Watchdog/Wakeup Timer: On chip Timer based on internal RC oscillation, 13~140mS wakeup time
11. Reset: Power On Reset, Watchdog Reset, Low Voltage Reset, External pin Reset
12. System Clock Mode:
- Slow Crystal: 32KHz
- Fast Crystal: 455KHz ~24MHz
- Internal RC: 4MHz
- External RC
13. Operation Voltage: Low Voltage Reset Level to 5.5V
14. Instruction set: 36 Instructions
15. Interrupts: Three pin interrupts, Timer0/Timer1 interrupt and Wakeup Timer interrupt
16. Power Down mode support
17. Package Types: 8 DIP/SOP, 16 DIP/SOP/SSOP, 20 DIP/SOP/SSOP
DEVICE OTP ROM TTP™ function Note
TM57PA40 4K x 14 bits Available
TM57PA20 2K x 14 bits Not Available

Advance Information UM-TM57PA20&40_E
8 Bit Microcontroller
4tenx technology, inc.
Preliminary Rev 1.3, 2009/10/19
BLOCK DIAGRAM
PIN ASSIGNMENT
VSS 1
U 20 VDD
Xrc/Xin/PA4 2 19 PA6/ADC0/INT0
Xout/PA3 3 18 PA1/ADC1/INT1
VPP/nRESET/INT2/PA7 4 TM57PA20 17 PA2/ADC2/T0I
T1OUT/PD0 5 TM57PA40 16 PB1/ADC3
BUZZER/PD1 6 20 SOP 15 PD7/ADC4
PD2 7 20 DIP 14 PA5/ADC5
PD3 8 20 SSOP 13 PA0/PWM0
PD4 9 12 PB0/ADC7/PWM1
PD5 10 11 PD6/ADC6/TCOUT
VSS 1
U 16 VDD
Xrc/Xin/PA4 2 TM57PA20 15 PA6/ADC0/INT0
Xout/PA3 3 TM57PA40 14 PA1/ADC1/INT1
VPP/nRESET/ INT2/PA7 4 16 SOP 13 PA2/ADC2/T0I
T1OUT/PD0 5 16 DIP 12 PB1/ADC3
BUZZER/PD1 6 16 SSOP 11 PD7/ADC4
PD2 7 10 PA5/ADC5
PD3 8 9 PA0/PWM0
VSS 1
U 8
VDD
Xrc/Xin/PA4 2 TM57PA20 7PA1/ADC1/INT1
Xout/PA3 3 TM57PA40 6PA2/ADC2/T0I
VPP/nRESET/ INT2/PA7 4 8 SOP/DIP 5 PA0/PWM0

Advance Information UM-TM57PA20&40_E
8 Bit Microcontroller
5tenx technology, inc.
Preliminary Rev 1.3, 2009/10/19
PIN DESCRIPTION
Name In/Out Pin Description
PA2–PA0 I/O
Bit-programmable I/O port for Schmitt-trigger input, CMOS “push-pull” output or
“pseudo-open-drain” output. Pull-up resistors are assignable by software.
PA6-PA3
PB1-PB0
PD7-PD0
I/O Bit-programmable I/O port for Schmitt-trigger input, CMOS “push-pull” output or
“open-drain” output. Pull-up resistors are assignable by software.
PA7 I Schmitt-trigger input
nRESET I External active low reset
Xin,Xout – Crystal/Resonator oscillator connection for system clock.
Xrc External RC oscillator connection for system clock
VDD, VSS P Power input pin and ground
VPP I PROM programming high voltage input
INT0~2 I External interrupt input
T0I I Timer0’s input in counter mode
T1OUT O Timer1 match output, T1OUT toggles when Timer1 overflow occurs
BUZZER O BUZZER output
TCOUT O
Instruction cycle clock divided by N output. Where N is 1,2,4,8. The instruction
clock frequency is system clock frequency divided by two.
PWM0/PWM1 O 10-bit PWM output
ADC7~0 I A/D converter input

Advance Information UM-TM57PA20&40_E
8 Bit Microcontroller
6tenx technology, inc.
Preliminary Rev 1.3, 2009/10/19
FUNCTIONAL DESCRIPTION
1. CPU Core
1.1 Clock Scheme and Instruction Cycle
The system clock is internally divided by two to generate Q1 state and Q2 state for each instruction
cycle. The Programming Counter (PC) is updated at Q1 and the instruction is fetched from program
ROM and latched into the instruction register in Q2. It is then decoded and executed during the
following Q1-Q2 cycle. Branch instructions take two cycles since the fetch instruction is ‘flushed’ from
the pipeline, while the new instruction is being fetched and then executed.
Fetch Execute
Branch
Instruction
Instruction
Pipeline
Flow Fetch Execute
Fetch Flush
Fetch Execute
Instruction
Cycle
FOSC
Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2
1.2 Addressing Mode
There are two Data Memory Planes in CPU, R-Plane and F-Plane. The registers in R-Plane are write-
only. The “MOVWR” instruction copy the W-register’s content to R-Plane registers by direct addressing
mode.
The lower locations of F-Plane are reserved for the SFR. Above the SFR is General Purpose Data
Memory, implemented as static RAM. F-Plane can be addressed directly or indirectly. Indirect
Addressing is made by INDF register. The INDF register is not a physical register. Addressing INDF
actually addresses the register whose address is contained in the FSR register (FSR is a pointer). The
first half of F-Plane is bit-addressable, while the second half of F-Plane is not bit-addressable.
R-Plane F-Plane
00 00
SFR
Bit Addressable
MOVWR Instruction 1F
Write Onl
y
20 RAM
Bit Addressable
27
28 RAMBANK=0 RAMBANK=1
Bit Addressable Bit Addressable
3F 3F
40 RAMBANK=0 RAMBANK=1
7F

Advance Information UM-TM57PA20&40_E
8 Bit Microcontroller
7tenx technology, inc.
Preliminary Rev 1.3, 2009/10/19
1.3 Programming Counter (PC) and Stack
The Programming Counter is 12-bit wide capable of addressing a 4K x 14 program ROM. As a program
instruction is executed, the PC will contain the address of the next program instruction to be executed.
The PC value is normally increased by one except the followings. The Reset Vector (000h) and the
Interrupt Vector (001h) are provided for PC initialization and Interrupt. For CALL/GOTO instructions, PC
loads 12 bits address from instruction word. For RET/RETI/RETLW instructions, PC retrieves its
content from the top level STACK. For the other instructions updating PC [7:0], the PC [11:8] keeps
unchanged. The STACK is 12-bit wide and 6-level in depth. The CALL instruction and Hardware
interrupt will push STACK level in order. While the RET/RETI/RETLW instruction pops the STACK level
in order.
1.4 ALU and Working (W) Register
The ALU is 8 bits wide and capable of addition, subtraction, shift and logical operations. In two-operand
instructions, typically one operand is the W register, which is an 8-bit non-addressable register used for
ALU operations. The other operand is either a file register or an immediate constant. In single operand
instructions, the operand is either W register or a file register. Depending on the instruction executed,
the ALU may affect the values of Carry (C), Digit Carry (DC), and Zero (Z) Flags in the STATUS
register. The C and DC flags operate as a /Borrow and /Digit Borrow, respectively, in subtraction.
1.5 STATUS Register
This register contains the arithmetic status of ALU and the Reset status. The STATUS register can be
the destination for any instruction, as with any other register. If the STATUS register is the destination
for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These
bits are set or cleared according to the device logic. It is recommended, therefore, that only BCF, BSF
and MOVWF instructions be used to alter the STATUS Register because these instructions do not
affect those bits.
STATUS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset Value – – 0 0 0 0 0 0
R/W – – R/W R R R/W R/W R/W
Bit Description
7-6 Not Used
5
RAMBANK: RAM Bank Selection
0: RAM Bank0
1: RAM Bank1
4
TO: Time Out
0: after Power On Reset, LVR Reset, or CLRWDT/SLEEP instruction
1: WDT time out occurred
3
PD: Power Down
0: after Power On Reset, LVR Reset, or CLRWDT instruction
1: after SLEEP instruction
2
Z: Zero Flag
0: the result of a logic operation is not zero
1: the result of a logic operation is zero
DC: Decimal Carry Flag or Decimal/Borrow Flag
ADD instruction SUB instruction
1 1: a carry from the low nibble bits of
the result occurred
0: no carry
1: no borrow
0: a borrow from the low nibble bits
of the result occurred
C: Carry Flag or Borrow Flag
ADD instruction SUB instruction
0 1: a carry occurred from the MSB
0: no carry
1: no borrow
0: a borrow occurred from the MSB

Advance Information UM-TM57PA20&40_E
8 Bit Microcontroller
8tenx technology, inc.
Preliminary Rev 1.3, 2009/10/19
1.6 Interrupt
The device has 1 level, 1 vector and six interrupt sources. Each interrupt source has its own enable
control bit. An interrupt event will set its individual pending flag, no matter its interrupt enable control bit
is 0 or 1. Because the device has only 1 vector, there is not an interrupt priority register. The interrupt
priority is determined by F/W.
If the corresponding interrupt enable bit has been set (INTE), it would trigger CPU to service the
interrupt. CPU accepts interrupt in the end of current executed instruction cycle. In the mean while, A
“CALL 001” instruction is inserted to CPU, and i-flag is set to prevent recursive interrupt nesting. The i-
flag is cleared in the instruction after the “RETI” instruction. That is, at least one instruction in main
program is executed before service the pending interrupt. The interrupt event is level trigged. F/W must
clear the interrupt event register while serves the interrupt routine.
Interrupt Pending
Interrupt
Vector
i-Flag
Interrupt
Source
Interrupt
Enable

Advance Information UM-TM57PA20&40_E
8 Bit Microcontroller
9tenx technology, inc.
Preliminary Rev 1.3, 2009/10/19
2. Chip Operation Mode
2.1 Reset
The device can be RESET in four ways.
－Power-On-Reset
－Low Voltage Reset (LVR)
－External Pin Reset(PA7)
－Watchdog Reset (WDT)
After Power-On-Reset, all system and peripheral control registers are then set to their default hardware
Reset values. And the clock source, LVR level and chip operation mode are selected by the SYSCFG
register value.
The Low Voltage Reset features static reset when supply voltage is below a threshold level. There are
two threshold levels can be selected. The LVR’s operation mode is defined by the SYSCFG register.
The External Pin Reset and Watchdog Reset can be disabled or enabled by the SYSCFG register. These
two resets also set all the control registers to their default reset value. The TO/PD flag is not affected by
these resets.
2.2 System Configuration Register (SYSCFG)
The System Configuration Register (SYSCFG) is located at ROM address FFCh. The SYSCFG
determines the option for initial condition of MCU. It is written by PROM Writer only. User can select clock
source, LVR threshold voltage and chip operation mode by SYSCFG register. The 13th bit of SYSCFG is
code protection selection bit. If this bit is 0, the data in PROM will be protected, when user read PROM.
Bit 13~0
Default Value 11_1111_111x_xxxx
Bit Description
13 nPROTECT: Code Protection Selection
1 No protect
0 Code protection
12 nREUSE: PROM Re-use Control
1 Not Re-use
0 Re-use (TM57PA20 do not support)
11-10 LVR: LV reset mode
11 LVR threshold is 2.1V, always enable
10 LVR threshold is 2.1V, disable in sleep mode
01 LVR threshold is 3.1V, always enable
00 LVR disable
9-8 CLKS: Clock Source Selection
11 Fast Xtal (455KHz~24MHz)
10 Slow Xtal (32KHz)
01 Internal RC (4MHz)
00 External RC
7 XRESETE: External pin Reset Enable
1 Enable External pin Reset
0 Disable External pin Reset
6 WDTE: WDT Reset Enable
1 Enable WDT Reset, Disable WKT Timer
0 Disable WDT Reset, Enable WKT Timer
4-0 IRCF: Internal RC Frequency adjustment control

Advance Information UM-TM57PA20&40_E
8 Bit Microcontroller
10 tenx technology, inc.
Preliminary Rev 1.3, 2009/10/19
2.3 PROM Re-use
The PROM size of TM57PA40 is 4K words. For some F/W program, the program size could be less than
2K words. To fully utilize the PROM, the device allows users to reuse the PROM. This feature is named
as Two Time Programmable (TTP) ROM. While the first half of PROM is occupied by a useless program
code and the second half of the PROM remains blank, users can re-write the PROM with the updated
program code into the second half of the PROM. In the Re-use mode, the Reset Vector and Interrupt
Vector are re-allocated at the beginning of the PROM's second half by the Assembly Compiler. Users
simply choose the "REUSE" option in the ICE tool interface, then the Compiler will move the object code
to proper location. That is, the user's program still has reset vector at address 000h, but the compiled
object code has reset vector at 800h. In the SYSCFG, if nPROTECT=0 and nREUSE=1, the Code
protection area is first half of PROM. This allows the Writer tool to write then verify the Code during the
Re-use Code programming. After the Re-use Code being written into the PROM's second half, user
should write "nREUSE" control bit to "0". In the mean while, the Code protection area becomes the whole
PROM except the Reserved Area.
PROM, nREUSE=1 PROM, nREUSE=0
000 Reset Vecto
r
000
001 Interru
p
t Vecto
r
001
Code Useless
Protect Code
Area
Use
r
Code
7FF Code 7FF Protect
800 800 Reset Vecto
r
Area
801 801 Interru
p
t Vecto
r
Use
r
Code
FFC SYSCFG FFC SYSCFG
FFD Manufacture
r
FFD Manufacture
r
FFE Reserved FFE Reserved
FFF Area FFF
A
rea
For TM57PA20, the PROM size is 2K words(0x000~0x7ff) and the address of PROM 0xffc~fff are still
Reserved Area. The REUSE function isn’t useful any more.
2.4 Power-Down Mode
The Power-down mode is activated by SLEEP instruction. During the Power-down mode, the system
clock and peripherals stops to minimize power consumption, while the WDT/WKT Timer is working or not
depends on F/W setting. The Power down mode can be terminated by Reset, or enabled Interrupts
(External pins and WKT interrupt).

Advance Information UM-TM57PA20&40_E
8 Bit Microcontroller
11 tenx technology, inc.
Preliminary Rev 1.3, 2009/10/19
3. Peripheral Functional Block
3.1 Watchdog(WDT) / Wakeup(WKT) Timer
The WDT and WKT share the same internal RC Timer. The overflow period of WDT/WKT can be selected
from 13mS to 140mS. The WDT/WKT is cleared by the CLRWDT instruction. If the Watchdog Reset is
enabled (WDTE=1), the WDT generates the chip reset signal, even in sleep mode, otherwise, the WKT
only generates overflow time out interrupt. If WDTE=0 and WKTIE=0 (Wakeup interrupt disable), the
internal RC Timer stops for power saving.

Advance Information UM-TM57PA20&40_E
8 Bit Microcontroller
12 tenx technology, inc.
Preliminary Rev 1.3, 2009/10/19
3.2 Timer0: 8-bit Timer/Counter with Pre-scale (PSC)
The Timer0 is an 8-bit wide register of F-Plane. It can be read or written as any other register of F-Plane.
Besides, Timer0 increases itself periodically and automatic roll over base on the pre-scaled clock source,
which can be the instruction cycle or T0I input. The Timer0 increase rate is determined by “Timer0 Pre-
Scale” (TM0PSC) register in R-Plane. The Timer0 can generate interrupt (TM0I) when it rolls over.

Advance Information UM-TM57PA20&40_E
8 Bit Microcontroller
13 tenx technology, inc.
Preliminary Rev 1.3, 2009/10/19
3.3 Timer1: 8-bit Timer with Pre-scale (PSC)
The Timer1 is an 8-bit wide register of F-Plane. It can be read or written as any other register of F-Plane.
Besides, Timer1 increases itself periodically and automatic reloads a new “offset value” (TM1RELD) while it
rolls over base on the pre-scaled instruction clock. The Timer1 increase rate is determined by “Timer1 Pre-
Scale” (TM1PSC) register in R-Plane. The Timer1 can generate interrupt (TM1I) and T1OUT toggle signal
when it rolls over.

Advance Information UM-TM57PA20&40_E
8 Bit Microcontroller
14 tenx technology, inc.
Preliminary Rev 1.3, 2009/10/19
3.4 8+2 bit PWM
PWM0 and PWM1 have the same structure. The PWM can generate fix frequency waveform with 1024 duty
resolution base on System Clock. A spread LSB technique allow PWM to run its frequency at “System Clock
divided by 256” instead of “System Clock divided by 1024”, which means the PWM is 4 times fast than normal.
The advantage of higher PWM frequency is that the post RC filter can transform the PWM signal to more
stable DC voltage level. The PWM output signal reset to low level whenever the 8-bit base counter matches
the 8-bit MSB of PWM duty register (PWMDUTY). When the base counter rolls over, the 2-bit LSB of PWM
duty register decide whether to set the PWM output signal high immediately or set it high after one clock cycle
delay.

Advance Information UM-TM57PA20&40_E
8 Bit Microcontroller
15 tenx technology, inc.
Preliminary Rev 1.3, 2009/10/19
PWM example code:
movlw 01111111b
movwf 0ch ;set PWM0DUTY[9:2]=8’b01111111
movlw 11000000b
movwf 0dh ;set PWM0DUTY[1:0]=2’b11
movlw 01000000b
movwr 0bh ;enable PWM0 output to PA0 (PWM0_OUT)
:
:
movlw 00h
movwr 0bh ;disable PWM0 (PWM0_OUT)

Advance Information UM-TM57PA20&40_E
8 Bit Microcontroller
16 tenx technology, inc.
Preliminary Rev 1.3, 2009/10/19
3.5 12-bit ADC
The 12-bit ADC (Analog to Digital Converter) consists of a 8-channel analog input multiplexer, control register,
clock generator, 12 bit successive approximation register, and output data register. To use the ADC, user
needs to set ADCLKS to choose a proper ADC clock frequency, which must be less than 2MHz. User then
launch the ADC conversion by set the ADCSTART control bit. After end of conversion, H/W automatic clears
the ADCSTAT bit. User can poll this bit to know the conversion status. The nADC_IE control register is used
for ADC pin type setting, user can write the corresponding bit to “0” when the pin is used as a ADC input. The
setting can disable the pin logical input path to save power consumption.
ADC example code:
movlw 00000111b
movwf 11h ;ADC channel select,ADC7(PB0) (ADCSEL)
movlw 00000001h
movwr 09h ;disable PB0 pull up resistor (nPBPU)
movlw 01111111b

Advance Information UM-TM57PA20&40_E
8 Bit Microcontroller
17 tenx technology, inc.
Preliminary Rev 1.3, 2009/10/19
movwr 12h ;set ADC7 input enable (nADC_IE)
movlw 00010000b
movwr 0ch ;set ADC clock is instruction cycle / 64 (ADCCLKS)
bsf 11h,3 ;start ADC conversion (ADCSTART)
ADC_LOOP:
btfsc 11h,3
goto ADC_LOOP ;wait ADCSTART go LOW
: ;read ADCQ[11:0] (ADCDQ)
:

Advance Information UM-TM57PA20&40_E
8 Bit Microcontroller
18 tenx technology, inc.
Preliminary Rev 1.3, 2009/10/19
3.6 System Clock Oscillator
System Clock can be operated in four different oscillation modes, which is selected by setting the CLKS in the
SYSCFG register. In Slow/Fast Crystal mode, a crystal or ceramic resonator is connected to the Xin and Xout
pins to establish oscillation. In external RC mode, the external resistor and capacitor determine the oscillation
frequency. In the internal RC mode, the on chip oscillator generates 4MHz system clock.
.
XIN
XOUT
C1
C2
External Oscillator Circuit
(Crystal or Ceramic)
External RC Oscillator

Advance Information UM-TM57PA20&40_E
8 Bit Microcontroller
19 tenx technology, inc.
Preliminary Rev 1.3, 2009/10/19
3.7 BUZZER Output
The Buzzer driver consists of 6-bit counter and a clock divider. It generates 50% duty square waveform with
wide frequency range. To use the Buzzer function, user need to set both the Buzzer enable control bit
(BUZ_EN) and the Buzzer output pin enable control bit (BUZ_OUT).
Buzzer
Counter
Buffer
Reload
Buzzer
Output
Buzzer Data
Change
Before > After
Buzzer Data
Change
Before < After
Buzzer
Disable Buzzer
Enable
BUZ_PROD[5:0] determines output frequency. Frequency calculation is as follows.
FBZ = (fOSC/2) / (Instruction Cycle Divider) / (BUZ_PROD +1)
Output frequency calculation
CPU Clock (fosc) = 8192KHz
Instruction Cycle = fosc/2 = 8192KHz/2 = 4096KHz
Prescaler Ratio (BUZ_PSC) = 2’b11 (Instruction Cycle Divider = 32)
Period Data (BUZ_PROD) = 9