Toshiba TMP96C141AF User manual

TOSHIBA
TOSHIBA CORPORATION
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TLCS-900 Series TMP96C141AF
The information contained here is subject to change without notice.
The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equip-
ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
CMOS 16-bit Microcontroller
TMP96C141AF
1. Outline and Device Characteristics
The TMP96C141AF is high-speed advanced 16-bit microcon-
troller developed for controlling medium to large-scale equip-
ment.
The TMP96C141AF is housed in an 80-pin flat package.
Device characteristics are as follows:
(1) Original 16-bit CPU
• TLCS-90 instruction mnemonic upward compatible.
• 16M-byte linear address space
• General-purpose registers and register bank system
• 16-bit multiplication/division and bit transfer/arithmetic
instructions
• High-speed micro DMA
- 4 channels (1.6 µ s/2 bytes @ 20MHz)
(2) Minimum instruction execution time
- 200ns @ 20MHz
(3) Internal RAM: 1K byte
Internal ROM: None
(4) External memory expansion
• Can be expanded up to 16M bytes (for both programs and
data).
• Can mix 8- and 16-bit external data buses.
…
Dynamic data bus sizing
(5) 8-bit timers: 2 channels
(6) 8-bit PWM timers: 2 channels
(7) 16-bit timers: 2 channels
(8) Pattern generators: 4 bits, 2 channels
(9) Serial interface: 2 channels
(10) 10-bit A/D converter: 4 channels
(11) Watchdog timer
(12) Chip select/wait controller: 3 blocks
(13) Interrupt functions
• 3 CPU interrupts
… …
SWI instruction, privileged violation,
and Illegal instruction
• 14 internal interrupts
• 6 external interrupts
(14) I/O ports
(15) Standby function : 3 halt modes (RUN, IDLE, STOP)
7-level priority can be set.

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TMP96C141AF
Figure 1. TMP96C141AF Block Diagram

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TMP96C141AF
2. Pin Assignment and Functions
The assignment of input/output pins for TMP96C141AF, their
name and outline functions are described below.
Figure 2.1 Pin Assignment (80-pin QFP)
2.1 Pin Assignment
Figure 2.1 shows pin assignment of TMP96C141AF.

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TMP96C141AF
2.2 Pin Names and Functions
The names of input/output pins and their functions are described below.
Note: With the external DMA controller, this device’s built-in memory or built-in I/O cannot be accessed using the BUSRQ and BUSAK pins.
Table 2.2. Pin Names and Functions
Pin Name Number
of Pins I/O Functions
P00 ~ P07
AD0 ~ AD7 8I/O Tri-state
Port 0: I/O port that allows I/O to be selected on a bit basis
Address / data (lower): 0 - 7 for address / data bus
P10 ~ P17
AD8 ~ AD15
A8 ~ A15
8
I/O
Tri-state
Output
Port 1: I/O port that allows I/O to be selected on a bit basis
Address data (upper): 8 - 15 for address / data bus
Address: 8 to 15 for address bus
P20 ~ P27
A0 ~ A7
A16 ~ A23
8
I/O
Output
Output
Port 2: I/O port that allows selection of I/O on a bit basis (with pull-down resistor)
Address: 0 - 7 for address bus
Address: 16 - 23 for address bus
P30
RD 1Output
Output
Port 30: Output port
Read: Strobe signal for reading external memory
P31
WR 1Output
Output
Port 31: Output port
Write: Strobe signal for writing data on pins AD0 -7
P32
HWR 1I/O
Output
Port 32: I/O port (with pull-up resistor)
High write: Strobe signal for writing data on pins AD8 - 15
P33
WAIT 1I/O
Input
Port 33: I/O port (with pull-up resistor)
Wait: Pin used to request CPU bus wait
P34
BUSRQ 1 I/O
Input
Port 34: I/O port (with pull-up resistor)
Bus request: Signal used to request high impedance for AD0 - 15, A0 - 23, RD, WR, HWR, R/W, RAS, CS0,
CS1, and CS2 pins. (For external DMAC)
P35
BUSAK 1I/O
Output
Port 35: I/O (with pull-up resistor)
Bus acknowledge: Signal indicating that AD0 - 15, A0 - 23, RD, WR, HWR, R/W, RAS, CS0, CS1, and CS2
pins are at high impedance after receiving BUSRQ. (For external DMAC)
P36
R/W 1I/O Output
Port 36: I/O port (with pull-up resistor)
Read/write: 1 represents read or dummy cycle; 0, write cycle.
P37
RAS 1I/O
Output
Port 37: I/O port (with pull-up resistor)
Row address strobe: Outputs RAS strobe for DRAM.
P40
CS0
CAS0
1
I/O
Output
Output
Port 40: I/O port (with pull-up resistor)
Chip select 0: Outputs 0 when address is within specified address area.
Column address strobe 0: Outputs CAS strobe for DRAM when address is within specified address area.

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TMP96C141AF
Pin Name Number
of Pins I/O Functions
P41
CS1
CAS1
1
I/O
Output
Output
Port 41: I/O port (with pull-up resistor)
Chip select 1: Outputs 0 if address is within specified address area.
Column address strobe 1: Outputs CAS strobe for DRAM if address is within specified address area.
P42
CS2
CAS2
1
I/O
Output
Output
Port 42: I/O port (with pull-up resistor)
Chip select 2: Outputs 0 if address is within specified address area.
Column address strobe 2: Outputs CAS strobe for DRAM if address is within specified address area.
P50 ~ P53
AN0 ~ AN3 4Input Input
Port 5: Input port
Analog input: Input to A/D converter
VREF 1 Input Pin for reference voltage input to A/D converter
AGND 1 Input Ground pin for A/D converter
P60 ~ P63
PG00 ~ PG03 4I/O Output
Ports 60 - 63: I/O ports that allow selection of I/O on a bit basis (with pull-up resistor)
Pattern generator ports: 00 - 03
P64 ~ P67
PG10 ~ PG13 4I/O Output
Ports 64 - 67: I/O ports that allow selection of I/O on a bit basis (with pull-up resistor)
Pattern generator ports: 10 - 13
P70
T10 1I/O Input
Port 70: I/O port (with pull-up resistor)
Timer input 0: Timer 0 input
P71
T01 1I/O Output
Port 71: I/O port (with pull-up resistor)
Timer output 1: Timer 0 or 1 output
P72
T02 1I/O Output
Port 72: I/O port (with pull-up resistor)
PWM output 2: 8-bit PWM timer 2 output
P73
T03 1I/O Output
Port 73: I/O port (with pull-up resistor)
PWM output 3: 8-bit PWM timer 3 output
P80
TI4
INT4
1
I/O
Input
Input
Port 80: I/O port (with pull-up resistor)
Timer input 4: Timer 4 count/capture trigger signal input
Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge
P81
TI5
INT5
1
I/O
Input
Input
Port 81: I/O port (with pull-up resistor)
Timer input 5: Timer 4 count/capture trigger signal input
Interrupt request pin 5: Interrupt request pin with rising edge
P82
TO4 1I/O Output
Port 82: I/O port (with pull-up resistor)
Timer output 4: Timer 4 output pin
P83
TO5 1I/O Output
Port 83: I/O port (with pull-up resistor)
Timer output 5: Timer 4 output pin

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TMP96C141AF
Note: Pull-up/pull-down resistor can be released from the pin by software.
Pin Name Number
of Pins I/O Functions
P84
TI6
INT6
1
I/O
Input
Input
Port 84: I/O port (with pull-up resistor)
Timer input 6: Timer 5 count/capture trigger signal input
Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge
P85
TI7
INT7
1
I/O
Input
Input
Port 85: I/O port (with pull-up resistor)
Timer input 7: Timer 5 count/capture trigger signal input
Interrupt request pin 7: Interrupt request pin with rising edge
P86
TO6 1I/O Output
Port 86: I/O port (with pull-up resistor)
Timer output 6: Timer 5 output pin
P87
INT0 1I/O Input
Port 87: I/O port (with pull-up resistor)
Interrupt request pin 0: Interrupt request pin with programmable level/rising edge
P90
TXD0 1I/O Output
Port 90: I/O port (with pull-up resistor)
Serial send data 0
P91
RXD0 1I/O Input
Port 91: I/O port (with pull-up resistor)
Serial receive data 0
P92
CTS0 1I/O
Input
Port 92: I/O port (with pull-up resistor)
Serial data send enable 0 (Clear to Send)
P93
TXD1 1I/O Output
Port 93: I/O port (with pull-up resistor)
Serial send data 1
P94
RXD1 1I/O Input
Port 94: I/O port (with pull-up resistor)
Serial receive data 1
P95
SCLK1 1I/O I/O
Port 95: I/O port (with pull-up resistor)
Serial clock I/O 1
WDTOUT 1 Output Watchdog timer output pin
NMI 1 Input Non-maskable interrupt request pin: Interrupt request pin with falling edge.
Can also be operated at rising edge by program.
CLK 1 Output Clock output: Outputs X1 ÷ 4 clock. Pulled-up during reset.
EA 1 Input External access: 0 should be inputted with TMP96C141AF
1, with TMP96CM40F/TMP96PM40F.
ALE 1 Output Address latch enable
RESET 1 Input Reset: Initializes LSI. (With pull-up resistor)
X1/X2 2 I/O Oscillator connecting pin
VCC 2 Power supply pin (+ 5V)
VSS 3 GND pin (0V)

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TMP96C141AF
3. Operation
This section describes in blocks the functions and basic oper-
ations of the TMP96C141AF device.
Check the chapter Guidelines and Restrictions for proper
care of the device.
3.1 CPU
The TMP96C141AF device has a built-in high-performance
16-bit CPU. (For CPU operation, see TLCS-900 CPU in the
book Core Manual Architecture User Manual.)
This section describes CPU functions unique to
TMP96C141AF that are not described in that manual.
3.1.1 Reset
To reset the TMP96C141AF, the RESET input must be kept at
0 for at least 10 system clocks (10 states: 1 µ s with a 20MHz
system clock) within an operating voltage range and with a
stable oscillation.
When reset is accepted, the CPU sets as follows:
• Program counter (PC) to 8000H.
• Stack pointer (XSP) for system mode to 100H.
• SYSM bit of status register (SR) to 1. (Sets to system mode.)
• IFF2 to 0 bits of status register to 111. (Sets mask register to
interrupt level 7.)
• MAX bit of status register to 0. (Sets to minimum mode.)
• Bits RFP2 to 0 of status register to 000. (Sets register banks
to 0.)
When reset is released, instruction execution starts from
address 8000H. CPU internal registers other than the above
are not changed.
When reset is accepted, processing for built-in I/Os,
ports, and other pins is as follows:
• Initializes built-in I/O registers as per specifications.
• Sets port pins (including pins also used as built-in I/Os) to
general-purpose input/output port mode (sets I/O ports to
input ports).
• Sets the WDTOUT pin to 0. (Watchdog timer is set to enable
after reset.)
• Pulls up the CLK pin to 1.
• Sets the ALE pin to 0.

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TMP96C141AF
3.2 Memory Map
Figure 3.2 is a memory map of the TMP96C141AF.
Figure 3.2 Memory Map

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TMP96C141AF
3.3 Interrupts
The TLCS-900 interrupts are controlled by the CPU interrupt
mask flip-flop (IFF2 to 0) and the built-in interrupt controller.
The TMP96C141AF have altogether the following 23
interrupt sources:
A fixed individual interrupt vector number is assigned to
each interrupt source; six levels of priority (variable) can also
be assigned to each maskable interrupt. Non-maskable inter-
rupts have a fixed priority of 7.
When an interrupt is generated, the interrupt controller
sends the value of the priority of the interrupt source to the
CPU. When more than one interrupt is generated simulta-
neously, the interrupt controller sends the value of the highest
priority (7 for non-maskable interrupts is the highest) to the
CPU.The CPU compares the value of the priority sent with the
value in the CPU interrupt mask register (IFF2 to 0). If the value
is greater than that of the CPU interrupt mask register, the
interrupt is accepted. The value in the CPU interrupt mask reg-
ister (IFF2 to 0) can be changed using the EI instruction (con-
tents of the EI num/IFF<2:0> = num). For example,
programming EI 3 enables acceptance of maskable interrupts
with a priority of 3 or greater, and non-maskable interrupts
which are set in the interrupt controller. The DI instruction
• Interrupts from the CPU
…
3
(Software interrupts, privileged violations, and Illegal (undefined) instruction execution)
• Interrupts from external pins (NMI, INT0, and INT4 to 7)
…
6
• Interrupts from built-in I/Os
…
14
(IFF<2:0> = 7) operates in the same way as the EI 7 instruc-
tion. Since the priority values for maskable interrupts are 0 to 6,
the DI instruction is used to disable maskable interrupts to be
accepted. The EI instruction becomes effective immediately
after execution. (With the TLCS-90, the EI instruction becomes
effective after execution of the subsequent instruction.)
In addition to the general-purpose interrupt processing
mode described above, there is also a high-speed micro DMA
processing mode. High-speed micro DMA is a mode used by
the CPU to automatically transfer byte or word data. It enables
the CPU to process interrupts such as data saves to built-in I/Os
at high speed.
Figure 3.3 (1) is a flowchart showing overall interrupt
processing.

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TMP96C141AF
Figure 3.3 (1) Interrupt Processing Flowchart