Toshiba TXZ+ Series User manual

TXZ+ Family
TMPM4K Group(2)
Clock Control and Operation Mode
2021-06-15
Rev. 1.1
1 / 64
© 2020-2021
Toshiba Electronic Devices & Storage Corporation
2021-06
32-bit RISC Microcontroller
TXZ+ Family
TMPM4K Group(2)
Reference Manual
Clock Control and Operation Mode
(CG-M4K(2)-E)
Revision 1.1

TXZ+ Family
TMPM4K Group(2)
Clock Control and Operation Mode
2021-06-15
Rev. 1.1
2 / 64
Contents
Preface ................................................................................................................................................................. 6
Related documents ...................................................................................................................................................6
Conventions ..............................................................................................................................................................7
Terms and Abbreviations ..........................................................................................................................................9
1. Clock control and operation mode.............................................................................................................. 10
1.1. Outlines ............................................................................................................................................................10
1.2. Clock control ....................................................................................................................................................11
1.2.1. Clock type...................................................................................................................................................................11
1.2.2. The initial value by a reset action ...............................................................................................................................11
1.2.3. Clock System diagram................................................................................................................................................12
1.2.4. Warming-up function ..................................................................................................................................................13
1.2.4.1. The warming-up timer for a high speed oscillation ........................................................................................................13
1.2.4.2. The directions for a warming-up timer ...........................................................................................................................14
1.2.5. Clock multiplying circuit (PLL) for fsys ........................................................................................................................14
1.2.5.1. A PLL setup after reset release .....................................................................................................................................14
1.2.5.2. The formula and the example of a setting of a PLL multiplication value ........................................................................15
1.2.5.3. Change of the PLL multiplication value under operation................................................................................................16
1.2.5.4. PLL operation start / stop / switching procedure............................................................................................................17
(1) fc setup (PLL stop >>> PLL start) ..................................................................................................................17
(2) fc setup (conduct PLL >>> PLL stop).............................................................................................................17
1.2.6. System clock ..............................................................................................................................................................18
1.2.6.1. The setting method of a system clock ...........................................................................................................................19
(1) fosc setup (Internal oscillation >>> External oscillation) ................................................................................19
(2) fosc setup (Internal oscillation >>> External clock input) ...............................................................................20
(3) fosc setup (External oscillation/External clock input >>> Internal oscillation) ................................................20
1.2.7. Clock supply setting function ......................................................................................................................................21
1.2.8. Prescaler clock ...........................................................................................................................................................21
1.3. Operation mode ...............................................................................................................................................22
1.3.1. Details of an Operation mode.....................................................................................................................................22
1.3.1.1. The feature in each mode .............................................................................................................................................22
1.3.1.2. Transition to and Return from Low Power Consumption mode......................................................................................23
1.3.1.3. Selection of a Low Power Consumption mode ..............................................................................................................23
1.3.1.4. The peripheral function state in a Low Power Consumption mode ................................................................................24
1.3.2. Mode State Transition ................................................................................................................................................25
1.3.2.1. IDLE mode transition flow .............................................................................................................................................25
1.3.2.2. STOP1 mode transition flow..........................................................................................................................................26
1.3.3. Return from a Low Power Consumption mode...........................................................................................................27
1.3.3.1. The release source of a Low Power Consumption mode ..............................................................................................27
1.3.3.2. Warming-up at the release of Low Power Consumption mode ......................................................................................28
1.3.4. Clock operation by mode transition ............................................................................................................................29
1.3.4.1. NORMAL >>> IDLE >>> NORMAL Operation mode transition......................................................................................29
1.3.4.2. NORMAL >>> STOP1 >>> NORMAL Operation mode transition..................................................................................29
1.4. Explanation of Register....................................................................................................................................30
1.4.1. Register list.................................................................................................................................................................30

TXZ+ Family
TMPM4K Group(2)
Clock Control and Operation Mode
2021-06-15
Rev. 1.1
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1.4.2. Detail of Register........................................................................................................................................................31
1.4.2.1. [CGPROTECT] (CG write protection register) ...............................................................................................................31
1.4.2.2. [CGOSCCR] (Oscillation control register)......................................................................................................................31
1.4.2.3. [CGSYSCR] (System clock control register)..................................................................................................................32
1.4.2.4. [CGSTBYCR] (Standby control register) .......................................................................................................................33
1.4.2.5. [CGPLL0SEL] (PLL selection register for fsys)..............................................................................................................33
1.4.2.6. [CGWUPHCR] (High speed oscillation warming-up register).........................................................................................34
1.4.2.7. [CGFSYSMENA] (Supply and stop register A for fsysm)...............................................................................................34
1.4.2.8. [CGFSYSMENB] (Supply and stop register B for fsysm)...............................................................................................37
1.4.2.9. [CGFSYSENA] (Supply and stop register A for fsysh)...................................................................................................38
1.4.2.10. [CGFCEN] (Clock supply and stop register for fc) .......................................................................................................39
1.4.2.11. [CGSPCLKEN] (Clock supply and stop register for ADC and Debug circuit) ...............................................................39
1.5. Information according to product .....................................................................................................................40
1.5.1. [CGFSYSMENA] ........................................................................................................................................................40
1.5.2. [CGFSYSMENB] ........................................................................................................................................................41
1.5.3. [CGFSYSENA] ...........................................................................................................................................................42
1.5.4. [CGFCEN] ..................................................................................................................................................................42
2. Memory map ............................................................................................................................................... 43
2.1. Outlines ............................................................................................................................................................43
2.1.1. TMPM4KxFYA............................................................................................................................................................44
2.1.2. TMPM4KxFWA...........................................................................................................................................................45
2.2. Bus Matrix ........................................................................................................................................................46
2.2.1. Structure.....................................................................................................................................................................47
2.2.1.1. Single Chip Mode..........................................................................................................................................................47
2.2.1.2. Single Boot Mode ..........................................................................................................................................................48
2.2.2. Connection table.........................................................................................................................................................49
2.2.2.1. Connection of Memory related ......................................................................................................................................49
2.2.2.2. Connection of peripheral function..................................................................................................................................51
3. Reset and power supply control ................................................................................................................. 52
3.1. Outlines ............................................................................................................................................................52
3.2. Description of function and operation ..............................................................................................................52
3.2.1. Cold reset ...................................................................................................................................................................52
3.2.1.1. Reset by a Power On Reset Circuit (without using a RESET_N pin) .............................................................................53
3.2.1.2. Reset by a RESET_N pin ..............................................................................................................................................54
3.2.1.3. Continuation of reset by LVD.........................................................................................................................................56
3.2.2. Warm reset.................................................................................................................................................................57
3.2.2.1. Warm reset by RESET_N pin........................................................................................................................................57
3.2.2.2. Warm reset by LVD .......................................................................................................................................................57
3.2.2.3. Warm reset by other internal reset ................................................................................................................................57
3.2.3. Starting in Single Boot Mode ......................................................................................................................................58
3.2.3.1. Starting by the RESET_N pin ........................................................................................................................................58
3.2.3.2. Starting in Single Boot Mode when power supply is stable............................................................................................59
3.2.4. Power On Reset Circuit ..............................................................................................................................................60
3.2.4.1. Operation at the time of a power supply ........................................................................................................................60
3.2.4.2. Operation at the time of turn off.....................................................................................................................................60

TXZ+ Family
TMPM4K Group(2)
Clock Control and Operation Mode
2021-06-15
Rev. 1.1
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3.2.5. About turn on power supply after turn off....................................................................................................................61
3.2.6. After reset release ......................................................................................................................................................61
3.2.6.1. The reset factor and the reset range .............................................................................................................................62
4. Revision History .......................................................................................................................................... 63
RESTRICTIONS ON PRODUCT USE............................................................................................................... 64

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TMPM4K Group(2)
Clock Control and Operation Mode
2021-06-15
Rev. 1.1
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List of Figures
Figure 1.1 Clock system diagram............................................................................................................. 12
Figure 1.2 Mode State Transition............................................................................................................. 25
Figure 1.3 NORMAL >>> STOP1 >>> NORMAL Operation mode transition ......................................... 29
Figure 2.1 TMPM4KxFYA ........................................................................................................................ 44
Figure 2.2 TMPM4KxFWA ....................................................................................................................... 45
Figure 2.3 Single Chip Mode.................................................................................................................... 47
Figure 2.4 Single Boot Mode.................................................................................................................... 48
Figure 3.1 The reset operation by a Power On Reset Circuit.................................................................. 53
Figure 3.2 Reset operation by a RESET_N pin (1).................................................................................. 54
Figure 3.3 Reset operation by a RESET_N pin (2).................................................................................. 55
Figure 3.4 Reset operation by LVD reset................................................................................................. 56
Figure 3.5 Warm reset operation ............................................................................................................. 57
Figure 3.6 When the power supply is on, starting in Single Boot Mode by the RESET_N pin ............... 58
Figure 3.7 Starting in the Single Boot Mode when power supply is stable ............................................. 59
Figure 3.8 Power On Reset Circuit .......................................................................................................... 60
List of Tables
Table 1.1 Details of [CGPLL0SEL]<PLL0SET[23:0]> setup.................................................................... 15
Table 1.2 PLL correction (example)......................................................................................................... 15
Table 1.3 PLL0SET setting value (example) ........................................................................................... 16
Table 1.4 Clock domains of CPU and peripherals................................................................................... 18
Table 1.5 Time interval for changing System clock ................................................................................. 18
Table 1.6 Example of operating frequency .............................................................................................. 18
Table 1.7 Operating frequency examples of High speed and Middle speed system clocks................... 19
Table 1.8 Time interval for changing prescaler clocks ............................................................................ 21
Table 1.9 Low Power Consumption mode selection................................................................................ 23
Table 1.10 Block operation status in each Low Power Consumption mode ........................................... 24
Table 1.11 Release source list................................................................................................................. 27
Table 1.12 Warming-up............................................................................................................................ 28
Table 1.13 [CGFSYSMENA] register corresponding to each product..................................................... 40
Table 1.14 [CGFSYSMENB] register corresponding to each product..................................................... 41
Table 1.15 [CGFSYSENA] register corresponding to each product........................................................ 42
Table 1.16 [CGFCEN] register corresponding to each product............................................................... 42
Table 2.1 Single Chip Mode..................................................................................................................... 49
Table 2.2 Single Boot Mode..................................................................................................................... 49
Table 2.3 Single Chip Mode..................................................................................................................... 50
Table 2.4 Single Boot Mode..................................................................................................................... 50
Table 2.5 Connection of peripheral function ............................................................................................ 51
Table 3.1 The reset factor and the range initialized................................................................................. 62
Table 4.1 Revision History ....................................................................................................................... 63

TXZ+ Family
TMPM4K Group(2)
Clock Control and Operation Mode
2021-06-15
Rev. 1.1
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Preface
Related documents
Document name
Arm®documentation set for the Arm Cortex®-M4
Exception
Oscillation Frequency Detector
Voltage Detection Circuit
Clock Selective Watchdog Timer
Flash Memory
The datasheet of each product (Electrical Characteristics)

TXZ+ Family
TMPM4K Group(2)
Clock Control and Operation Mode
2021-06-15
Rev. 1.1
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Conventions
●Numeric formats follow the rules as shown below:
Hexadecimal: 0xABC
Decimal: 123 or 0d123 – Only when it needs to be explicitly shown that they are decimal numbers.
Binary: 0b111 – It is possible to omit the "0b" when the number of bit can be distinctly understood from a
sentence.
●"_N" is added to the end of signal names to indicate low active signals.
●It is called "assert" that a signal moves to its active level, "deassert" to its inactive level.
●When two or more signal names are referred, they are described like as [m: n].
Example: S[3: 0] shows four signal names S3, S2, S1 and S0 together.
●The characters surrounded by [ ] defines the register.
Example: [ABCD]
●"n" substitutes suffix number of two or more same kind of registers, fields, and bit names.
Example: [XYZ1], [XYZ2], [XYZ3] [XYZn]
●"x" substitutes suffix number or character of units and channels in the Register List.
In case of unit, "x" means A, B, and C ...
Example: [ADACR0], [ADBCR0], [ADCCR0] [ADxCR0]
In case of channel, "x" means 0, 1, and 2 ...
Example: [T32A0RUNA], [T32A1RUNA], [T32A2RUNA] [T32AxRUNA]
●The bit range of a register is written like as [m: n].
Example: Bit[3: 0] expresses the range of bit 3 to 0.
●The configuration value of a register is expressed by either the hexadecimal number or the binary number.
Example: [ABCD]<EFG> =0x01 (hexadecimal), [XYZn]<VW> =1 (binary)
●Word and Byte represent the following bit length.
Byte: 8 bits
Half word: 16 bits
Word: 32 bits
Double word: 64 bits
●Properties of each bit in a register are expressed as follows:
R: Read only
W: Write only
R/W: Read and Write are possible
●Unless otherwise specified, register access supports only word access.
●The register defined as reserved must not be rewritten. Moreover, do not use the read value.
●The value read from the bit having default value of "-" is unknown.
●When a register containing both of writable bits and read-only bits is written, read-only bits should be
written with their default value, In the cases that default is "-", follow the definition of each register.
●Reserved bits of the Write-only register should be written with their default value.
In the cases that default is "-", follow the definition of each register.
●Do not use read-modified-write processing to the register of a definition which is different by writing and
read out.

TXZ+ Family
TMPM4K Group(2)
Clock Control and Operation Mode
2021-06-15
Rev. 1.1
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All other company names, product names, and service names mentioned herein may be trademarks of their
respective companies.
***********************************************************************************************************************
Arm, Cortex and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US
and/or elsewhere. All rights reserved.
***********************************************************************************************************************

TXZ+ Family
TMPM4K Group(2)
Clock Control and Operation Mode
2021-06-15
Rev. 1.1
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Terms and Abbreviations
Some of abbreviations used in this document are as follows:
ADC Analog to Digital Converter
A-ENC32 Advanced Encoder input Circuit (32-bit)
A-PMD Advanced Programmable Motor Control Circuit
A-VE+ Advanced Vector Engine Plus
CG Clock Control and Operation Mode
CRC Cyclic Redundancy Check
D-Bus DCode memory interface
DMAC Direct Memory Access Controller
DNF Digital Noise Filter
EI2C I2C Interface Version A
EHOSC External High speed Oscillator
fsys frequency of SYSTEM Clock
IA(INTIF) Interrupt control register A
IB(INTIF) Interrupt control register B
I-Bus ICode memory interface
IHOSC Internal High speed Oscillator
IMN Interrupt Monitor
INT Interrupt
I2C Inter-Integrated Circuit
LVD Voltage Detection Circuit
NBDIF Non Break Debug Interface
NMI Non-Maskable Interrupt
OFD Oscillation Frequency Detector
OPAMP Operational Amplifier
POR Power On Reset Circuit
PORF Power On Reset Circuit for FLASH and debug
RAMP RAM Parity
RLM Low speed oscillation / power supply control / reset
S-Bus System interface
SIWDT Clock Selective Watchdog Timer
TRGSEL Trigger Selection Circuit
TRM Trimming Circuit
TSPI Serial Peripheral Interface
T32A 32-bit Timer Event Counter
UART Universal Asynchronous Receiver Transmitter

TXZ+ Family
TMPM4K Group(2)
Clock Control and Operation Mode
2021-06-15
Rev. 1.1
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1. Clock control and operation mode
1.1. Outlines
The clock/mode control block can select a clock gear and prescaler clock, and set the warming-up of oscillator and
so on.
Furthermore, it has Normal mode and a low power consumption mode in order to reduce power consumption
using mode transition.
Functions related to a clock are as follows.
●System clock control
●Prescaler clock control

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TMPM4K Group(2)
Clock Control and Operation Mode
2021-06-15
Rev. 1.1
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1.2. Clock control
1.2.1. Clock type
This section shows a list of clocks:
EHCLKIN : The high speed clock input from the external
fosc : A clock generated in the internal oscillation circuit or input from the X1 and X2 pins after being
selected by [CGOSCCR]<OSCSEL>.
fPLL : A clock multiplied with PLL0
fc : A clock selected by [CGPLL0SEL]<PLL0SEL> (High speed clock)
fsysh : A high speed system clock selected by [CGSYSCR]<GEAR[2:0]>
fsysm : A middle speed system clock selected by [CGSYSCR]<GEAR[2:0]><MCKSEL[1:0]>
ΦT0h : A high speed clock selected by [CGSYSCR]<PRCK[3:0]> (High speed prescaler clock)
ΦT0m : A middle speed clock selected by [CGSYSCR]<PRCK[3:0]> <MCKSEL[1:0]> (Middle speed
prescaler clock)
fIHOSC1 : A clock generated with the internal high speed oscillator1
fIHOSC2 : A clock generated with the internal high speed oscillator2
ADCLK : A conversion clock for ADC
TRCLKIN : A clock for tracing facilities of a debugging circuit (Trace or SWV)
Note: The high speed system clock and the middle speed system clock are collectively called System clock
(fsys). And the high speed prescaler clock and the middle speed prescaler clock are collectively called
Prescaler clock (ΦT0).
1.2.2. The initial value by a reset action
A clock setup is initialized to the following states by a reset action.
External high speed oscillator : Stop
Internal high speed oscillator1 : Oscillation
Internal high speed oscillator2 : Stop
PLL (multiplying circuit) : Stop
Gear clock : fc (no frequency dividing)

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TMPM4K Group(2)
Clock Control and Operation Mode
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Rev. 1.1
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1.2.3. Clock System diagram
The figure below shows a clock system diagram.
PLL0
[CGOSCCR]<IHOSC2EN>
[CGOSCCR]<EOSCEN>
[CGOSCCR]<IHOSC1EN>
High speed
Warming-up timer
[CGWUPHCR]<WUON>
[CGWUPHCR]<WUPT[15:4]>
[CGWUPHCR]
<WUCLK>
[CGOSCCR]
<OSCSEL>
X2
X1
OFD
SIWDT
fosc
[CGPLL0SEL]
<PLL0SEL>
fc
1/2
1/4
1/8
1/16
[CGSPCLKEN]
<ADCKEN[3:0]>
[CGFCEN]
<FCIPEN[31:0]>
Peripheral function using fsysm
Peripheral function using fc
Peripheral function using fsysh
ADC
fc
(To fsys and ΦT0 generation)
1/512
1/256
1/128
1/64
1/32
[CGSYSCR]
<PRCK[3:0]>
fc
1/2
1/4
1/2
1/4
[CGSYSCR]
<GEAR[2:0]>
[CGSYSCR]
<MCKSEL[1:0]>
Peripheral function using ΦT0m
Peripheral function using ΦT0h
[CGFSYSMENA]
<IPMENA[31:0]>
[CGFSYSMENB]
<IPMENB[31:0]>
[CGFSYSENA]
<IPENA[31:0]>
CPU
[CGSPCLKEN]
<TRCKEN>
fsysm
fsysh
ΦT0m
ΦT0h
1/64
ADCLK
SysTick
TRCK
TARGET
EHOSC
REF
f
PLL
fsysh
fsysm
EHCLKIN
fosc
fc
CRC, RAMP(ch0)
N/A
TSPI, UART, T32A
PORT, TSPI, UART, I2C, EI2C,
T32A, ADC, OPAMP, A-ENC32,
A-PMD, A-VE+, RAMP(ch1), OFD,
TRM, TRGSEL, DMAC, NBDIF,
SIWDT, Flash(SFR)
DNF, OFD(Target clock)
fsysh
Code Flash, Data Flash, Boot ROM,
RAM0/1, INTIF(IB, IMN)
RAM2, LVD, INTIF(IA), RLM
1/4
DEBUG
TRCLKIN
Internal
High speed
oscillator1
External
High speed
oscillator
Internal
High speed
oscillator2
Figure 1.1 Clock system diagram

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TMPM4K Group(2)
Clock Control and Operation Mode
2021-06-15
Rev. 1.1
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1.2.4. Warming-up function
A warming-up function starts the warming-up timer for high speed oscillator automatically to secure the
oscillation stable time when the STOP1 mode is released.
It is also available as a count-up timer which uses the warming-up timer for high speed oscillator to secure the
stability of an external oscillator or an internal oscillator.
This chapter explains the setting method to the register for warming-up timers, and the case where it is used as a
count-up timer. The detailed explanation at the time of STOP1 mode release, refer to "1.3.3.2. Warming-up at the
release of Low Power Consumption mode".
1.2.4.1. The warming-up timer for a high speed oscillation
A 16-bit up-timer is built in as a warming-up timer only for a high speed oscillation. Also when setting it before
changes to the STOP1 mode, calculate with the following formula and set [CGWUPHCR]<WUPT[15:4]> to the
upper 12 bits of the result. Lower 4bits are ignored.
<Formula>
(Using external high speed oscillator)
Warming-up timer setting value (16 bits)
= (warming-up time (s) / clock period (s)) - 16
(Example) When 5 ms of warming-up time is set up with 10 MHz (100 ns of clock periods) of oscillators
Warming-up timer setting value (16 bits) = (5ms / 100ns) - 16
= 50000 - 16
= 49984
= 0xC340
Since upper 12 bits are used, set the register as follows.
[CGWUPHCR]<WUPT[15:4]> = 0xC34
(Using internal high speed oscillator1)
Warming-up timer setting value (16 bits)
= (warming-up time (s) – 63.3(µs)) / clock period (s) - 41
(Example) When 163.4 µs of warming-up time is set up with 10 MHz (100 ns of clock periods) of oscillators
Warming-up timer setting value (16 bits) = ((163.4µs – 63.3µs) / 100ns) - 41
= (100.1µs – 100ns) - 41
= 960
= 0x03C0
Since upper 12 bits are used, set the register as follows.
[CGWUPHCR]<WUPT[15:4]> = 0x03C
The setting range is 0x03C ≤<WUPT[15:4]> ≤0xFFF, warming-up time is set from 163.4 µs to 6.6194 ms.

TXZ+ Family
TMPM4K Group(2)
Clock Control and Operation Mode
2021-06-15
Rev. 1.1
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1.2.4.2. The directions for a warming-up timer
The directions for a warming-up function are explained.
(1) Selection of a clock
In a high speed oscillation, the clock classification (internal oscillation/external oscillation) counted with a
warming-up timer is selected by [CGWUPHCR]<WUCLK>.
(2) Calculation of warming-up timer setting value
The warming-up time can set any value to the timer for a high speed oscillation. Please compute and set up
from the formula.
(3) The start of warming-up, and a termination Confirmation
When software (command) performs the start of warming-up, starting warming-up count is carried out by
setting [CGWUPHCR]<WUON> to "1". Termination is confirmed with [CGWUPHCR]<WUEF> that
becomes from "1" to "0". "1" shows that it is warming-up and "0" shows termination. After a counting end,
a timer is reset and returns to an initial state.
It is not forced to terminate, although "0" is written to [CGWUPHCR]<WUON> during timer operation.
Writing "0" is disregarded.
Note: Since it is operating with the oscillating clock, a warming-up timer includes an error, when Oscillation
frequency has fluctuation. Therefore, It serves an approximate time.
1.2.5. Clock multiplying circuit (PLL) for fsys
The clock multiplying circuit outputs the fPLL clock (maximum 160MHz) multiplied by the optimum condition for
the frequency (6 MHz to 12 MHz) of the output clock fosc of the high speed oscillator.
So, it is possible to make input frequency to an oscillator low and to make an internal clock high speed by this
circuit.
1.2.5.1. A PLL setup after reset release
The PLL is disabled after reset release.
In order to use the PLL, set [CGPLL0SEL]<PLL0SET[23:0]> to a multiplication value while [CGPLL0SEL]
<PLL0ON> is "0". Then wait until approximately 100 µs has elapsed as a PLL initial stabilization time, and set
<PLL0ON> to "1" to start PLL operation. After that, to use fPLL clock which is multiplied fosc, wait until
approximately 400 µs has elapsed as a lock up time. Then set [CGPLL0SEL]<PLL0SEL> to "1".
Note that a time is required until PLL operation becomes stable using the warming-up function, etc.

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TMPM4K Group(2)
Clock Control and Operation Mode
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Rev. 1.1
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1.2.5.2. The formula and the example of a setting of a PLL multiplication value
The details of the items of [CGPLL0SEL]<PLL0SET[23:0]> which set up a PLL multiplication value are shown
below.
Table 1.1 Details of [CGPLL0SEL]<PLL0SET[23:0]> setup
The items of PLL0SET
Function
[23:17]
Correction
value setup
The quotient of fosc/450000 (integer). For details, refer to
Table 1.2.
[16:14] fosc setup
000: 6 < fosc ≤ 7 (unit: MHz)
001: 7 < fosc ≤ 8
010: 8 < fosc ≤ 10
011: 10 < fosc ≤ 12
100 to 111: Reserved
[13:12] Dividing setup
00: Reserved
01: Dividing by 2 (×1/2)
10: Dividing by 4 (×1/4)
11: Dividing by 8 (×1/8)
[11:8]
Fraction part
Multiplication
setup
0000: 0.0000
0001: 0.0625
0010: 0.1250
0011: 0.1875
0100: 0.2500
0101: 0.3125
0110: 0.3750
0111: 0.4375
1000: 0.5000
1001: 0.5625
1010: 0.6250
1011: 0.6875
1100: 0.7500
1101: 0.8125
1110: 0.8750
1111: 0.9375
[7:0]
Integer part
Multiplication
setup
0x00: 0
0x01: 1
0x02: 2
:
0xFD: 253
0xFE: 254
0xFF: 255
Note: A multiplication value is the total of <PLL0SET[7:0]> (integer part) and <PLL0SET[11:8]>
(fraction part).
fPLL is denoted by the following formulas.
fPLL = fosc × ([CGPLL0SEL]<PLL0SET[7:0]> + [CGPLL0SEL]<PLL0SET[11:8]>) ×
([CGPLL0SEL]<PLL0SET[13:12]>)
Note1: The absolute value of frequency accuracy is not guaranteed.
Note2: There is no Linearity in the frequency by the Fraction part Multiplication setup.
Note3: fPLL ≤(Maximum Operating Frequency)
Table 1.2 PLL correction (example)
fosc (MHz)
<PLL0SET[23:17]>
(a decimal, an integral value)
6.00
14
8.00
18
10.00
23
12.00
27
The PLL correction value can be calculated below.
fosc = 10.0 MHz, 10.0/0.45 = 22.22 23; A fraction part is rounded up.

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Clock Control and Operation Mode
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The main examples of a setting of [CGPLL0SEL]<PLL0SET[23:0]> are shown below.
It multiplies by PLL, and dividing is carried out and the target Clock frequency (fPLL) is generated for input
frequency (fosc).
A dividing value is chosen from 1/2, 1/4, and 1/8.
Moreover, set up the frequency after multiplication in the following ranges.
200 MHz ≤(fosc × Multiplication value) ≤400 MHz
Table 1.3 PLL0SET setting value (example)
fosc (MHz)
Multiplication
value
Dividing
value
fPLL (MHz) <PLL0SET[23:0]>
6.00
53.3125
1/2
159.94
0x1C1535
8.00
40.0000
1/2
160
0x245028
10.00
32.0000
1/2
160
0x2E9020
12.00
26.6250
1/2
159.75
0x36DA1A
1.2.5.3. Change of the PLL multiplication value under operation
To change the setting of a PLL multiplication during PLL multiplication clock operation, set [CGPLL0SEL]
<PLL0SEL> to "0" that does not use a PLL multiplication clock. And [CGPLL0SEL]<PLL0ST> =0 is read to
confirm that a multiplication clock setting is not used, then, [CGPLL0SEL]<PLL0ON> is set to "0", and PLL is
stopped.
Then, the multiplication value of [CGPLL0SEL]<PLL0SET[23:0]> is changed, as reset time of PLL, after about
100 µs has elapsed, [CGPLL0SEL]<PLL0ON> is set to "1", and operation of PLL is started.
Then, [CGPLL0SEL]<PLL0SEL> is set to "1" after lock-up time (about 400µs) has elapsed.
Finally, [CGPLL0SEL]<PLL0ST> is read and it checks having changed.

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1.2.5.4. PLL operation start / stop / switching procedure
(1) fc setup (PLL stop >>> PLL start)
As an fc setup, the example of switching procedure from the PLL stop state to the PLL operation state is as
follows.
<< The state before switching >>
[CGPLL0SEL]
<PLL0ON> =0 Stops the PLL operation for fsys.
[CGPLL0SEL]<PLL0SEL> =0 Selects the setting of the PLL for fsys to "PLL is unused (fosc)".
[CGPLL0SEL]<PLL0ST> =0 Indicates the status of the PLL for fsys to "PLL is unused (fosc)".
[CGSYSCR]<MCKSEL> =00
Ratios of (High speed system clock vs Middle speed system clock) and
(High speed prescaler clock vs Middle speed system clock) are 1:1.
<< The example of switching procedure >>
1
[CGSYSCR]<MCKSEL[1:0]> = 01 or
1*
Ratios of (High speed system clock vs Middle speed system clock) and
(High speed prescaler clock vs High speed system clock) are changed.
2
[CGSYSCR] <MCKSELGST>
<MCKSELPST> is read
Wait until they become the values set at Step 1.
3
[CGPLL0SEL]
<PLL0SET[23:0]> =0xX A PLL multiplication value setup is chosen.
4 Wait 100 µs or more. Latency time after a multiplication setup
5
[CGPLL0SEL]
<PLL0ON> =1 PLL operation for fsys is carried out to an oscillation.
6 Wait 400 µs or more. PLL output clock stable latency time
7 [CGPLL0SEL]<PLL0SEL> =1 PLL selection for fsys is carried out to PLL use (fPLL).
8 [CGPLL0SEL]<PLL0ST> is read It waits until the PLL selection status for fsys becomes PLL use (fPLL) (=1).
Note1: 1 and 2 are executed when the ratio of the system clock should be changed.
Note2: 3 to 6 are unnecessary when the state before switching is [CGPLL0SEL]<PLL0ON> = 1.
When changing from the state where the PLL output clock is stable, it can be changed to the PLL
operation state by execution of only 7 and 8.
(2) fc setup (conduct PLL >>> PLL stop)
As an fc setup, the example of switching procedure from the PLL operation state to a PLL stop state is as follows.
<< The state before switching >>
[CGPLL0SEL]<PLL0ON> =1 Sets the PLL for fsys to oscillate.
[CGPLL0SEL]<PLL0SEL> =1 Selects the PLL for fsys to "PLL is used (fPLL)".
[CGPLL0SEL]
<PLL0ST> =1
Indicates the status of the PLL for fsys to "PLL is used (f
PLL
)".
<< The example of switching sequence >>
1
[CGPLL0SEL]
<PLL0SEL> =0
Selects the PLL for fsys to "PLL is unused (fosc)".
2 [CGPLL0SEL]<PLL0ST> is read
Waits until the status of the PLL for fsys becomes "PLL is unused (fosc)
(=0)".
3 [CGPLL0SEL]
<PLL0ON> =0
Sets the PLL operation for fsys to stop.

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1.2.6. System clock
An internal high speed oscillation clock or external high speed oscillation clock (connected oscillator or clock
input) can be used as a source of system clock.
The system clock consists of "High speed system clock (fsysh)(maximum 160MHz)" for high speed operation and
"Middle speed system clock (fsysm)(maximum 80MHz)" which is generated by dividing High speed system clock.
Middle speed system clock is used by peripheral function to save power dissipation without degrading CPU
performance. The clock domains of the peripheral function can be checked in Table 1.4.
High speed system clock can be generated by dividing fc using [CGSYSCR]<GEAR[2:0]> (Clock gear). And
Middle speed system clock is generated by dividing the high speed system clock using [CGSYSCR]
<MCKSEL[1:0]>. Although a setting can be changed during operation, after register writing before the clock
actually changes, a time interval shown in Table 1.5 is required. The completion of the clock change should be
checked by [CGSYSCR]<GEARST[2:0]> <MCKSELGST[1:0]>.
Table 1.4 Clock domains of CPU and peripherals
Clock domain
Block
High speed system clock
CPU, Code Flash, Data Flash, Boot ROM, RAM0/1, CG,
INTIF(IB, IMN), CRC, RAMP(ch0)
Middle speed system clock
DMAC, NBDIF, SIWDT, UART, TSPI, I2C, EI2C, T32A, ADC,
OPAMP, PORT, A-PMD, A-ENC32, A-VE+, INTIF(IA),
DNF, LVD,
TRM, Flash(SFR), OFD, RAMP(ch1) , RLM, TRGSEL, RAM2
Table 1.5 Time interval for changing System clock
System clock
High speed (fsysh)
Middle speed (fsysm)
fsys 16 fc cycles at maximum 16 fc cycles at maximum
fsys/2 - 32 fc cycles at maximum
fsys/4 - 64 fc cycles at maximum
Note1: The clock gear and the system clock should not be changed while the peripheral function such as
the timer/counter is operating.
Note2: An access between High speed system clock domain and Middle speed system clock domain
cannot be done when the system clock is changing.
The table below shows the example of operating frequency by the clock gear ratio (1/1 to 1/16) to the frequency fc
set up with oscillation frequency, a PLL multiplication value, etc.
Table 1.6 Example of operating frequency
External
Oscillation
(MHz)
External
Clock
input
(MHz)
Built-in
oscillation
IHOSC1
(MHz)
PLL
Multiplication
value
(after dividing)
Maximum
Frequency
(fc)(MHz)
Operating frequency (MHz)
by the clock gear ratio
PLL=ON
Operating frequency (MHz)
by the clock gear ratio
PLL=OFF
1/1
1/2
1/4
1/8
1/16
1/1
1/2
1/4
1/8
1/16
6 6 - 26.66 159.94 159.94 79.97 39.99 19.99 10.00 6 3 1.5 - -
8 8 - 20 160 160 80 40 20 10 8 4 2 1 -
10 10 10 16 160 160 80 40 20 10 10 5 2.5 1.25 -
12 12 - 13 156 156 78 39 19.5 9.75 12 6 3 1.5 -

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Table 1.7 Operating frequency examples of High speed and Middle speed system clocks
High speed
system clock
fsysh (MHz)
Middle speed system clock
fsysm (MHz)
1/1
1/2
1/4
160 - 80 40
80 80 40 20
Note: The maximum frequency of Middle speed system clock is 80 MHz.
1.2.6.1. The setting method of a system clock
(1) fosc setup (Internal oscillation >>> External oscillation)
As a fosc setup, the example of switching procedure to the external high speed oscillator (EHOSC) from an
internal high speed oscillator1 (IHOSC1) is shown below.
<< The state before switching >>
[CGOSCCR]
<IHOSC1EN> =1
An internal high speed oscillator1 oscillates.
[CGOSCCR]<OSCSEL> =0
The high speed oscillation selection for fosc is an internal high speed
oscillator1 (IHOSC1).
[CGOSCCR]<OSCF> =0
The high speed oscillation selection status for fosc is an internal high
speed oscillator1 (IHOSC1).
An oscillator is connected to X1 / X2 pin. Do not connect any devices except a resonator.
<< The example of switching procedure >>
1
[PHPDN]<bit[1:0]> =00
[PHIE]<bit[1:0]> =00
Disable the pull-down resistors of X1 and X2 pins.
Disable input control of X1 and X2 pins.
2 [CGOSCCR]<EOSCEN[1:0]> =01
It is an external high speed oscillator (EHOSC) about selection of an
external oscillation of operation.
3
[CGWUPHCR]<WUCLK> =1
[CGWUPHCR]<WUPT[15:4]> =
arbitrary value
It is the external high speed oscillator (EHOSC) about high speed
oscillation warming-up clock selection.
A warming-up timer setting value is set to oscillator stable time.
4 [CGWUPHCR]<WUON> =1 High speed oscillation warming-up is started.
5 [CGWUPHCR]<WUEF> is read.
It waits until it becomes the termination of high speed oscillation
warming-up (= 0).
6 [CGOSCCR]<OSCSEL> =1
It is high speed oscillation selection for fosc to the external high speed
oscillator (EHOSC).
7 [CGOSCCR]<OSCF> is read
It waits until the high speed oscillation selection status for fosc becomes
external high speed oscillator (=1).
8
[CGOSCCR]
<IHOSC1EN> =0
An internal high speed oscillator1 is suspended.

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(2) fosc setup (Internal oscillation >>> External clock input)
As a fosc setup, the example of switching procedure to the external clock input (EHCLKIN) from an internal
oscillator1(IHOSC1) is shown below.
<< The state before switching >>
[CGOSCCR]
<IHOSC1EN> =1 An internal high speed oscillator1 oscillates.
[CGOSCCR]<OSCSEL> =0
The high speed oscillation selection for fosc is an internal high speed
oscillator1 (IHOSC1).
[CGOSCCR]<OSCF> =0
The high speed oscillation selection status for fosc is an internal high
speed oscillator1 (IHOSC1).
Clock into to EHCLKIN Input in the proper voltage range.
<< The example of switching procedure >>
1
[PHPDN]<bit[0]> =0
[PHIE]<bit[0]> =1
Disable the pull-down resistor of X1/EHCLKIN pin.
Enable the input control of X1/EHCLKIN pin.
2 [CGOSCCR]<EOSCEN[1:0]> =10
Selection of an external high speed oscillation of operation is carried out
to an external clock input (EHCLKIN).
3 [CGOSCCR]<OSCSEL> =1 It is high speed oscillation selection for fosc to an external clock.
4 [CGOSCCR]<OSCF> is read
It waits until the high speed oscillation selection status for fosc becomes
external high speed oscillator (=1).
5
[CGOSCCR]
<IHOSC1EN> =0
An internal high speed oscillator1 is suspended.
(3) fosc setup (External oscillation/External clock input >>> Internal oscillation)
As a fosc setup, the example of switching procedure to the internal high speed oscillator1 (IHOSC1) from an
external high speed oscillator (EHOSC) Operation State or an external clock input (EHCLKIN) Operation State is
shown below.
<< The state before switching >>
[CGOSCCR]<EOSCEN[1:0]> = 01 or 10
Selection of an external oscillator of operation is an external high speed
oscillator (EHOSC) or external clock input.
[CGOSCCR]<OSCSEL> =1
The high speed oscillation selection for fosc is the external high speed
oscillator (EHOSC).
[CGOSCCR]<OSCF> =1
The high speed oscillation selection status for fosc is the external high
speed oscillator (EHOSC).
<< The example of switching procedure >>
1 [CGWUPHCR]<WUCLK>=0
Set the warming-up clock selection to internal high speed oscillator1
(IHOSC1).
2 [CGWUPHCR]<WUPT[15:4]>=0x03C
Set the high speed oscillation warming-up timer setting value of 163.4 µs
(=0x03C) or more.
3
[CGOSCCR]
<IHOSC1EN> = 1 An internal high speed oscillator1 is oscillated.
4
[CGWUPHCR]
<WUON> = 1
Start the high speed oscillation warming-up timer
5
[CGWUPHCR]
<WUEF> is read
Wait until an warming-up timer status flag becomes ends(=1).
6 [CGOSCCR]<OSCSEL> = 0
Set the high speed oscillation selection for fosc to internal high speed
oscillator1 (IHOSC1).
7 [CGOSCCR]<OSCF> is read
It waits until the high speed oscillation selection status for fosc becomes
an internal high speed oscillator1 (=0).
8 [CGOSCCR]<EOSCEN[1:0]> = 00 Set the selection of an external high speed oscillator operation to unused.