onsemi AR0823-IBGA116 User manual

EVAL BOARD USER’S MANUAL
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©Semiconductor Components Industries, LLC, 2023
March, 2023 − Rev. 0 1Publication Order Number:
EVBUM2860/D
AR0823-IBGA116
Evaluation Board User's
Manual
EVBUM2860/D
EVALUATION BOARD OVERVIEW
The evaluation boards are designed to demonstrate the features of
onsemi’s image sensor products. This headboard is intended to plug
directly into the Demo3 system. Test points and jumpers on the board
provide access to the clock, I/O’s, and other miscellaneous signals.
FEATURES
•Clock Input
♦Default − 27 MHz Crystal Oscillator
♦Optional − Demo3 Controlled Mclk
•Two Wire Serial Interface
♦Selectable Base Address
•4 Lane MIPI / HiSPi (High Speed Serial Pixel) Interface
•RoHS Compliant
F
igure 1. AR0823 iBGA116 Evaluation Boar
d

EVBUM2860/D
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BLOCK DIAGRAM
Figure 2. Block Diagram

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HARDWARE DESCRIPTION
•Data, Control & Power connector – 52 pins (J1):
Part Number: QFS−026−04.25−L−D−A−RT1
Serial, I2C, FBCLK, MCLK, POWER, RST, SHUTDOWN STEST and GPIO’s are interfaced with Demo3 baseboard
using this connector.
Table 1. J1 CONNECTOR PINOUT
Pin. No Dir Function Pin. No Dir Function
1 O H_M_DATA1_P 2 O H_M_DATA2_P
3 O H_M_DATA1_N 4 O H_M_DATA2_N
5 O DEMO_FB_CLK 6 O H_M_DATA3_P
7 − NC 8 O H_M_DATA3_N
9 − NC 10 − NC
11 − NC 12 − NC
13 − NC 14 − NC
15 P +VDDIO_LS 16 − NC
17 − NC 18 − NC
19 − NC 20 − NC
21 − NC 22 − NC
23 − NC 24 − NC
25 − NC 26 Bi S_GPIO4
27 I S_TEST 28 Bi S_GPIO0
29 − NC 30 Bi S_GPIO2
31 I HB_RST_L 32 Bi S_GPIO3
33 Bi S_GPIO1 34 − NC
35 − NC 36 − NC
37 Bi DEMO_SDA 38 P +2V8_VAA_HB
39 P +5V0_HB 40 − NC
41 − NC 42 P +1V8_HB
43 I DEMO_SCL 44 I HB_MCLK
45 − NC 46 P +1V2_HB
47 P +3V3_HB 48 P +2V8_VDDIO_HB
49 O H_M_DATA0_P 50 O H_M_CLK_N
51 O H_M_DATA0_N 52 O H_M_CLK_P

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BOARD TOP AND BOTTOM VIEW
SADDR0
SADDR2
SADDR1
P49
P18
LED D1
Baseboard Connector J1
RESET Switch SW1
LED P15
FLASH/GPIO0 P7
SHUTTER/GPIO1
GPIO2 P10
P8
TRIGGER/GPIO3 P13
GPIO4 P17
GPIO5 P37
VAA−PLL Sel P1
VDDIO & VDDIO_LS Sel P16
TEST P47
ATEST TS1 Sel P3
ATEST TS2 Sel P2
CLK Sel P20
ATEST4 P43
ATEST3 P42
ATEST2 P41
ATEST1 P40
P51
P50
VDD−SLVS Sel
MULTICAM SLAVE CONN P25
MULTICAM MASTER CONN P26
SHUTDOWN P23
I2C DEBUG P24
EEPROM ADDR Sel P27
Figure 3. Top View of Evaluation Board
Figure 4. Bottom View of Evaluation Board

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JUMPER PIN LOCATIONS
The jumpers on headboards start with Pin 1 on the leftmost side of the pin. Grouped jumpers increase in pin size with each
jumper added.
Pin 1
Pin 1 Pins 1−4
Pins 5 and 6 Pins 7 and 8 Pins 9 and 10 Pins 1 and 2 Pins 3 and 4
Figure 5. Pin Locations for a Single Jumper. Pin 1 is Located at the Leftmost Side and Increases as it Moves to
the Right.
Figure 6. Pin Locations and Assignments of Grouped Jumpers Left to Right
Pins 1 and 2
Pins 3 and 4
Pins 5 and 6
Pins 7 and 8
Pins 9 and 10
Pin 1
Figure 7. Pin Locations and Assignments of Grouped Jumpers Top to Bottom