PeakTech 1235 User manual

PeakTech
®
1235
Operation manual
32-Chanel Logic Analyser

1. Brief Introduction
Today has been a digital information age. Compared with analog technique, the
transmission and measurement of information is much different. Numerous data
channels transmit simultaneously in the spatial distribution while data code flows
are built according to certain format in the time distribution. The data code flows
are the data words taking discrete time as independent variable but not the
analog waveform taking continuous time as independent variable. Some important
parameters in analog signal analysis are not so important in digital signal
analysis. For instances, the digital signal analysis of voltage pay much attention
to voltage higher or less than some threshold level; for the analysis of time, only
the relative relations among the digital signals are noticed. So the traditional
testing device (voltmeter, oscilloscope, etc.) can not measure and analyze digital
system effectively, even not meet the requirements of circuit design and
debugging in digital system. In such a case, Logic analyzer, a new-type data
measuring instrument is manufactured to observe and measure the digital signals
in digital information processing. Some special problems of designing and
debugging in digital system are difficult to find and solve without the logic
analyzer, such as transmission delay, competition risk and burr interference. At
present, digital circuit and bus technique are used in many apparatuses. In order
to analyze and validate the result of information processing, the logic analyzer
must be used to find out the error in programming and running, measure and
compare the state of digital logic circuit. With the rapid development of digital
technique, using logic analyzer to analyze and solve the problems in digital circuit
should be mastered. But the logic analyzer in present market is so complicated to
understand and operate for teaching in universities and colleges. It is impossible
to purchase a batch for high price. So a popular logic analyzer with basic
necessary function, simple operation and appropriate price must be selected.
PeakTech
®
1235 Logic Analyzer is such a practical measuring instrument meeting
the above requirements in data field.
2. Prepare for use
2.1. Check up
Open the packing case and check whether the appearance of the instrument is
intact, accessories are all there. If the package damaged severely, please don’t
open until consult with the departments concerned.
Packing list:
Name Amount
PeakTech
®
1235 logic analyzer 1
User’s guide 1
3-core power cable 1
50 wires cables and connector 2
Input transferring boxes 2
Test hook 40
Test hook connecting cable 40
Interface demo CD 1
USB interface cable 1
RS-232 interface cable 1
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2.2. Start operation
The instrument is used with the following conditions.
Power Supply: Voltage: 100 ~ 240 V
Frequency: 60 (1±5%) Hz
Power: <30 VA
Environmental Conditions: Temperature: 0 ~ 40°C
Humidity: 80%
No powerful electromagnetic interference
Plug into the power receptacle with voltage from 100 to 240V and earthing wire,
then press the power switch on the panel to make the generator connected to
power source. Now the initialization of the generator begins. The name of
instrument and manufacturer are displayed first, and then install the default
parameters. Finally the timing waveform interface is displayed.
Warning!
For manipulator’s safety, triple socket with safe earthing wire must be used.
3. Principle summarize
When sample the external signal source, the external signal is sent into the
positive input port of the high-speed comparator via the input circuit. The
threshold circuit generates a threshold voltage according with the setting values,
and sends the voltage to the negative input port of the high-speed comparator. A
TTL level digital signal is generated by the comparison of the two signals and
then the digital signal is stored synchronously in the data flip-latch by sampling
clock. When sample the internal code, the code generator will produce 30
channels of internal digital signals which are stored synchronously in the data
flip-latch by sampling clock. The sampling data in the data flip-latch are stored in
high-speed memory according to appointed address.
Selecting the internal clock in timing sampling can set the cycle of sampling clock.
State sampling with external clock can select the phase of sampling clock.
During the period of sampling storage, a “sequence add 1 counter” supplies
storage address for the high-speed memory in memory control circuit, each
sampling clock makes the memory change to a new writing address. At the same
time the flip-latch sends a new sampling data, so a new data is stored in the
memory. The start-up and end of the address counter is determined by the
memory control circuit according to the parameters of triggering process. After
sampling storage, Micro controller unit reads a series of data and send them to
the LCD which will display the timing waveform and data list.
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The work principle is shown as the following diagram.
-3-
Read/write
data
Sampling
circuit
Sampling
rate
read/write
data
Keyboard
Input
Storage
address
generator
High-speed
comparator
Threshold
voltage
High-speed
memory
MCU
T
rigger
process
External
signal
Clock circuit
Internal code
generator

4. Display and keyboard
4.1. The panel of the instrument
Front panel
1. Power switch
2. Display screen
3. Display control keys
4. Data input keys
5. Cursor key
6. Sample key
7. Function keys
8. Signal input
9. Signal input
10. Adjusting knob
AC 100-240V
45-65Hz 1A
REPLACE FUSE
AS SPECIFIED
DISCONNECT POWER CORD
BEFORE REPLACING FUSE
RS-232USB
3. 2. 1.
Rear panel
1. Power source outlet
2. RS232 interface
3. USB Device interface
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1. 2. 3. 4.
5.
6.
7.
8. 9.
10.

4.2. Keyboard description
There are 34 keys on the front panel, functions are following:
4.2.1. Function optional key (8 keys)
【Channel】:select and set the sequence order, name, color and switch of
each channel in cycle.
【Threshold】: select and set the threshold voltage.
【System】:select and set the system parameters.
【Trigger】:select and set the parameters and the switch in the trigger
process.
【Time/State】: select the mode of timing sample or state sample in cycle
【Source】:select internal code generator or external signal source in cycle.
【Save】:save the current setting parameters.
【Recall】: recall the last saved setting parameters
4.2.2. Sample control (2 keys)
【Run/Stop】: circular run/stop recycling sample
【Single】: single sample
4.2.3. Number input (11 keys)
【0】【1】【2】
【3】【4】【5】
【6】【7】【8】
【9】: number input key
【x】: special characters x, only used for data search input
4.2.4. Input control (4 keys)
【↑】【↓】: select the setting parameters up to down in cycle
【←】: backspace, to delete the input data when the input hasn’t
finished
【Shift】: used for input the English letters above the button
4.2.5. Display control (5 keys)
【Display】: display timing waveforms or data lists in cycle.
【↑↓】:use the knob to roll timing waveforms and data lists up and
down
【←→】: use the knob to roll timing waveforms and left and right
【Zoom】: use the knob to zoom timing waveforms
【Find】: find and display the data points suited the search conditions
4.2.6. Control knob (2 keys)
【Cursor 1】: use the knob to move the cursor1 left and right
【Cursor 2】: use the knob to move the cursor2 left and right
4.2.7. Working state (2 keys)
【Reset】: initialize the instrument and resume the default parameters
settings
【Language】: Only English interface
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4.3. Display description
On the top of the display screen, there are some words shown the function and
the operation of the button you pressed (except the numeric keys).
There are 3 types of display interface under the denotation words, details are
following:
4.3.1. Waveforms display interface
The waveforms display frame is on the top of the display interface which displays
eight channels of timing waveforms, the serial number and the name of the
waveform, four different colors vertical cursor lines. There is one scale on the top
of the waveform frame, and another one is on the bottom of the waveform frame.
They are the zoom scales, the time value of every scale varies with the zoom
coefficient. Below the waveform frame is the parameters display frame, the six
parameters on the left is the state parameters, varies automatically with different
operations, showing the current state of the equipment. The six parameters on
the right is the parameters settings of the system, can be set with number keys.
4.3.2. Data display interface
The data display frame is on the top of the display interface which displays 19
rows of data, each row is one sampled data point in the memory, corresponding
to 32 sample channels. The three columns of data from left to right is the address
of data, the data value in Dec, the data value in Hex, the data value in Bin. The
parameters display frame is below the data lists frame, the three parameters on
the left is the state parameters, changes automatically with different operations,
showing the current state of the instrument. The two parameters on the right is
the parameters settings of the system, can be set with numeric keys.
4.3.3. Trigger settings interface
The trigger settings interface displays the whole trigger process. Adopting the
graphical mode makes users can easy to understand the whole trigger process.
The panes in the display interface is the nodes of the trigger process, the connect
lines among the panes show the direction of the trigger process, six parameters
can be set on the right, the left side have six switch can be set, the specifications
of the setting shows in the chapters behind.
5. Instructions for use
5.1. Starting initialization
Press the power button to connect the electricity supply. Firstly the model number
and the manufacturer of the instrument will be showed on the screen. Please
operate the initialization program and load the default parameter settings. Then
the timing waveforms of internal code will be displayed. All kinds of operational
practice can be carried out without connecting with the external input signals.
Most of the researching objects of the logic analyzer are single or non-cyclical
signals included in high speed data stream. So the analyzer can’t display the
signals in time on the screen as the oscilloscope does, but can sample the
signals according to certain time (sample clock). It can catch and save the
interesting signals by setting up the suitable trigger process. The saved data can
be recalled showing on the screen and researched repeatedly.
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5.2. Operation general principles
5.2.1. Keyboard description
When any key is pressed, there is a corresponding hint on the screen which
explains the function and the operation of the key. If there is a circular symbol,
consisting of two arrows laid end to end, on the left of the hint, then it is a cycle
key. It runs different functions by pressing it repeatedly. If there is no circular
symbol, the key has only one function.
5.2.2. Parameters input
If there are reverse numbers or characters on the screen, means the parameter is
a selected one which can be set by pressing the keys. If the user needs to select
other data, 【↑】and【↓】can be used. The user also can turn the knob left and
right to select other data cyclical. If input the wrong characters or numbers, user
can delete them one by one by pressing 【←】. As soon as the reverse
characters areas are filled with numbers, the parameter settings take effects.
Meanwhile the【←】doesn‘t work anymore, unless restarting input process.
5.2.3. Letters input
The 26 letters, from A to Z, are marked on 26 keys. During the process of
parameter input, press【shift】key and release the key, then input the letter you
need. If there is no letter on the key, user can input space. The【shift】key is a
one-kick. So if the user needs to input the next letter, please repeat the
operations above.
5.3 Channels setting
5.3.1. Channel order setting
The double digits number 00-31, on the most left of the waveforms display frame,
is the channel serial number. Press【Channel】key to select the channel serial
number setting. Then set the channel sequence by numeric keys. The settings
only change the position of channel waveforms on screen so that some channels
of waveforms can be closely displayed and easily compared. However the real
positions of sampling channels are not changed, the sampled data too. If the real
positions of sampling channels need to be changed, user has to change the
connection of the test nips for sampling on the circuit board.
5.3.2. Channels label setting
The four characters on the right of the channel serial numbers are the label of the
channel. Press 【Channel 】key to select the channel label setting. Set the
channel label by numeric keys or letter keys. Every channel label can be set by
user.
5.3.3. Channels color setting
Press【Channel】key to select channel color setting. Set the color by numeric
keys. Every channel can be set according to user’s favorite color.
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5.3.4. Channels switch setting
Press【Channel】key to select channel switch setting. Set the channel “on” by
using the numeric key【1】. Set the channel “off” by using the key【0】. The
settings will take effect in the process of next sampling display.
The settings of the channels are complicated but there is no need to change them
frequently. Press【Save】to save the self-defined channel settings so that you
can use it when you need without reset the settings.
5.4. Thresholds setting
Press 【Threshold】key to select threshold voltage setting. The 【↑】and【↓】
pushbuttons are used to circularly select one of the six threshold voltages. Only
knob can be used to set the value of threshold voltages in a continuous manner.
The voltage will increase by turning the knob to right and decrease by turning the
knob to left. When the voltage value passes the zero, the polarity sign will
automatically change. The internal code-generator doesn’t pass the voltage
comparator, so the settings on threshold voltage aren’t valid when sampling the
internal code.
The analyzer has 32 external signals input channels and 2 external clock
channels. The best performance is when the peak-to-peak value of input voltage
is between 500mVpp and 20Vpp. The maximum input voltage handle is ±40V.
After accessing the analyzer, the input signal first passes through the voltage
comparison circuit and is compared with the threshold voltage set by the user. If
the input signals are higher than the threshold voltage, the analyzer shows the
number “1”, otherwise it shows the number “0”. Then the signals are sampled and
saved and displayed on the screen.
Waveforms displayed by this means only reflect the timing logic when the input
signals are higher or lower than the threshold voltage. It doesn’t reflect the real
amplitude of the input signals, and may be far different from the real waveforms
of the input signals. This kind of waveforms displayed by logic analyzer is usually
called a “pseudo waveform”.
In practical operation, the sampled signals appear by groups. For example,
grouped by the data bus or the address bus .The characteristics of amplitude of a
group of signals are the same, so use the same compare threshold voltage. In
practical operation, there are many kinds of signals with different amplitude to be
tested such as TTL, CMOS and ECL. In every experimental circuit, the amplitude
characteristics of signals may be various. To satisfy these conditions, the
instrument is deployed with six individual adjustable threshold voltages. Four of
them are used in four channel groups which contain 8 signal input channels in
each one. And the other 2 threshold voltages are used in 2 external clock input
channels.
In practice, the instruments measure signals mostly in groups, for instance in the
total line and address line. The amplitude characteristic of one group is identical
and should use the same comparison threshold voltage. However the instrument
has 32 signal input channels and again, it is not necessary to setup 32
independently adjustable threshold voltages. But in practice, there are signals
measured with different amplitude for instance TTL, CMOS, and ECL.
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In many experiment circuits, the amplitude required may vary. For this application,
6 independently adjustable threshold voltages are configured in instrument, 4 of
which are used for 4 channel groups, each group has 8 signal input channels.
The other two are used for 2 external clock input channels separately.
In practice, the electrical sources of +5V or +3.3V are usually used in digital
system. So all default settings of the threshold voltage are +1.6V. Generally
speaking, the setting range of the threshold voltages for TTL is between +5V and
+3.3V. And the setting range of threshold voltages for CMOS is between +5V and
+4.3V. If the tested signals contain large ringing effect or other noises, there are
wrong data in the sampled results. When it happens, repeat sampling function to
adjust the threshold voltage and observe the sampling waveforms, until clear and
correct sampling waveforms are obtained.
5.5. Display setting
The PeakTech
®
1235 logic analyzer can display a vast amount of data. There are
two display modes of the sampling data: timing waveform display and data listing
display.
5.5.1. Timing waveform display
Press【Display】to view timing waveforms for up to 8 channels displays. Each
channel can be displayed with different color to easily indentify and separate
them visually. The order of 32 channels waveforms is that the highest channel is
on the top and the lowest channel is at the bottom. This is to enable the highest-
order digit of the byte to be on the top and the lowest-order digit on the bottom.
5.5.2. Waveform rolling Up/Down
The waveform rolling can be used to observe all the waveforms in 32 channels.
Press 【↑↓】and turn the knob to browse the waveforms. If there is a need to
compare the waveforms, the method of channel order setting (5.3.1) can be used
to display the desired waveforms.
5.5.3. Waveform rolling Left/Right:
The PeakTech
®
1235 allows for 260,000 memory addresses for each channel,
however only 280 data points can be viewed due to the horizontal width of the
screen. In order to display the needed blocks from the mass of stored data, the
screen display window aim at any position in memory. This requires setting a
changeable “window address” for display window, as long as changes the window
address, the screen of analyzer will show the storing data block taking this
address as initial point.
Parameter in the first row on the right bottom of the wave frame is the window-
addr. The waveform displays the data on the most left, that is the data
corresponding to the window address in sampling memory. Press【System 】to
select window-addr and can set the window address in Dec numbers with the
range of 0~260000. After setting, the waveform of sampling storing data block, to
which this window address corresponds, will display immediately. If one needs to
continuously observe a waveform nearby the window, press【←→】and turn the
knob, the window-address will change continuously, as if the waveform is rolling
from left to right in the display window.
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Parameter in second row on the right bottom of the wave frame is scroll-step,
turn knob one step; the window-address will increase a scroll-step value. The
higher the value of scroll-step is, the faster the speed of waveform rolling is, but
this may miss needed part; the lower the value of scroll-step is, the slower the
speed of rolling is, and the finer observe the waveforms. Press 【System 】to
select scroll-step, the value of the scroll-step can be set by number keys with
the range of 1~ 260 000, after the setting, press【←→】and turn the knob to roll
the waveform left and right, so that the speed of waveform rolling will change.
Setting the window-address with number keys directly enables display window to
locate in the data block needing to visit, and rolling waveforms with knob turning
can observe the change situations of a section of waveform continuously.
5.5.4. Waveform zoom
In digital systems, the changing rate of the logic level may be very different in
different data channels, in a timing waveform displaying graph; it may include 8
channels with big difference in changing rate of logic level. This brings a problem,
that is, a large number of pulse waveforms crowds together in channel with fast
changing rate of logic level and cannot be seen clearly, but in the channel with
slow changing rate, it is a line on screen. To solve this problem, can stretch the
waveforms in level direction and unfold the crowded pulse wave to visit waveform
characteristics with fast changing, also can compress the waveforms and gather
sparse pulse waveform together to visit waveform characteristics with slow
changing.
Press【Zoom】key and turn the knob to make the display waveforms stretch or
compress in horizontal direction. “Zoom= ns/div” in the sixth row on the left
bottom of the wave frame will change, this ratio coefficient stands for time amount
that each lattice of scale line represents, in the above and underside two rows of
waveform frame. The essence of waveform amplification is that a number in
sampling memory is displayed continuously with several points in waveform
display. So, the amplifying waveform can make dense waveform be seen more
clearly and let measurement become easy, it won’t generate any distortion to
waveform. But waveform amplification is unable to increase resolution; the
original invisible contents are still not seen after amplification. If want to observe
the detailed change, need to increase sampling velocity. The essence of
compression is taking one number to display from several data points in sampling
memory, therefore after compression, waveform’s observing scope is broadened,
but may lead to distortion and miss small changing part, more compression rate
results in more serious distortion. So compression should be made gradually, one
should not continue compressing when finds distortion. The amplifying or
compression state will be displayed in present waveform, with the turn of knob;
character indication displays on top of interface at any moment.
Because waveform zoom is taken sampling clock as the time unit, so the zoom
ratio change is spaced by step, if measure waveform’s interval with scale of
waveform frame, may have error, just a rough measurement. If need to measure
the interval of the waveform accurately, should use the method of cursor
measurement.
The zoom function of the waveform is applied in the situation that the changing
rate difference of the logic-level in every channel is very big in a group of
waveforms, if the changing rate of the logic level in a group of waveforms is
generally bigger or smaller, then should solve it by adjusting the sampling rate.
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5.5.5. Data lookup
The instrument has convenient search function, after the sampling, can find the
data conforming to the setting conditions in a large group of sampling data.
Parameters in the third row on the right bottom of the wave frame is the find-data
which is a 32bits data word in Hex format, press【System】to select find-data,
can set search data word, input the numbers of 0~9 or the letters of A~F, also
can input x(attention: the【x】on the right of the key 【0】，is not the letter “x” in
English), x means “ignore”, that is, no matching and contrast to this number in
data find. After setting the find data word, press 【Find】again, can find a data
according with the searching conditions, denoting with a yellow dashed generally
can be seen on the most left of the screen. At the same time, window address will
also change to show the position of this data in sampling memory. Press【Find】
repeatedly, until find the end point of sampling memory, thus can find all the data
words conforming to setting conditions from sampling data.
The find-data function runs after finishing sampling and is used to look up data
word set randomly in stored sampling data, this point is different from trigger
conditions data word that will be described behind, the latter is preset in advance
before sampling and used to capture data word conforming to trigger conditions.
5.5.6. Data listing display
Press【Display】key, 19 rows of data listings can be showed. In the data listing
interface, the most left line is the Dec address value of sampling data in memory,
and increase one continuously from the top to the bottom. The middle is the
address value of the sampling data in Hex, the right one is the Bin address value,
a parting line between each 8 bits Bin code so as to read conveniently. Use two
different colors to distinguish the two adjacent lines, making display clear,
beautiful and not easy to confuse. The storage depth of the instrument is 260,000
storing addresses, but the screen shows only 19 rows in the vertical height,
therefore, data lists also must roll up and down in the display window. The
parameter definitions and operation methods showed in data listing are the as
timing waveforms display mentioned before. The window addresses, rolling step,
find-data words are identical. The difference are that rolling up and down in the
data lists equals rolling left and right in the timing waveforms display, and the
found data is a row of orange data showed in upper part of data listing. The data
listing cannot roll left and right, also cannot zoom.
5.6. Cursor setting
There are two cursors in this instrument for measurement: cursor1 and cursor2.
5.6.1. Timing waveforms cursor
In the timing waveforms display interface, press 【cursor 1 】key, the green
cursor1 shows active state, turn the knob, enable the cursor1 to move left and
right.Press【cursor 2】key, the purple cursor is chosen, turn the knob, enable the
cursor2 to move left and right.The step of cursor movement can be set with
number keys 0~9. For example, press 【1】, then turn knob a lattice, the cursor
moves one point distance on the screen, press 【9】, then turn knob a lattice, the
cursor moves nine points distance on the screen. Generally speaking, first move
the cursor with the longer step to the aim point nearby, then move the cursor with
the shorter step to the aim point.
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5.6.2. Cursor measurement
It is available to measure the sampling data value of any points in the display
waveforms and the time interval between any two points in the waveforms with it.
The second row on the left bottom of the waveform frame is the parameter value
of cursor1, the third row is the parameter value of cursor2, the six numbers on the
left of the parameter are the decimalization data address cursor indicates, and
the 8 numbers on the right of the parameter are the Hex data value of position
cursor indicates, which is the sampling data of 32 input channels, each number
represents 4 channels, according to the general custom, the data from left to right
represents the 32 input channels of waveforms from the top to the bottom in turn.
So the screen only shows the waveforms of 8 channels, one can know the logic
levels of the 32 channels as long as reads the data value of the cursor out
without moving waveforms up and down to visit. When turn knob to make
measurement cursor move, cursor parameter’s address value and data value will
change dynamically with it, when the two cursors move into the same point, their
parameter values are identical.
The difference value between cursor1 and cursor2 displays in the 4
th
row on the
left bottom of the waveform frame, denoted by sampling clock cycle, that is
address value. The data in the 5
th
row on the left bottom is the difference value
between cursor1 and cursor2, denoted by absolute time (ns). When the cursor1 is
on the right of the cursor2, the two parameters are positive values; they are
negative values on the left of cursor2. When the two cursors coincide with each
other, their parameters are 0.
If want to measure the time difference between two points in present waveform
interface, can move cursor1 and cursor2 to the two aim points respectively; it’s
easy to read the time difference or the address difference between the two points.
But if the address difference between the two points to be measured exceeds 280,
the two points can’t be displayed in the same interface at the same time, and
cannot measure using the above method. To solve this problem, it sets the
cursor1 and the cursor 2 into different characteristic. Cursor 1 is a drift cursor,
appearing in the displaying window always, can be seen as an aim line, and able
to move anywhere in window with knob. But cursor1 appears to suspend on
waveform, and doesn't move with the waveforms together, its address value and
data value will change with the waveform movement, denoting waveform’s
address value and data value cursor placed at any moment.
Cursor 2 is an adhering cursor, although it can be moved into anywhere in
window with knob, it will adhere to waveform once stops moving, when waveform
moves, cursor 2 moves as it. When moving the cursor 2 out, can imagine it still
adheres to and moves with waveform, its address value and data value won’t
change not caring how long waveform moves. When we want to measure time or
address difference between any two points in sampling waveforms, firstly move
cursor 2 to the first aim point, then move waveform left or right until the second
aim point displays no matter whether cursor2 moves display out and how long
waveform moves, turn knob to move cursor1 to the second aim point, then able to
read time or address value out between two aim points. After finishing once
measurement, press【cursor 2】key to recall it into display window and begin the
next measurement.
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5.6.3. Data listing cursor
In data listing interface, cursor1, cursor2 and cursor measurement, are all the
same as the cursors in timing waveform interface. The difference is that cursors
in timing waveform display interface are vertical cursor lines, but in data listing
display interface cursors are level white display row. There is only address
display of two cursor rows about parameter display under data listing (data values
in the listing already).
5.7. Sampling setting
The logic analyzer uses the sampling mode for data obtaining, which is sampling
to input “digital”, notice that it is not to collect sample to input signal directly, but
to digital generated through comparison and distinguishing for input signal and
threshold, and stores sampling data in memory. So, the basic requirement for
logic analyzer use is setting sampling parameters correctly.
5.7.1. Sampling source
The purpose of using logic analyzer is to analyze the logic state of signal to be
measured, so the aim signal to be sampled is external signal source surely. But
take the following three points for consideration, set an educational pulse
generator in instrument inner. First, many users may be not familiar with the logic
analyzer, some may use it the first time, so first make operation practice to
deepen apprehension for the correlation between various parameters’ setting,
and familiarize operational control for display interface, and not need to connect
mass of input test nips, very conveniently no doubt. Moreover, external signals to
be measured are usually unknown and complicated, may be mixed with random
interference signal too, so it is necessary to set threshold voltage suitably and
take sample to external signal directly, getting expectant result may be more
difficult. Because the Inner Code Generator’s logic relation is simple, waveform is
pure and standard; one can quickly master logic analyzer’s use with it. Second, in
practical application, if the test result is different from expectant one, sometimes
it is hard to make clear that the problem comes from the tested circuit or logic
analyzer, here as long as use inner code generator to take samples and contrast,
it is easy to find reasons. Third, when instrument fails to work and need repairing
and debugging, the code generator is very convenient of course.
The inner code generator is composed of two types of signals, 00 ~ 15 channels
are count waveforms, count value are 0~65535, and each clock cycle adds 1.
16~29 channels are shift pulse waveforms and high level pulse moves one bit to
the right in turn from low to high channel. 30~31 channels are used to measure
external clock1 and 2 (6.7.2). The code generator in the equipment, if only power
is open, runs in its independent clock continuously till power closes. The inner
code generator directly generates standard digital signals for sampling, not
passing threshold voltage comparator. If choose inner code generator, then
external digital signal cuts automatically, vice versa, they don’t affect each other.
Pressing 【source 】key can switch into inner code generator or external signal
source in cycle, instrument default setting is inner code generator. The internal
code-generator has its own adjustable clock, can emulate measured signals with
different velocities, press 【system】to select parameter pattern-clk and input
the clock cycle value with decimalization numbers 0~9, its unit is ns, resolution is
10ns,the last number on the right has no use. The minimum cycle value is 20 ns;
the maximum value is 999999990ns, approximate to 1s. After code generator’s
clock changes, waveform display’s change is visible. The default setting of the
clock cycle is 20 ns.
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If take samples to external signal source, first connect one end of fifty-line cables
to instrument input port, connect the other end to input-transferring case which
has 16 signal input ends and one external clock input end, use single-core joint
line to connect these input terminals and the test nips, then connect with
sampling points on the circuit board with test nips. Each input terminal of
transferring case has a grounding terminal correspondingly, although not all
terminals are necessarily connected to circuit board’s signal earth, but the more
connect ground lines, the less noise of input signal makes, and the better for
measurement. If connect only one ground line, sampling signal may get glitch
interference, and bring difficulties for data analysis.
5.7.2. Sampling mode
There are two sampling modes for logic analyzer: One is timing sample which
collects samples to the external signals using the internal equal time interval
clock, the sampled data is equal time interval data, in other words it takes "time"
as the independent variable. The timing waveforms after sampling can basically
reflect the changes of the tested signal as time, this approach is known as the
timing analysis, but the sampling clock and the tested system are independent
each other and not synchronous, so it is also called "asynchronous sampling."
The other mode is state sample which collects samples using the clock of the
tested system, the clock is equal time interval, and also can be random time
interval. The sampling clock pulse can be seen as the discrete event, that is, take
the "event" sequences as independent variable, the data listing after sampling
reflects the logic state relation between the system clock and the other signals in
the system, this mode is known as state analysis. Here, the sampling clock is
synchronous with the tested system; it is also called "synchronous sampling." If
take sample using inner clock to inner code generator, this also belongs to
"synchronous sampling."
If use state sampling as sampling clock signal in measured system, must connect
to special input channel clk1 or clk2, otherwise the sampling couldn’t start. If the
noise in the external clock signals is too large, should adjust the threshold
voltage settings of the external clock (5.4) so as to obtain a pure clock signal, if
the sampling clock signal is poor, the sampled data can not be used. However,
the external clock signals are not stored, also no special accesses to display
waveforms, so it is impossible to know the quality of the clock signals after
passing threshold voltage comparator. A substitute method mentioned once in
(5.7.1): press 【source 】to select aim source and use inner clock as timing
sampling, then connect external clock signal to the special clock channels clk1
and clk2, here external clock can take samples to external clock signals, clk1
and clk2’s timing waveforms display in 30~31 channels after sampling. When
adjust the threshold voltage settings of the external clock, one can use the two
channels to monitor the adjustment effect.
Sampling mode can be set with 【Time/State 】key, inner clock for timing
sampling, and external clock for state sampling. The external clock contains
external clk1 and external clk2. The default setting is the timing sample, using
internal clock.
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5.7.3. Clock limitations
To visit the particular changes of the tested signals, we hope to use higher
sampling velocity, but this would greatly increase the data amount in the memory.
Besides, sometimes the tested signal is single or occasional and is included in
the long data stream. To effectively capture them, we must lengthen the time of
the sampling as we can; thus the data stored in the memory will be greater. But
the space of the high-speed memory is limited, to solve this problem; the
instrument sets two external clocks’ logic "and" and logic "or" which is limiting an
external clock using anther one. For example, select the logic "and" of two
external clocks as the sampling clock, use high level of the external clk1 as the
limit condition, only when external clk1 is a high level, the sampling clk2 can be
opened, the sampling can run, in other times the clk2 is shut down and cannot
sample. If set limit conditions suitable, it can ensure that not only effectively
capture the signals one interested in, but also save the space of the memory.
Using【Time/State】key can select limitation mode in cycle: the logic “and” and
logic “or” of external clock clk1 and clk2.
5.7.4. Sampling cycle
The logic analyzer captures data on the hop edge of the sampling clock; the data
between two hop edges is ignored. If choose longer sampling cycle, the fast-
changing sections of input signals will be missed, then the displayed waveforms
will have serious distortion compared with the true waveforms of input signals
both in amplitude and time, even invisible. One should use shorter sampling cycle
in order to observe the particular changes of the tested signals, that is, to
increase the sampling rate.
Generally speaking, the sampling cycle should be less 3-5 times than the
narrowest pulse width of the tested signals. In other words, even the narrowest
pulse of the tested signals should include three sampling points at least, which
can truly reflect input signals’ change as time.
The instrument uses internal clock in the time sampling, and clock cycle can be
set. Press 【system】to select parameter pattern-clk and input the clock cycle
value with decimalization numbers 0~9, its unit is ns, resolution is 10ns, the last
number on the right has no use. The minimum cycle value is 10 ns; the maximum
value is 999999990ns, approximate to 1s. When code generator’s clock is
changed, waveform display’s change is visible. The default setting of the clock
cycle is 10 ns, that is to say, the highest sampling velocity is 100MHz.
The instrument uses the external clock cycle in state sampling; the sampling
cycle can’t be changed optionally, one needs to select the suitable signals as the
sampling clock according to the state of the tested signals.
5.7.5. Sampling phase
The logic analyzer uses sampling clock’s rising edge for data obtaining, but in
state sampling using external clock, due to “synchronous sampling”, sometimes
should choose clock’s function edge reasonably according to logic relation
between signal and system clock of tested system. For instance, various logic
levels change in system clock’s rising edge, if samples using rising edge, various
logic level is in changing then and the time is not consistent strictly, so sampling
data may be wrong. If choose falling edge, all logic levels are just in stable state,
sampling date won’t be wrong.
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Therefore, instrument sets sampling phase choices: rising edge sampling and
falling edge sampling. In timing sampling to external signal with internal clock,
sampling phase setting is out of meaning because of “asynchronous sampling”.
Press 【system 】to select sample-phase and set sampling phase in numbers,
press【0】to select clock falling edge, press【1】to select rising edge.
The default setting is the falling edge sampling.
5.7.6. Sampling control
There are two keys used for controlling in the sampling process：press 【single】
key, sample process runs once only, after sampling, display the result in timing
waveform or data listing, then can make various operations and analyses to it,
this is universal using method of logic analyzer. Press【Run/Stop】, the sampling
process runs automatically and repeatedly with result displaying each time, until
press 【Run/Stop 】, sampling process stops, which is generally used to visit
dynamic change of tested signal or dynamic response of the adjusting parameter
setting, when grasp the characteristics of tested signal, or adjust parameter
setting suitably, press【single】key to sample and analyze the results in detail.
5.8. Trigger setting
In modern digital system, the code stream rate is very high in us or ns level
generally, which requires corresponding sampling velocity for logic analyzer.
However, the space of memory in the instrument is limited, so in practical, the
effective sampling time is very short, it can say sampling process completes
instantaneously. If start up sampling process manually, this needs to press
【Single】in an extreme accurate time, but it is too hard to do, moreover, the
data needed sampling and storing is often contained in the long data stream, we
don’t know when we should start up to capture the data, so it is even more
impossible to start up the sampling process manually. Due to limited memory
space, large amount of data will enter memory soon after starting up, if sampling
process can not stop immediately, following data will overwrite preceding ones,
when press key manually, the data stored in the memory finally may not useful for
us. So, manual control is also infeasible. The logic analyzer must run the
sampling process automatically according to operator and stop after capturing
useful signals automatically; this is the fundamental difference between logic
analyzer and the data collector.
Using logic analyzer firstly, one may feel very difficult to start in trigger process
setting and uneasy to understand the functions of setting parameters, press
【trigger】, display a graphical trigger setting interface, which can make operator
know the whole process of sampling visually and directly, and master setting
method of trigger process.
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5.8.1. Signal input
Signals input process is on the left of trigger setting interface: the external tested
signal from “probe” passes through test nips, “commuting case”, transmitting
cable, connector, to “comparator”, then compare with the “threshold voltage” to
generate digital signals. Internal code generator pattern generates emulational
digital signal, choose one of this two signals through switch “source select”, press
【source】to select the switch state in cycle. The selected input signal passes
through the channel switch “switches” to sampling circuit. The setting of the
channel switch has been described in (5.3.4).
5.8.2. Start conditions
The sampling trigger process is on the right of the trigger setting interface, press
【Single 】key, the sampling process does not really start, but firstly to check
start conditions, once the data in the input signals can match with it, the sampling
process starts immediately.
The start “bit-select” can be set with numbers in Hex, representing 32 input
channels, if set bit-select to 0, shows this channel can be ignored, without match
checking, and has no influence on start whatever signal level of this channel is 0
or 1. If set bit-select to 1, shows the channel is effective, and must be made
matching checking. The default setting of start bit-select is 0000FFFF, means that
only detect 00~15 channels, ignore 16~32 channels.
The start “compare word” can be set with numbers in Hex, the default setting of
start compare word is 00001234 and means once “1234” appears in 00~15
channels in the input data streams, in other words when the logic level of 00~15
channels is “0001001000110100”, the sampling process starts.
5.8.3. Start select
The “start select” can be set with numbers, the key【0】cut the switch, the key
【1】connects the switch. If the start select switch is connected, “the start
conditions” will be short-circuit, having no use. In other words, after pressing
【Single 】, the sampling process starts directly without detecting the start
conditions, equal to random sample manually.
The default setting of the “start select switch” is “connect” in order to make
random sampling drilling justly without specific sampling purpose, not need to set
the start conditions. If the setting of the start select switch is “cut”, then only
understand the tested signal clearly and have specific sampling purpose, can set
the suited start conditions. Otherwise, if set start conditions unsuitably, then
cannot satisfy start conditions forever, the sample can’t start.
5.8.4. Trigger conditions
When sampling starts up, the instrument writes the sampling data into the high-
speed memory continuously according to the sampling clock time. Once the
memory is filled, it will be back to the top and overwrite the former data. Then
when will the sampling process stop? The sampling purpose is making limited
storage data blocks contain the signals we concern, so it needs to set the
appropriate trigger conditions to capture the signals, after the signals are
captured, the instrument takes a short time of “store delay”, the sampling process
stops automatically. The suitable setting of trigger conditions can decrease
storage of useless data, improve the effective utilization of the memory, and bring
convenience for the data analysis.
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The start “bit-select” can be set with numbers in Hex, representing 32 input
channels, if set bit-select to 0, shows this channel can be ignored, without match
checking, and has no influence on start whatever signal level of this channel is 0
or 1. If set bit-select to 1, shows the channel is effective, and must be made
matching checking. The default setting of start bit-select is 0000FFFF, means that
only check 00~07 channels, ignore 08~31 channels.
The start “compare word” can be set with numbers in Hex, the default setting of
start compare word is 00000069 and means once Hex number 69 appears in
00~07 channels in the input data streams, in other words when the logic level of
00~07 channels is “01101001”，the trigger conditions is satisfied.
Different from start conditions, the trigger conditions sets three trigger limit
switches, <, =, >, which are useful for testing the data fluctuant limit to the tested
signals. The trigger limit switch can be set with number keys, press 【1】to
connect the switch, but only one is connected in the three trigger limit switch,
once one switch is connected, the other two switches are disconnected. The
default setting of the trigger limit switch is "=" connecting.
5.8.5. Event count
When the sampling process starts, the instrument starts to sample the input
signals, and stores the sampling data in the memory, at the same time, compares
the sampling data with the trigger conditions and the trigger limit switch, if the
sampling data satisfy the trigger conditions and the trigger limit switch, means
that it captures a trigger event. In some applications, the trigger event we care
may appear many times, and the thing we interested in is the situations after the
trigger event appears many times. If we can capture the trigger event for many
times in one sampling process, that may be more convenient for analysis. So the
instrument sets a trigger event counter, after the sampling process starts, the
count value firstly resets, then the count value adds one when meets the trigger
event once, till the count value reaches the setting value of the trigger event , the
trigger process finishes.
The trigger events count can be set with numbers in Dec, the setting range is
1~999, the default setting of the trigger event count value is 001.
5.8.6. Trigger select
The trigger select switch can be set with numbers, the key【0】cuts the switch，
the key 【1】connects the switch.If the trigger select switch is connected, the
trigger conditions, the trigger limit switch and the event counter are all short-
circuit, having no use.In other words, after sampling process starts, the
instrument does not detect the trigger conditions, also does not count the event ,
the trigger process finishes unconditionally.
The default setting of the “start select switch” is “connect” in order to make
random sampling drilling justly, and has no specific sampling purpose on
capturing what kind of signal, not need to set the trigger conditions and event
count too. If the setting of the start select switch is “cut”, then only understand
the tested signal clearly and have specific sampling purpose, can set the suitable
trigger conditions, trigger limit switch and event count. Otherwise, if sets these
parameters unsuitably, the trigger process may not finish.
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5.8.7. Store delay
The sampling process can stop in usual after the trigger process finishes. But in
some applications, we hope to delay a period of storage time of the sampling data
in order to analyze some signals characteristics after trigger events. So a delay
counter is set in this instrument, after the trigger process finishes, the sampling
process still runs, meanwhile clears the delay counter and counts for sampling
clock, the count value adds one each clock cycle, the sample process stops when
the count value reaches the setting value of the delay counter.
The “store delay” can be set with numbers in Decimalization, the setting range is
1~260000, the unit is the number of sample cycles; the default setting of storage
delay is 600 sample cycles.
Because both the default setting of the start select switch and the trigger select
switch are “connected”, we don’t need to set the trigger process, just press
【Single 】key, the instrument doesn’t check, but directly starts sampling and
makes storage delay, in other words, the sampling process stops automatically
after sampling 600 clock cycles randomly.
5.8.8. Manually stop sample
As already mentioned above, if set the start select switch as disconnected, but
set the start conditions unsuitably, the sampling process can’t start. If set trigger
select switch as disconnected, but set trigger conditions unsuitably, the trigger
process can’t stop. Under such two conditions, the instrument is on the detecting
state all the times, until the suitable signals appear and displays “sample is
processing, press any key to stop”. To release from this state, just press any key
to stop the sampling process manually. Then one must study the tested signals
carefully, reset the trigger process to make sure the sampling process can run
normally.
5.8.9. Trigger cursor
Sometimes there may be one or several vertical red lines in the timing waveforms
interface, they are trigger cursors. The positions of the cursors are the sampling
data points that satisfy the setting of the trigger conditions in (5.8.4).
The parameter value of the trigger cursor is on the left bottom of the waveforms
frame in first row, the six numbers on the left of the parameter are the addresses
of the data in Dec that cursor indicates, the eight numbers on the right of the
parameter are the values of the data in Hex that cursor indicates, i.e. the
sampling data of the 32 input channels, every number represents four channels,
according to the general custom, the data from left to right represents the 32
channels of waveforms from the top to the bottom in turn. Press 【single 】
repeatedly for sampling and indication. Because it is random sampling, the
position of the trigger cursor line changes every time, the address value in the
parameters of the trigger cursor changes every time, the left six numbers of the
data value change every time, but the right two bits of the parameter value is
always 69. Because the default setting of the trigger condition is that 69 in Hex
appears in 00~07 channels, other channels are ignored. That means the position
that the trigger cursor line displays in the timing waveforms interface, is the data
points which is fully in line with the trigger conditions.
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