Philips LPC213 Series User manual

UM10120
Volume 1: LPC213x User Manual
Rev. 01 — 24 June 2005 User manual
Document information
Info Content
Keywords LPC2131, LPC2132, LPC2134, LPC2136, LPC2138, LPC2000, LPC213x,
ARM, ARM7, embedded, 32-bit, microcontroller
Abstract An initial LPC213x User Manual revision

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual Rev. 01 — 24 June 2005 2
Philips Semiconductors UM10120
Volume 1 LPC2131/2/4/6/8 UM
Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, please send an email to: [e-mail]
Revision history
Rev Date Description
01 20050624 Initial version

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User manual Rev. 01 — 24 June 2005 3
1.1 Introduction
The LPC2131/32/34/36/38 microcontrollers are based on a 16/32 bit ARM7TDMI-S™
CPU with real-time emulation and embedded trace support, that combines the
microcontroller with 32 kB, 64 kB, 128 kB, 256 kB and 512 kB of embedded high speed
Flash memory. A 128-bit wide memory interface and a unique accelerator architecture
enable 32-bit code execution at maximum clock rate. For critical code size applications,
the alternative 16-bit Thumb® Mode reduces code by more than 30 % with minimal
performance penalty.
Due to their tiny size and low power consumption, these microcontrollers are ideal for
applications where miniaturization is a key requirement, such as access control and
point-of-sale. With a wide range of serial communications interfaces and on-chip SRAM
options of 8/16/32 kB, they are very well suited for communication gateways and protocol
converters, soft modems, voice recognition and low end imaging, providing both large
buffer size and high processing power. Various 32-bit timers, single or dual 10-bit
8channel ADC(s), 10-bit DAC, PWM channels and 47 GPIO lines with up to nine edge or
level sensitive external interrupt pins make these microcontrollers particularly suitable for
industrial control and medical systems.
1.2 Features
•16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package
•8/16/32 kB of on-chip static RAM and 32/64/128/256/512 kB of on-chip Flash program
memory. 128 bit wide interface/accelerator enables high speed 60 MHz operation.
•In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader software.
Single Flash sector or full chip erase in 400 ms and 256 bytes programming in 1 ms.
•EmbeddedICE®and Embedded Trace interfaces offer real-time debugging with the
on-chip RealMonitor™ software and high speed tracing of instruction execution.
•One (LPC2131/2) or two (LPC2134/6/8) 8 channel 10-bit A/D converters provide(s) a
total of up to 16 analog inputs, with conversion times as low as 2.44 µs per channel.
•Single 10-bit D/A converter provides variable analog output. (LPC2132/4/6/8 only).
•Two 32-bit timers/external event counters (with four capture and four compare
channels each), PWM unit (six outputs) and watchdog.
•Low power Real-time clock with independent power and dedicated 32 kHz clock input.
•Multiple serial interfaces including two UARTs (16C550), two Fast I2C (400 kbit/s),
SPI™ and SSP with buffering and variable data length capabilities.
•Vectored interrupt controller with configurable priorities and vector addresses.
UM10120
Chapter 1: General information
Rev. 01 — 24 June 2005 User manual

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Philips Semiconductors UM10120
Volume 1 Chapter 1: Introductory information
•Up to 47 of 5 V tolerant general purpose I/O pins in tiny LQFP64 package.
•Up to nine edge or level sensitive external interrupt pins available.
•60 MHz maximum CPU clock available from programmable on-chip Phase-Locked
Loop (PLL) with settling time of 100 µs.
•On-chip integrated oscillator operates with external crystal in range of 1 MHz to
30 MHz or with external oscillator from 1 MHz to 50 MHz.
•Power saving modes include Idle and Power-down.
•Individual enable/disable of peripheral functions as well as peripheral clock scaling
down for additional power optimization.
•Processor wake-up from Power-down mode via external interrupt or Real-time Clock.
•Single power supply chip with Power-On Reset (POR) and Brown-Out Detection
(BOD) circuits:
–CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O
pads
1.3 Applications
•Industrial control
•Medical systems
•Access control
•Point-of-sale
•Communication gateway
•Embedded soft modem
•General purpose applications
1.4 Device information
Table 1: LPC2131/2132/2134/2136/2138 device information
Device Number of
pins On-chip SRAM On-chip FLASH Number of 10-bit ADC
channels
Number of
10-bit DAC
channels
Note
LPC2131 64 8 kB 32 kB 8 - -
LPC2132 64 16 kB 64 kB 8 1 -
LPC2134 64 16 kB 128 kB 16 1UART1 with full
modem interface
LPC2136 64 32 kB 256 kB 16 1UART1 with full
modem interface
LPC2138 64 32 kB 512 kB 16 1UART1 with full
modem interface

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User manual Rev. 01 — 24 June 2005 5
Philips Semiconductors UM10120
Volume 1 Chapter 1: Introductory information
1.5 Architectural overview
The LPC2131/2/4/6/8 consists of an ARM7TDMI-S CPU with emulation support, the
ARM7 Local Bus for interface to on-chip memory controllers, the AMBA Advanced
High-performance Bus (AHB) for interface to the interrupt controller, and the VLSI
Peripheral Bus (VPB, a compatible superset of ARM’s AMBA Advanced Peripheral Bus)
for connection to on-chip peripheral functions. The LPC2131/2/4/6/8 configures the
ARM7TDMI-S processor in little-endian byte order.
AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the
4gigabyte ARM memory space. Each AHB peripheral is allocated a 16 kB address space
within the AHB address space. LPC2131/2/4/6/8 peripheral functions (other than the
interrupt controller) are connected to the VPB bus. The AHB to VPB bridge interfaces the
VPB bus to the AHB bus. VPB peripherals are also allocated a 2 megabyte range of
addresses, beginning at the 3.5 gigabyte address point. Each VPB peripheral is allocated
a 16 kB address space within the VPB address space.
The connection of on-chip peripherals to device pins is controlled by a Pin Connect Block
(see chapter "Pin Connect Block" on page 73). This must be configured by software to fit
specific application requirements for the use of peripheral functions and pins.
1.6 ARM7TDMI-S processor
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
THUMB, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
•The standard 32-bit ARM instruction set.
•A 16-bit THUMB instruction set.
The THUMB set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because THUMB code
operates on the same 32-bit register set as ARM code.
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the
performance of an equivalent ARM processor connected to a 16-bit memory system.

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User manual Rev. 01 — 24 June 2005 6
Philips Semiconductors UM10120
Volume 1 Chapter 1: Introductory information
The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet that
can be found on official ARM website.
1.7 On-chip Flash memory system
The LPC2131/2/4/6/8 incorporates a 32, 64, 128, 256 and 512 kB Flash memory system
respectively. This memory may be used for both code and data storage. Programming of
the Flash memory may be accomplished in several ways: over the serial builtin JTAG
interface, using In System Programming (ISP) and UART0, or by means of In Application
Programming (IAP) capabilities. The application program, using the IAP functions, may
also erase and/or program the Flash while the application is running, allowing a great
degree of flexibility for data storage field firmware upgrades, etc. When the
LPC2131/2/4/6/8 on-chip bootloader is used, 32/64/128/256/500 kB of Flash memory is
available for user code.
The LPC2131/2/4/6/8 Flash memory provides minimum of 10,000 erase/write cycles and
10 years of data-retention.
1.8 On-chip Static RAM (SRAM)
On-chip Static RAM (SRAM) may be used for code and/or data storage. The on-chip
SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2131/2/4/6/8 provide
8/16/32 kB of static RAM respectively.
The LPC2131/2/4/6/8 SRAM is designed to be accessed as a byte-addressed memory.
Word and halfword accesses to the memory ignore the alignment of the address and
access the naturally-aligned value that is addressed (so a memory access ignores
address bits 0 and 1 for word accesses, and ignores bit 0 for halfword accesses).
Therefore valid reads and writes require data accessed as halfwords to originate from
addresses with address line 0 being 0 (addresses ending with 0, 2, 4, 6, 8, A, C, and E in
hexadecimal nottaion) and data accessed as words to originate from adresses with
address lines 0 and 1 being 0 (addresses ending with 0, 4, 8, and C in hexadecimal
notation). This rule applies to both off and on-chip memory usage.
The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls during
back-to-back writes. The write-back buffer always holds the last data sent by software to
the SRAM. This data is only written to the SRAM when another write is requested by
software (the data is only written to the SRAM when software does another write). If a chip
reset occurs, actual SRAM contents will not reflect the most recent write request (i.e. after
a "warm" chip reset, the SRAM does not reflect the last write operation). Any software that
checks SRAM contents after reset must take this into account. Two identical writes to a
location guarantee that the data will be present after a Reset. Alternatively, a dummy write
operation before entering idle or power-down mode will similarly guarantee that the last
data written will be present in SRAM after a subsequent Reset.

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User manual Rev. 01 — 24 June 2005 7
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Volume 1 Chapter 1: Introductory information
1.9 Block diagram
(1) LPC2134/2136/2138 only.
(2) LPC2132/2134/2136/2138 only.
(3) Pins shared with GPIO.
Fig 1. LPC2131/2/4/6/8 block diagram
002aab067
system
clock
SCL0,1
AOUT(2)
P0.31:0
P1.31:16
SDA0,1
TRST(3)
TMS(3)
TCK(3)
TDI(3)
TDO(3) XTAL2
XTAL1
SCK0,1
MOSI0,1
MISO0,1
EINT3:0
8 ×CAP0
8 ×MAT
AD0.7:0
AD1.7:0(1)
PWM6:1
SSEL0,1
TXD0,1
RXD0,1
RTXC2
RTXC1
VBAT
DSR1(1),CTS1(1),
RTS1(1), DTR1(1)
DCD1(1),RI1(1)
AMBA AHB
(Advanced High-performance Bus)
INTERNAL
FLASH
CONTROLLER
AHB BRIDGE
EMULATION TRACE
MODULE
TEST/DEBUG
INTERFACE
AHB
DECODER
AHB TO VPB
BRIDGE VPB DIVIDER
VECTORED
INTERRUPT
CONTROLLER
SYSTEM
FUNCTIONS
PLL
SPI AND SSP
SERIAL INTERFACES
I2C SERIAL
INTERFACES 0 AND 1
UART0/UART1
REAL TIME CLOCK
WATCHDOG
TIMER
SYSTEM
CONTROL
EXTERNAL
INTERRUPTS
GENERAL
PURPOSE I/O
PWM0
CAPTURE/
COMPARE
TIMER 0/TIMER 1
A/D CONVERTERS
0 AND 1(1)
D/A CONVERTER(2)
32/64/128/
256/512 kB
FLASH
ARM7TDMI-S
LPC2131/2132/2134/2136/2138
INTERNAL
SRAM
CONTROLLER
8/16/32 kB
SRAM
ARM7 local bus
VPB (VLSI
peripheral bus)
RST

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User manual Rev. 01 — 24 June 2005 8
2.1 Memory maps
The LPC2131/2/4/6/8 incorporates several distinct memory regions, shown in the
following figures. Figure 2 shows the overall map of the entire address space from the
user program viewpoint following reset. The interrupt vector area supports address
remapping, which is described later in this section.
UM10120
Chapter 2: LPC2131/2/4/6/8 Memory Addressing
Rev. 01 — 24 June 2005 User manual
Fig 2. System memory map
TOTAL OF 32 kB ON-CHIP NON-VOLATILE MEMORY
(LPC2131)
0xC000 0000
0x8000 0000
0x0000 0000
0.0 GB
1.0 GB
2.0 GB
3.75 GB
4.0 GB
3.0 GB
TOTAL OF 64 kB ON-CHIP NON-VOLATILE MEMORY
(LPC2132)
RESERVED ADDRESS SPACE
8 kB ON-CHIP STATIC RAM (LPC2131)
16 kB ON-CHIP STATIC RAM (LPC2132/2134)
32 kB ON-CHIP STATIC RAM (LPC2136/2138)
RESERVED ADDRESS SPACE
BOOT BLOCK
(REMAPPED FROM ON-CHIP FLASH MEMORY)
RESERVED ADDRESS SPACE
AHB PERIPHERALS
VPB PERIPHERALS
3.5 GB
0x4000 4000
0x4000 3FFF
0x4000 8000
0x4000 7FFF
0x4000 0000
0xE000 0000
0xF000 0000
0xFFFF FFFF
TOTAL OF 128 kB ON-CHIP NON-VOLATILE MEMORY
(LPC2134)
TOTAL OF 256 kB ON-CHIP NON-VOLATILE MEMORY
(LPC2136)
TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY
(LPC2138)
0x4000 2000
0x4000 1FFF
0x0000 8000
0x0000 7FFF
0x0001 0000
0x0000 FFFF
0x0002 0000
0x0001 FFFF
0x0004 0000
0x0003 FFFF
0x0008 0000
0x0007 FFFF

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User manual Rev. 01 — 24 June 2005 9
Philips Semiconductors UM10120
Volume 1 Chapter 2: Memory map
Figures 3through 5show different views of the peripheral address space. Both the AHB
and VPB peripheral areas are 2 megabyte spaces which are divided up into 128
peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying the
Fig 3. Peripheral memory map
AHB PERIPHERALS
RESERVED
RESERVED
VPB PERIPHERALS
0xFFFF FFFF
0xFFE0 0000
0xFFDF FFFF
0xF000 0000
0xEFFF FFFF
0xE020 0000
0xE01F FFFF
0xE000 0000
3.5 GB
3.5 GB + 2 MB
3.75 GB
4.0 GB - 2 MB
4.0 GB
Notes:
- AHB section is
128 x 16 kB blocks
(totaling 2 MB).
- VPB section is
128 x 16 kB blocks
(totaling 2 MB).

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User manual Rev. 01 — 24 June 2005 10
Philips Semiconductors UM10120
Volume 1 Chapter 2: Memory map
address decoding for each peripheral. All peripheral register addresses are word aligned
(to 32-bit boundaries) regardless of their size. This eliminates the need for byte lane
mapping hardware that would be required to allow byte (8-bit) or half-word (16-bit)
accesses to occur at smaller boundaries. An implication of this is that word and half-word
registers must be accessed all at once. For example, it is not possible to read or write the
upper byte of a word register separately.
Fig 4. AHB peripheral map
VECTORED INTERRUPT CONTROLLER
(AHB PERIPHERAL #0)
0xFFFF F000 (4G - 4K)
0xFFFF C000
0xFFFF 8000
(AHB PERIPHERAL #125)
(AHB PERIPHERAL #124)
(AHB PERIPHERAL #3)
(AHB PERIPHERAL #2)
(AHB PERIPHERAL #1)
(AHB PERIPHERAL #126)
0xFFFF 4000
0xFFFF 0000
0xFFE1 0000
0xFFE0 C000
0xFFE0 8000
0xFFE0 4000
0xFFE0 0000

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Philips Semiconductors UM10120
Volume 1 Chapter 2: Memory map
Fig 5. VPB peripheral map
SYSTEM CONTROL BLOCK
(VPB PERIPHERAL #127) 0xE01F FFFF
0xE007 0000
0xE006 C000
DAC
(VPB PERIPHERAL #27)
(VPB PERIPHERALS #28-126)
NOT USED
SSP
(VPB PERIPHERAL #26)
NOT USED
(VPB PERIPHERAL #25)
10 BIT AD1 (LPC2138)
(VPB PERIPHERAL #24)
I2C1
(VPB PERIPHERAL #23)
NOT USED
(VPB PERIPHERAL #14-22)
10 BIT ADO
(VPB PERIPHERAL #13)
NOT USED
(VPB PERIPHERAL #12)
PIN CONNECT BLOCK
(VPB PERIPHERAL #11)
GPIO
(VPB PERIPHERAL #10)
RTC
(VPB PERIPHERAL #9)
SPI0
(VPB PERIPHERAL #8)
I2C0
(VPB PERIPHERAL #7)
NOT USED
(VPB PERIPHERAL #6)
PWM
(VPB PERIPHERAL #5)
UART1
(VPB PERIPHERAL #4)
URT0
(VPB PERIPHERAL #3)
TIMER1
(VPB PERIPHERAL #2)
TIMER0
(VPB PERIPHERAL #1)
WATCHDOG TIMER
(VPB PERIPHERAL #0)
0xE01F C000
0xE006 8000
0xE006 4000
0xE006 0000
0xE005 C000
0xE003 8000
0xE003 4000
0xE003 0000
0xE002 C000
0xE002 8000
0xE002 4000
0xE002 0000
0xE001 C000
0xE001 8000
0xE001 4000
0xE001 0000
0xE000 C000
0xE000 8000
0xE000 4000
0xE000 0000

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Philips Semiconductors UM10120
Volume 1 Chapter 2: Memory map
2.2 LPC2131/2132/2134/2136/2138 memory re-mapping and boot block
2.2.1 Memory map concepts and operating modes
The basic concept on the LPC2131/2/4/6/8 is that each memory area has a "natural"
location in the memory map. This is the address range for which code residing in that area
is written. The bulk of each memory space remains permanently fixed in the same
location, eliminating the need to have portions of the code designed to run in different
address ranges.
Because of the location of the interrupt vectors on the ARM7 processor (at addresses
0x0000 0000 through 0x0000 001C, as shown in Table 2 below), a small portion of the
Boot Block and SRAM spaces need to be re-mapped in order to allow alternative uses of
interrupts in the different operating modes described in Table 3. Re-mapping of the
interrupts is accomplished via the Memory Mapping Control feature (Section 3.6 “Memory
mapping control” on page 25).
Table 2: ARM exception vector locations
Address Exception
0x0000 0000 Reset
0x0000 0004 Undefined Instruction
0x0000 0008 Software Interrupt
0x0000 000C Prefetch Abort (instruction fetch memory fault)
0x0000 0010 Data Abort (data access memory fault)
0x0000 0014 Reserved
Note: Identified as reserved in ARM documentation, this location is used
by the Boot Loader as the Valid User Program key. This is descibed in
detail in "Flash Memory System and Programming" chapter on page 216.
0x0000 0018 IRQ
0x0000 001C FIQ
Table 3: LPC2131/2/4/6/8 memory mapping modes
Mode Activation Usage
Boot
Loader
mode
Hardware
activation by
any Reset
The Boot Loader always executes after any reset. The Boot Block
interrupt vectors are mapped to the bottom of memory to allow
handling exceptions and using interrupts during the Boot Loading
process.
User
Flash
mode
Software
activation by
Boot code
Activated by Boot Loader when a valid User Program Signature is
recognized in memory and Boot Loader operation is not forced.
Interrupt vectors are not re-mapped and are found in the bottom of the
Flash memory.
UserRAM
mode Software activation by
User program
Activated by a User Program as desired. Interrupt vectors are
re-mapped to the bottom of the Static RAM.

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User manual Rev. 01 — 24 June 2005 13
Philips Semiconductors UM10120
Volume 1 Chapter 2: Memory map
2.2.2 Memory re-mapping
In order to allow for compatibility with future derivatives, the entire Boot Block is mapped
to the top of the on-chip memory space. In this manner, the use of larger or smaller flash
modules will not require changing the location of the Boot Block (which would require
changing the Boot Loader code itself) or changing the mapping of the Boot Block interrupt
vectors. Memory spaces other than the interrupt vectors remain in fixed locations.
Figure 6 shows the on-chip memory mapping in the modes defined above.
The portion of memory that is re-mapped to allow interrupt processing in different modes
includes the interrupt vector area (32 bytes) and an additional 32 bytes, for a total of
64 bytes. The re-mapped code locations overlay addresses 0x0000 0000 through
0x0000 003F. A typical user program in the Flash memory can place the entire FIQ
handler at address 0x0000 001C without any need to consider memory boundaries. The
vector contained in the SRAM,external memory, and Boot Block must contain branches to
the actual interrupt handlers, or to other instructions that accomplish the branch to the
interrupt handlers.
There are three reasons this configuration was chosen:
1. To give the FIQ handler in the Flash memory the advantage of not having to take a
memory boundary caused by the remapping into account.
2. Minimize the need to for the SRAM and Boot Block vectors to deal with arbitrary
boundaries in the middle of code space.
3. To provide space to store constants for jumping beyond the range of single word
branch instructions.
Re-mapped memory areas, including the Boot Block and interrupt vectors, continue to
appear in their original location in addition to the re-mapped address.
Details on re-mapping and examples can be found in Section 3.6 “Memory mapping
control” on page 25.

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Philips Semiconductors UM10120
Volume 1 Chapter 2: Memory map
Fig 6. Map of lower memory is showing re-mapped and re-mappable areas (LPC2138
with 512 kB Flash)
12 kB BOOT BLOCK
(RE-MAPPED FROM TOP OF FLASH MEMORY)
RESERVED ADDRESSING SPACE
32 kB ON-CHIP SRAM
0.0 GB ACTIVE INTERRUPT VECTORS (FROM FLASH, SRAM, OR BOOT BLOCK)
0x8000 0000
0x4000 8000
0x4000 7FFF
0x4000 0000
0x3FFF FFFF
0x0000 0000
0x7FFF FFFF
Note: Memory regions are not drawn to scale.
1.0 GB
2.0 GB - 12 kB
2.0 GB
(BOOT BLOCK INTERRUPT VECTORS)
(SRAM INTERRUPT VECTORS)
512 kB FLASH MEMORY
(12 kB BOOT BLOCK RE-MAPPED TO HIGHER ADDRESS RANGE) 0x0008 0000
0x0007 FFFF
RESERVED ADDRESSING SPACE

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Philips Semiconductors UM10120
Volume 1 Chapter 2: Memory map
2.3 Prefetch abort and data abort exceptions
The LPC2131/2/4/6/8 generates the appropriate bus cycle abort exception if an access is
attempted for an address that is in a reserved or unassigned address region. The regions
are:
•Areas of the memory map that are not implemented for a specific ARM derivative. For
the LPC2131/2/4/6/8, this is:
–Address space between On-Chip Non-Volatile Memory and On-Chip SRAM,
labelled "Reserved Address Space" in Figure 2 and Figure 6. For 32 kB Flash
device this is memory address range from 0x0000 8000 to 0x3FFF FFFF, for 64 kB
Flash device this is memory address range from 0x0001 0000 to 0x3FFF FFFF, for
128 kB Flash device this is memory address range from 0x0002 0000 to
0x3FFF FFFF, for 256 kB Flash device this is memory address range from
0x0004 0000 to 0x3FFF FFFF while for 512 kB Flash device this range is from
0x0008 0000 to 0x3FFF FFFF.
–Address space between On-Chip Static RAM and the Boot Block. Labelled
"Reserved Address Space" in Figure 2. For 8 kB SRAM device this is memory
address range from 0x4000 2000 to 0x7FFF CFFF, for 16 kB SRAM device this is
memory address range from 0x4000 4000 to 0x7FFF CFFF, while for 32 kB SRAM
device this range is from 0x4000 8000 to 0x7FFF CFFF.
–Address space between 0x8000 0000 and 0xDFFF FFFF, labelled "Reserved
Adress Space".
–Reserved regions of the AHB and VPB spaces. See Figure 3.
•Unassigned AHB peripheral spaces. See Figure 4.
•Unassigned VPB peripheral spaces. See Figure 5.
For these areas, both attempted data access and instruction fetch generate an exception.
In addition, a Prefetch Abort exception is generated for any instruction fetch that maps to
an AHB or VPB peripheral address.
Within the address space of an existing VPB peripheral, a data abort exception is not
generated in response to an access to an undefined address. Address decoding within
each peripheral is limited to that needed to distinguish defined registers within the
peripheral itself. For example, an access to address 0xE000 D000 (an undefined address
within the UART0 space) may result in an access to the register defined at address
0xE000 C000. Details of such address aliasing within a peripheral space are not defined
in the LPC2131/2/4/6/8 documentation and are not a supported feature.
Note that the ARM core stores the Prefetch Abort flag along with the associated
instruction (which will be meaningless) in the pipeline and processes the abort only if an
attempt is made to execute the instruction fetched from the illegal address. This prevents
accidental aborts that could be caused by prefetches that occur when code is executed
very near a memory boundary.

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User manual Rev. 01 — 24 June 2005 16
3.1 Summary of system control block functions
The System Control Block includes several system features and control registers for a
number of functions that are not related to specific peripheral devices. These include:
•Crystal Oscillator
•External Interrupt Inputs
•Memory Mapping Control
•PLL
•Power Control
•Reset
•VPB Divider
•Wakeup Timer
Each type of function has its own register(s) if any are required and unneeded bits are
defined as reserved in order to allow future expansion. Unrelated functions never share
the same register addresses
3.2 Pin description
Table 4 shows pins that are associated with System Control block functions.
UM10120
Chapter 3: System Control Block
Rev. 01 — 24 June 2005 User manual
Table 4: Pin summary
Pin name Pin
direction Pin description
X1 Input Crystal Oscillator Input - Input to the oscillator and internal clock
generator circuits
X2 Output Crystal Oscillator Output - Output from the oscillator amplifier
EINT0 Input External Interrupt Input 0 - An active low/high level or
falling/rising edge general purpose interrupt input. This pin may be
used to wake up the processor from Idle or Power-down modes.
Pins P0.1 and P0.16 can be selected to perform EINT0 function.
EINT1 Input External Interrupt Input 1 - See the EINT0 description above.
Pins P0.3 and P0.14 can be selected to perform EINT1 function.
Important: LOW level on pin P0.14 immediately after reset is
considered as an external hardware request to start the ISP
command handler. More details on ISP and Serial Boot Loader can
be found in "Flash Memory System and Programming" chapter on
page 216.

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual Rev. 01 — 24 June 2005 17
Philips Semiconductors UM10120
Volume 1 Chapter 3: System Control Block
3.3 Register description
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
[1] Reset value relects the data stored in used bits only. It does not include reserved bits content.
EINT2 Input External Interrupt Input 2 - See the EINT0 description above.
Pins P0.7 and P0.15 can be selected to perform EINT2 function.
EINT3 Input External Interrupt Input 3 - See the EINT0 description above.
Pins P0.9, P0.20 and P0.30 can be selected to perform EINT3
function.
RESET Input External Reset input - A LOW on this pin resets the chip, causing
I/O ports and peripherals to take on their default states, and the
processor to begin execution at address 0x0000 0000.
Table 4: Pin summary
Pin name Pin
direction Pin description
Table 5: Summary of system control registers
Name Description Access Reset
value[1] Address
External Interrupts
EXTINT External Interrupt Flag Register R/W 0 0xE01F C140
EXTWAKE External Interrupt Wakeup Register R/W 0 0xE01F C144
EXTMODE External Interrupt Flag register R/W 0 0xE01F C148
EXTPOLAR External Interrupt Wakeup Register R/W 0 0xE01F C14C
Memory Mapping Control
MEMMAP Memory Mapping Control R/W 0 0xE01F C040
Phase Locked Loop
PLLCON PLL Control Register R/W 0 0xE01F C080
PLLCFG PLL Configuration Register R/W 0 0xE01F C084
PLLSTAT PLL Status Register RO 00xE01F C088
PLLFEED PLL Feed Register WO NA 0xE01F C08C
Power Control
PCON Power Control Register R/W 0 0xE01F C0C0
PCONP Power Control for Peripherals R/W 0x03BE 0xE01F C0C4
VPB Divider
VPBDIV VPB Divider Control R/W 0 0xE01F C100
Reset
RSID Reset Source Identification Register R/W 0 0xE01F C180
Code Security/Debugging
CSPR Code Security Protection Register RO o0xE01F C184

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual Rev. 01 — 24 June 2005 18
Philips Semiconductors UM10120
Volume 1 Chapter 3: System Control Block
3.4 Crystal oscillator
While an input signal of 50-50 duty cycle within a frequency range from 1 MHz to 50 MHz
can be used by the LPC2131/2/4/6/8 if supplied to its input XTAL1 pin, this
microcontroller’s onboard oscillator circuit supports external crystals in the range of 1 MHz
to 30 MHz only. If the on-chip PLL system or the boot-loader is used, the input clock
frequency is limited to an exclusive range of 10 MHz to 25 MHz.
The oscillator output frequency is called FOSC and the ARM processor clock frequency is
referred to as CCLK for purposes of rate equations, etc. elsewhere in this document. FOSC
and CCLK are the same value unless the PLL is running and connected. Refer to the
Section 3.7 “Phase Locked Loop (PLL)” on page 26 for details and frequency limitations.
The onboard oscillator in the LPC2131/2/4/6/8 can operate in one of two modes: slave
mode and oscillation mode.
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
(CCin Figure 7, drawing a), with an amplitude of at least 200 mVrms. The X2 pin in this
configuration can be left not connected. If slave mode is selected, the FOSC signal of 50-50
duty cycle can range from 1 MHz to 50 MHz.
External components and models used in oscillation mode are shown in Figure 7,
drawings b and c, and in Table 6. Since the feedback resistance is integrated on chip, only
a crystal and the capacitances CX1 and CX2 need to be connected externally in case of
fundamental mode oscillation (the fundamental frequency is represented by L, CLand
RS). Capacitance CPin Figure 7, drawing c, represents the parallel package capacitance
and should not be larger than 7 pF. Parameters FC, CL, RSand CPare supplied by the
crystal manufacturer.
Choosing an oscillation mode as an on-board oscillator mode of operation limits FOSC
clock selection to 1 MHz to 30 MHz.
Fig 7. Oscillator modes and models: a) slave mode of operation, b) oscillation mode of
operation, c) external crystal model used for CX1/X2 evaluation
LPC2131/2/4/6/8 LPC2131/2/4/6/8
X1X1 X2X2
Clock
CC
CX1 CX2
CLCP
L
RS
< = >
a) b) c)
Xtal

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual Rev. 01 — 24 June 2005 19
Philips Semiconductors UM10120
Volume 1 Chapter 3: System Control Block
Table 6: Recommended values for CX1/X2 in oscillation mode (crystal and external
components parameters)
Fundamental
oscillation frequency
FC
Crystal load
capacitance CL
Maximum crystal
series resistance RS
External load
capacitors CX1, CX2
1 MHz - 5 MHz 10 pF NA NA
20 pF NA NA
30 pF < 300 Ω58 pF, 58 pF
5 MHz - 10 MHz 10 pF < 300 Ω18 pF, 18 pF
20 pF < 300 Ω38 pF, 38 pF
30 pF < 300 Ω58 pF, 58 pF
10 MHz - 15 MHz 10 pF < 300 Ω18 pF, 18 pF
20 pF < 220 Ω38 pF, 38 pF
30 pF < 140 Ω58 pF, 58 pF
15 MHz - 20 MHz 10 pF < 220 Ω18 pF, 18 pF
20 pF < 140 Ω38 pF, 38 pF
30 pF < 80 Ω58 pF, 58 pF
20 MHz - 25 MHz 10 pF < 160 Ω18 pF, 18 pF
20 pF < 90 Ω38 pF, 38 pF
30 pF < 50 Ω58 pF, 58 pF
25 MHz - 30 MHz 10 pF < 130 Ω18 pF, 18 pF
20 pF < 50 Ω38 pF, 38 pF
30 pF NA NA
Fig 8. FOSC selection algorithm
True
MIN f
OSC = 10 MHz
MAX fOSC = 25 MHz
True
MIN fOSC = 1 MHz
MAX fOSC = 50 MHz MIN fOSC = 1 MHz MAX fOSC = 30 MHz
(Figure 7, mode a and/or b) (Figure 7, mode a) (Figure 7, mode b)
On-chip PLL used
in application?
ISP used for initial
code download?
External crystal
oscillator used? True
False
False
False
fOSC selection

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual Rev. 01 — 24 June 2005 20
Philips Semiconductors UM10120
Volume 1 Chapter 3: System Control Block
3.5 External interrupt inputs
The LPC2131/2/4/6/8 includes four External Interrupt Inputs as selectable pin functions.
The External Interrupt Inputs can optionally be used to wake up the processor from
Power-down mode.
3.5.1 Register description
The external interrupt function has four registers associated with it. The EXTINT register
contains the interrupt flags, and the EXTWAKEUP register contains bits that enable
individual external interrupts to wake up the microcontroller from Power-down mode. The
EXTMODE and EXTPOLAR registers specify the level and edge sensitivity parameters.
[1] Reset value relects the data stored in used bits only. It does not include reserved bits content.
3.5.2 External Interrupt Flag register (EXTINT - 0xE01F C140)
When a pin is selected for its external interrupt function, the level or edge on that pin
(selected by its bits in the EXTPOLAR and EXTMODE registers) will set its interrupt flag in
this register. This asserts the corresponding interrupt request to the VIC, which will cause
an interrupt if interrupts from the pin are enabled.
Writing ones to bits EINT0 through EINT3 in EXTINT register clears the corresponding
bits. In level-sensitive mode this action is efficacious only when the pin is in its inactive
state.
Once a bit from EINT0 to EINT3 is set and an appropriate code starts to execute (handling
wakeup and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise
the event that was just triggered by activity on the EINT pin will not be recognized in the
future.
Important: whenever a change of external interrupt operating mode (i.e. active
level/edge) is performed (including the initialization of an external interrupt), the
corresponding bit in the EXTINT register must be cleared! For details see Section
3.5.4 “External Interrupt Mode register (EXTMODE - 0xE01F C148)”and Section 3.5.5
“External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)”.
Table 7: External interrupt registers
Name Description Access Reset
value[1] Address
EXTINT The External Interrupt Flag Register contains
interrupt flags for EINT0, EINT1, EINT2 and
EINT3. See Table 8.
R/W 00xE01F C140
INTWAKE The Interrupt Wakeup Register contains four
enable bits that control whether each external
interrupt will cause the processor to wake up
from Power-down mode. See Table 9.
R/W 00xE01F C144
EXTMODE The External Interrupt Mode Register controls
whether each pin is edge- or levelsensitive. R/W 00xE01F C148
EXTPOLAR The External Interrupt Polarity Register controls
which level or edge on each pin will cause an
interrupt.
R/W 00xE01F C14C