Prestigio NOBILE 150 Operating manual

PRESTIGIO NOBILE 150
TECHNICAL SERVICE MANUAL

Contents
1. Hardware Engineering Specification ……………………………………………………………………….
1.1 Introduction …………………………………………………………………………………………………………………
1.2 Other Functions ……………………………………………………………………………………………………………
1.3 Peripheral Components …………………………………………………………………………………………………...
1.4 Power Management ………………………………………………………………………………………………………..
1.5 Appendix 1 : Intel 82801DBM ICH4-M GPIO Definitions ……………………………………………………………...
1.6 Appendix 2 : Prestigio Nobile 150 Product Specification ……………………………………………………………….
2. System View and Disassembly ……………………………………………………………………………...
2.1 System View ………………………………………………………………………………………………………………..
2.2 System Disassembly ………………………………………………………………………………………………………..
3. Definition & Location of Connectors / Switches …………………………………………………………..
3.1 Mother Board-A …………………………………………………………………………………………………………….
3.2 Mother Board-B …………………………………………………………………………………………………………….
4. Definition & Location of Major Components ……………………………………………………………..
4.1 Mother Board-A ……………………………………………………………………………………………………………
4.1 Mother Board-B ……………………………………………………………………………………………………………
5. Pin Description of Major Component …….………………………………………………………………..
5.1 Intel Pentium M Processor ………………………………………………………………………………………………..
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Contents
5.2 Intel Montara-GME Memory Controller Hub (GMCH) ……………………………………………………………….
5.3 Intel 82801DBM I/O Controller Hub Mobile (ICH4-M) ………………………………………………………………..
6. System Block Diagram ………………………………………………………………………………………
7. Maintenance Diagnostics ……………………………………………………………………………………
7.1 Introduction ………………………………………………………………………………………………………………..
7.2 Maintenance Diagnostics…………………………………………………………………………………………………..
7.3 Error Codes ………………………………………………………………………………………………………………..
8. Trouble Shooting …………………………………………………………………………………………….
8.1 No Power ……………………………………………………………………………………………………………………
8.2 No Display ………………………………………………………………………………………………………………….
8.3 VGA Controller Failure LCD No Display ………………………………………………………………………………..
8.4 External Monitor No Display ……………………………………………………………………………………………..
8.5 Memory Test Error ………………………………………………………………………………………………………..
8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error ……………………………………………………………………………
8.7 Hard Driver Test Error ……………………………………………………………………………………………………
8.8 CD-ROM Driver Test Error ………………………………………………………………………………………………
8.9 USB Port Test Error ……………………………………………………………………………………………………….
8.10 Audio Failure ……………………………………………………………………………………………………………..
8.11 LAN Test Error …………………………………………………………………………………………………………..
8.12 PC Card Socket Failure ………………………………………………………………………………………………….
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Contents
8.13 TV Test Error….………………………………………………………………………………………………………….
9. Spare Parts List ……………………………………………………………………………………………...
10. System Exploded Views ……………………………………………………………………………………
11. Circuit Diagram …………………………………………………………………………………………….
12. Reference Material …………………………………………………………………………………………
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1.1 Introduction
1. Hardware Engineering Specification
This document describes the brief introduction for Prestigio Nobile 150 portable notebook computer system.
1.1.1 General Description
The Nobile 150 model is designed for Intel Banias processor with 400MHz FSB with Micro-FCPGA package. It
can support Banias 1.3GHz ~ 1.7GHz. ,Dothan 1.7GHz ~ 1.9GHz, and Banias Celeron 1.2GHz ~ 1.4GHz.
This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which has standard
hardware peripheral interface. The power management complies with Advanced Configuration and Power Interface
(ACPI) 2.0. It also provides easy configuration through CMOS setup, which is built in system BIOS software and can
be pop-up by pressing F2 key at system start up or warm reset. System also provides icon LEDs to display system
status, such as AC Power indicator, Battery Power indicator, Battery status indicator, CD-ROM, HDD, NUM LOCK,
CAP LOCK, and SCROLL LOCK. It also equipped with LAN, 56K Fax MODEM, 4 USB port, 3D stereo audio
functions, S-Video and audio line out, and internal microphone.
The memory subsystem supports two expansion DDR SDRAM slot with unbuffered PC2100/PC2700 DDR-SDRAM
1.1.2 System Overview
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The Montara-GME GMCH Host Memory Controller integrates a high performance host interface for Intel Banias
processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, Digital Video port
(DVOB & DVOC) interface, and Intel Hub interface Technology connecting with Intel 82801DBM ICH4-M.
The Intel ICH4-M integrates three Universal Serial Bus 2.0 Host Controllers Interface (UHCI), the Audio
Controller with AC97 interface, the Ethernet includes a 32-bit PCI controller , the IDE Master/Slave controllers,
and Intel Hub interface technology.
The VIA VT6105LOM “Rhine III” Ethernet controller is a cutting edge, feature-rich, and cost-competitive single
ASIC chip solution for PC “LAN On Motherboard” applications or Low Cost NIC applications. The 6105LOM
eases server processor utilization by optimizing throughput between NIC and PCI bus allowing data transfers of up
to at 200Mbps in full duplex mode, without using the system CPU. The VT6105LOM contains advanced power
management feature for low power consumption including Wake On LAN (WOL) and is implemented using a low
power 0.22 micron design.
The TIE PCI1410A device is a high-performance PCI-to-PC Card controller that supports a single PC Card socket
compliant with the PC Card Standard. The PCI1410A device provides features that make it the best choice for
bridging between PCI and PC Cards in both notebook and desktop computers. The PC Card Standard retains the 16-
bit PC Card specification defined in PCI Local Bus Specification and defines the new 32-bit PC Card, CardBus, as
being capable of full 32-bit data transfers at 33 MHz. The PCI1410A device supports both 16-bit and CardBus PC
Cards, powered at 5 V or 3.3 V, as required.
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The ALC101 is an 18-bit, full duplex AC'97 2.2 compatible stereo audio CODEC designed for PC multimedia
systems, including host/soft audio and AMR/CNR based designs. The ALC101 AC'97 CODEC supports multiple
CODEC extensions with independent variable sampling rates and built-in 3D effects. The ALC101 CODEC
provides a pair of stereo outputs with independent volume controls and multiple stereo and mono inputs, along with
flexible mixing, gain and mute functions to provide a complete integrated audio solution for PCs. The digital
interface circuitry of the ALC101 CODEC operates from a 5V/3.3V power supply with EAPD (External Amplifier
Power Down) control for use in notebook and PC applications. The ALC101 integrates a 50mW/20ohm headset
audio amplifier into the CODEC, saving BOM costs.
The CH7011A is a display controller device which accepts a digital graphics input signal, and encodes and transmits
data to a TV output (analog composite, s-video or RGB). The device accepts data over one 12-bit wide variable
voltage data port which supports five different data format including RGB and YcrCb. The TV-Out processor will
perform non-interlace to interlace conversion with scaling and flicker filters, and encode the data into any of the
NTSC or PAL video standards. The scaling and flicker filter is adaptive and programmable to enable superior text
display. Eight graphics resolutions are supported up to 1024 X 768 with full vertical and horizontal underscan
capability in all modes. A high accuracy low jitter phase locked loop is integrated to create outstanding video
quality. Support is provided for Macrovision and RGB bypass mode which enable driving a VGA CRT with the
input data.
The Winbond mobile keyboard and embedded controller W83L950D architecture consists of a Turbo-51 core logic
controller and surrounded by various components, 2K+256 bytes of RAM, 40K on-chip MTP-ROM, ISA or
LPChost interface, 9 general purpose I/O port with 13 external interrupt source, 4 timers, 2 serial port, 2 SMBus
interface for master and slave, 3 PS2 port, two 8-bits and two 16-bits PWM channels, 2 D-A and 8 A-D converters.
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A full set of software drivers and utilities are available to allow advanced operating systems such as Windows XP to
take full advantage of the hardware capabilities. Features such as bus mastering IDE, Plug and Play, Advanced Power
Management (APM) with application restart, software-controlled power shutdown.
Following chapters will have more detail description for each individual sub-systems and functions.
System Parts
CPU : Intel Banias processor in Micro-FCPGA package
Synthesizer : PLL207-151
North Bridge : Montara-GME GMCH
South Bridge : ICH4-M
TV-Out : CH7011A
Keyboard System: Winbond W83L950D Universal Controller
Fax/Modem : Billonton MDC56S-I56Kbps Fax Modem
LAN Single Chip : VT6105LOM
PCMCIA Controller : TIPC1410A
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AC’97 Codec : ALC101
Thermal Sensor : ADT7460
System Flash Memory (BIOS)
1.1.2.1 CPU Module : Banias
Intel Banias Processors with 478 pins Micro-FCPGA package.
The first Intel mobile processor with the Intel NetBurst micro-architecture which features include hyper-
pipelined technology, a rapid execution engine, a 400MHz system, an execution trace cache, advanced
dynamic execution, advanced transfer cache, enhanced floating point and multi-media unit, and Streaming
SIMD Extensions 2 (SSE2).
The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia
applications including 3-D graphics, video decoding/encoding, and speech recognition.
Use Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data
four times per bus clock.
Support Enhanced Intel SpeedStep technology, which enables real-time dynamic switching of the
voltageand frequency between two performance modes.
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1.1.2.2 Synthesizer : PLL207-151
System frequency synthesizer: PLL207-151
Programmable output frequency, divider ratios, output rise/fall time, output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system if system malfunctions.
Programmable watchdog safe frequency.
Support I2C Index read/write and block read/write operations.
Use external 14.318MHz crystal.
1.1.2.3 Montara-GME GMCH IGUI 3D Graphic DDR/SDR Chipset
Montara-GME GMCH IGUI Host Memory Controller integrates a high performance host interface for Intel
Banias processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP
4X interface, and Intel®’ I/O Hub architecture INTEL 82801DBM ICH4-M.
Montara-GME GMCH Host Interface features the AGTL & AGTL+ compliant bus driver technology with
integrated on-die termination to support Intel Banias processors. Montara-GME GMCH provides a 12-deep In-
Order-Queue to support maximum outstanding transactions up to 12. It integrated a high performance 2D/3D
Graphic Engine, Video Accelerator and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for
the Intel Banias series based PC systems. It also integrates a high performance DDR333 Memory controller to
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sustain the bandwidth demand from the integrated GUI or external AGP master, host processor, as well as the
multi I/O masters. In addition to integrated GUI, Montara-GME GMCH also can support external AGP slot with
AGP 1X/2X/4X capability and Fast Write Transactions. A high bandwidth and mature Intel®’ I/O Hub
architecture is incorporated to connect Montara-GME GMCH and INTEL 82801DBM ICH4-Mtogether. Intel®’
I/O Hub architecture is developed into three layers, the Multi-threaded I/O Link Layer delivering 1.2GB
bandwidth to connect embedded DMA Master devices and external PCI masters to interface to Multi-threaded
I/O Link layer, the Multi-threaded I/O Link Encoder/Decoder in INTEL 82801DBM ICH4-M to transfer
dataw/533MB/s bandwidth from/to Multi-threaded I/O Link layer to/from Montara-GME GMCH, and the Multi-
threaded I/O Link Encoder/Decoder in Montara-GME GMCH to transfer data w/533MB/s from/to Multi-
threaded I/O Link layer to/from INTEL 82801DBM ICH4-M.
An Unified Memory Controller supporting DDR333 DRAM is incorporated, delivering a high performance data
transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine or external AGP
master, or the I/O bus masters. The memory controller also supports the Suspend to RAM function by retaining
the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The Montara-GME GMCH
adopts the Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by
organizing the frame buffer in the system memory. The frame buffer size can be allocated from 8MB to 64MB.
Processor/Host Bus Support
Processor/Host Bus SupportProcessor/Host Bus Support
Processor/Host Bus Support
Features :
•Intel®Banias processor
•2X Address, 4X Data
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•Support host bus Dynamic Bus Inversion (DBI)
•Supports system bus at 400MT/s (100 MHz)
•Supports 64-bit host bus addressing
•8-deep In-Order-Queue
•AGTL+ bus driver technology with integrated GTL termination resistors and low voltage operation
(1.05V)
•Supports Enhanced Intel®SpeedStepTM Technology (EIST) and Geyserville III
•Support for DPWR# signal to Banias processor for PSB power management
Memory System
•Directly supports one DDR channel, 64-bits wide (72-b with ECC)
•Supports up 2 Double-Sided SO-DIMMs(4 rows populated) with unbuffered PC1600/PC2100/PC2700
DDR (with or without ECC)
•Supports 128-Mb, 256-Mb and 512-Mbit technologies providing maximum capacity of 1-GB with only x
16 devices
•All supported devices have 4 banks
•Supports up to 16 simultaneous open pages
•Supports page sizes of 2KB, 4KB, 8KB, and 16KB. Page size is individually selected for every row
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•Support for memory self refresh in C3
•UMA support only
System Interrupt
•Supports 8259 and Processor System Bus interrupt delivery mechanism
•Supports interrupts signaled as upstream Memory Writes from PCI and Hub interface
•MSI sent to the CPU through the system Bus
•From IOxAPIC in ICH4-M
•Provides redirection for upstream interrupts to the System Bus
•Video Stream Decoder
•Improved HW Motion Compensation for MPEG2
•All format decoder (18 ATSC formats) supported
•Dynamic Bob and Weave support for Video Streams
•Software DVD at 60 fields/second and 30 frames/second full screen
•Support for 720x480 pixel resolution DVD quality encoding at low CPU utilization
•Video Overlay
•Single high quality scalable overlay and second Sprite to support second overlay
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•Multiple overlay functionality provided viaArithmetic Stretch Blt
•Direct YUV from Overlay to TV-out
•Independent Gamma Correction
•Independent Brightness / Contrast / Saturation
•Independent Tint / Hue support
•Destination Color keying
•Source Chromakeying
•Maximum source resolution of 1920x1080 pixels
•Maximum overlay clock of 133 MHz/200 MHz provides a pixel resolution up to 1600x1200@ 60Hz or
1280x1024@ 85 Hz
Display
•Analog Display Support
•350 MHz integrated 24-bit RAMDAC that can drive a standard progressive scan analog monitor up to
1800x1350 @ 85 Hz
•Accompanying I2C and DDC channels provided through multiplexed interface Hotplug and display
support
•Dual independent pipe with single display support Simultaneous: Same images and native display timings
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on each display device
•Dedicated LFP (local flat panel) interface
Single l LVDS panel support up to SXGA+ panel resolution with frequency range from 25MHz to
112MHz per channel
Supports data format of 24 bpp
LCD panel power sequencing compliant with SPWG timing specification
Compliant with ANSI/TIA/EIA –644-1995 spec
Integrated PWM interface for LCD backlight inverter control
Bi-linear Panel fitting
•Tri-view support through LFP interface, TV ports and CRT
•Internal Graphics Features
•Core Frequency
Display Core frequency of 133MHz,200MHz,250MHz
Render Core frequency of 100 MHz, 133 MHz, 166 MHz, 200 MHz, 250 MHz
Intel® Dual-Frequency Graphics Technology
•2D Graphics Engine
•Optimized 128 bit BLT engine
•Ten programmable and predefined monochrome patterns
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•Alpha Stretch Blt (via 3D pipeline)
•Anti-aliased lines
•Hardware-based BLT Clipping & Scissoring
•32-bit Alpha Blended cursor
•Programmable 64*64 3-color Transparent cursor
•Color Space Conversion
•3 Operand Raster BLTs
•8-bit, 16-bit, and 32-bit color
•ROP support
•DIB translation and Linear/Title addressing
•3D Graphics Engine
•3D Setup and Render Engine
•Viewpoint Transform and Perspective Divide
•Triangle Lists, Strips and Fans support
•Indexed Vertex and Flexible Vertex formats
•Pixel accurate Fast Scissoring and Clipping operation
•Backface Culling support
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•DirectXTM and OGL Pixelization rules
•Enhanced Hardware Binning Instruction Set supported
•Bi-Cubic Filtering supported
•Linear Gamma Blending for Video Mixer Rendering (VMR)
•Video Mixer Rendering (VMR) supported
•Anti-Aliased Lines support
•Sprite Points support
•Zone Rendering
•Provides the highest sustained fill rate performance in 32-bit color and 24-bit W mode
•High quality performance Texture Engine
•266 Mega Texel/speak performance
•Per Pixel Perspective corrected Texture Mapping
•Single Pass Texture Compositing (Multi-Texture) at rate
•Enhanced Texture Blending functions
•Twelve Level of Detail MIP Map Sizes from 1x1 to 2Kx2K
•Numerous Texture formats including 32-bit RGBA
•Alpha and Luminance Maps
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•Texture Chromakeying
•Bilinear, Trilinear, Anisotropic MIP-Mapped Filtering
•Cubic Environment Reflection Mapping
•Embossed Bump-mapping
•DXTn Texture Decompression
•3D Graphics Rasterrization enhancements
•One Pixel per Clock
•Flat and Gouraud Shading
•Color Alpha Blending for Transparency
•Vertex and Programmable Pixel Fog and Atmospheric effects
•Color Specular Lighting
•Vertex and Programmable Pixel Fog and Atmospheric effects
•Z Bais support
•Dithering
•Line and Full-Scence Anti-Aliasing
•16 and 24-bit Z Buffering
•16 and 24-bit W Buffering
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•8-bit Stencil Buffering
•Double and Triple Render Buffer support
•16 and 32 –bit color
•Destination Alpha
•Vertex Cahec
•Maximum 3D resolution of 1600x1200 x32 bpp at 85 Hz
•Optimal 3D resolution supported
•Fast Clear support
•ROP support
HUB Interface for ICH4
•533 MB/s point to point hub interface to ICH4-M
•66-M Hz base clock
•Supports the following traffic types to the ICH4-M
•Hub interface-to DRAM
•CPU-to-Hub interface
•Messaging
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•MSI interrupt messages
•Power Management state change
•SMI, SCI, and SERR error indication
•Power Management
SMRAM space remapping to A0000h (128-KB)
Supports extended SMRAM space above 256- MB ,additional 1 MB TSEG from top of Memory,
cacheable (cacheability controlled by CPU)
APM rev 1.2 compliant power management
Supports Suspend to System Memory(S3),Suspend to Disk(S4) and Hard Off/Total Reboot(S5)
ACPI 1.0b,2.0 Support
1.1.2.4 I/O Controller Hub : Intel 82801DBM
The Intel 82801DBM ICH4-M integrates three Universal Serial Bus 2.0 Host Controllers, the Audio Controller
with AC 97 Interface, the IDE Master/Slave controllers, and Intel® I/O Hub architecture. The PCI to LPC
Bridge, I/O Advanced Programmable Interrupt Controller, legacy system I/O and legacy power management
functionalities are integrated as well.
The integrated Universal Serial Bus Host Controllers features Dual Independent UHCI Compliant Host
controllers with six USB ports delivering 480 Mb/s bandwidth and rich connectivity. Besides, Legacy USB
devices as well as over current detection are also implemented.
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