Prestigio NOBILE 1510 Operating manual

PRESTIGIO NOBILE 1510
TECHNICAL SERVICE MANUAL

Contents
1. Hardware Engineering Specification……………………………………………………………………….
1.1 Introduction ………………………………………………………………………………………………………………..
1.2 System Overview …………………………………………………………………………………………………………..
1.3 System Hardware Parts …………………………………………………………………………………………………...
1.4 Other Functions ……………………………………………………………………………………………………………
1.5 Power Management ………………………………………………………………………………………………………..
1.6 Appendix 1: Intel ICH6-M GPIO Definitions ……………………………………………………………………………
1.7 Appendix 2: W83L950D KBC Pin Definitions …………………………………………………………………………..
1.8 Appendix 3: Nobile 1510 Product Specifications ……………………………………………………………………………
2. System View and Disassembly ……………………………………………………………………………...
2.1 System View ………………………………………………………………………………………………………………..
2.2 System Disassembly ………………………………………………………………………………………………………..
3. Definition & Location of Connectors / Switches …………………………………………………………..
3.1 Mother Board (Side A) ……………………………………………………………………………………………………
3.2 Mother Board (Side B) ……………………………………………………………………………………………………
3.3 Daughter Board…………………………………………………………………………………………………………….
4. Definition & Location of Major Components ……………………………………………………………..
4.1 Mother Board (Side A) ……………………………………………………………………………………………………
4.2 Mother Board (Side B) ……………………………………………………………………………………………………
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Contents
5. Pin Description of Major Component …….……………………………………………………………….
5.1 Intel 915GM North Bridge ……………………………………………………………………………………………….
5.2 Intel ICH6-M South Bridge ………………………………………………………………………………………………
6. System Block Diagram ………………………………………………………………………………………
7. Maintenance Diagnostics ……………………………………………………………………………………
7.1 Introduction ………………………………………………………………………………………………………………..
7.2 Maintenance Diagnostics…………………………………………………………………………………………………..
7.3 Error Codes ………………………………………………………………………………………………………………..
8. Trouble Shooting …………………………………………………………………………………………….
8.1 No Power ……………………………………………………………………………………………………………………
8.2 No Display ………………………………………………………………………………………………………………….
8.3 VGA Controller Failure LCD No Display ………………………………………………………………………………..
8.4 External Monitor No Display ……………………………………………………………………………………………..
8.5 Memory Test Error ………………………………………………………………………………………………………..
8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error ……………………………………………………………………………
8.7 Hard Driver Test Error ……………………………………………………………………………………………………
8.8 CD-ROM Driver Test Error ………………………………………………………………………………………………
8.9 USB Port Test Error ……………………………………………………………………………………………………….
8.10 Audio Failure ……………………………………………………………………………………………………………..
8.11 LAN Test Error …………………………………………………………………………………………………………..
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Contents
8.12 PC Card Socket Failure …………………………………………………………………………………………………
9. Spare Parts List ……………………………………………………………………………………………...
10. System Exploded Views …………………………………………………………………………………….
11. Circuit Diagram …………………………………………………………………………………………….
12. Reference Material ………………………………………………………………………………………… 186
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1.1 Introduction
1. Hardware Engineering Specification
The Prestigio Nobile 1510 model is designed for Intel Mobile Pentium-M Processor and Celeron-M Processor,Dothan
400 and 533 FSB.
This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which has standard
hardware peripheral interface. The power management complies with Advanced Configuration and Power Interface.
It also provides easy configuration through CMOS setup, which is built in system BIOS software and can be pop-up
by pressing F2 key at system start up or warm reset. System also provides icon LEDs to display system status, such
as Wireless LAN indicator, AC/Battery Power indicator, Battery status indicator, CD-ROM, HDD, NUM LOCK,
CAP LOCK, SCROLL LOCK. It also equipped with GIGA LAN, 56K Fax MODEM, 3 USB port, S-Video, line in,
SPIDIF, and internal/external microphone function.
The memory subsystem supports DDR2 SDRAM channels (64-bits wide).
The 915GM MCH Host Memory Controller integrates a high performance host interface for Intel Dothan processor,
a high performance PCI Express interface, a high performance memory controller, Digital Video port (DVOB &
DVOC) interface, and Direct Media Interface (DMI) connecting with Intel ICH6-M.
The Intel ICH6-M integrates three Universal Serial Bus 2.0 Host Controllers Interface (UHCI), the Audio
Controller with Azalia interface, the Ethernet includes a 32-bit PCI controller, the IDE Master/Slave controllers, the
SATA controller and Direct Media Interface technology.
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Intel Graphics enhancements includes DVMT 3.0, Zone Rendering 2.0, Quad pixel pipe rendering engine, Pixel
Shader 2.0 and 4x Faster Setup Engine.
The Realtek RTL8110SBL is a highly integrated, cost-effective single-chip Fast Ethernet controller that provides
32-bit performance, PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T specifications and
IEEE 802.3x Full Duplex Flow Control. It also supports the Advanced Configuration Power management Interface
(ACPI).
The Texas Instruments PCI4510 device is compliant with PCI Local Bus Specification. Function 0 provides the
independent PC Card socket controller compliant with the latest PC Card Standards. Function 1 of the PCI4510
device is an integrated IEEE 1394a-2000 open host controller interface (OHCI)PHY/link-layer controller (LLC)
device that is fully compliant with the PCI Local Bus Specification, the PCI Bus Power Management Interface
Specification, IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open Host Controller Interface
Specification.
The ALC655 is a 16-bit, full duplex AC97 2.3 compatible six channels audio CODEC designed for PC multimedia
systems, including host/soft audio and AMR/CNR based designs. The ALC655 incorporates proprietary converter
technology to meet performance requirements on PC99/2001 systems.
The W83L950D is a high performance microcontroller on-chip supporting functions optimized for embedded
control. These include ROM, RAM, four types of timers, a serial communication interface, optional I²C bus
interface, host interface, A/D converter, D/A converter, I/O ports, and other functions needed in control system
configurations, so that compact, high performance systems can be implemented easily.
A full set of software drivers and utilities are available to allow advanced operating systems such as Windows ME,
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Windows 2000 and Windows XP to take full advantage of the hardware capabilities. Features such as bus mastering
IDE, Plug and Play, Advanced Power Management (APM) with application restart, software-controlled power
shutdown.
Following chapters will have more detail description for each individual sub-systems and functions.
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1.2 System Overview
CPU Intel: Pentium M 735 Dothan 1.7GHz, 400FSB
Intel: Pentium M 770 Dothan 2.13GHz, 533FSB
Thermal spec 27W TDP
Core logic Intel 915GM + ICH6-M chipset
System BIOS W39V040FAP
Memory DDR2 RAM: MT8HTF3264HDY-53EB3 (256Mx2)
Nanya 533,256MB,NT256T64UH4A0FM-37B
HDD Fujitsu:MHT2060AT+ , 60GB
ODD KME: UJ-831BMT-A DVD Dual
KME: UJDA760 DVD Combo
Display 15”: Hydis,HT15X34-110
AU: B150XG01
Clock Generator ICS 954226
TV Intel 915GM
LAN RTL8110SBL
PCMCIA +
IEEE1394 TI PCI4510
Audio System AC’97 CODEC: ALC655
Power Amplifier: TI TPA0212
Modem Askey 1456VQL4A(INT)
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1.3 System Hardware Parts
1.3.1 Intel Dothan Processors in Micro-FCBGA package
Intel Dothan Processors with 479 pins Micro-FCBGA package.
It will be manufactured on Intel’s advanced 90 nanometer process technology with copper interconnect. It’s features
include Intel Architecture with Dynamic Execution, On-die primary 32-kB instruction cache and 32-kB write-back
data cache, on-die 2-MB second level cache with advanced Transfer Cache Architecture, Data Prefetch Logic,
Streaming SIMD Extensions 2 (SSE2), 533-MHz FSB.
The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications
including 3-D graphics, video decoding/encoding, and speech recognition.
Use Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four
times per bus clock.
Support Enhanced Intel SpeedStep technology, which enables real-time dynamic switching of the voltage and
frequency between two performance modes.
1.3.2 Clock Generator
System frequency synthesizer: ICS954226 is a CK410M Compliant clock synthesizer. It provides a single-chip
solution for mobile systems built with Intel P4-M processors and Intel mobile chipsets. It is driven with a
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1.3.3 The Mobile Intel 915GM Express Chipset
•Supports tight ppm accuracy clocks for Serial-ATA and SRC
•Supports spread spectrum modulation, 0 to –0.5% down spread
•Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning
•Supports undriven differential CPU, SRC pair in PD# for power management
14.318MHz crystal and generates CPU outputs up to 400MHz. It provides the tight ppm accuracy required by Serial
ATA and PCI-Express.
The Mobile Intel 915GM Express Chipset is a memory controller hub (GMCH) designed for use with the Dothan,
Yonah and Intel Celeron M Processor. It supports Intel Graphics Media Accelerator 900 & PCI Express based
Graphics.
The 915GM GMCH integrates a system memory DDR/DDR2 controller with two, 64-bit wide interfaces. Only
Double Data Rate (DDR/DDR2) memory is supported; the buffers support DDR SSTL_2 and DDR2 SSTL_18
signaling interfaces. The memory controller interface is fully configurable through a set of control registers. It
supports a high performance transition interface PCI Express Interface. PCI Express operates at a data rate of 2.5
GB/s. This allows a maximum theoretical bandwidth of 40 GB/s each direction. The 915GM GMCH integrates
Direct media interface (DMI) chip-to-chip interconnect between the GMCH and ICH6-M. DMI supports DMI x2
and DMI x4 configuration.
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Processor/FSB Support
•Intel®Dothan processor
•AGTL+ bus driver technology with integrated GTL termination resistors (gated AGTL+ receivers for
reduced power)
•Supports 32-bit AGTL+ host bus addressing
•Supports system bus at 533MT/s (533 MHz) and 400MT/s (400 MHz)
•2X Address, 4X data
•Host bus dynamic bus inversion HDINV support
•12 deep, in-order queue
Memory System
•Directly supports to two DDR or DDR2 SDRAM channels, 64-bts wide
•Supports SO-DIMMs of the same type (e.g.,all DDR or all DDR2), not mixed
•Maximum of two, double-sided unbuffered SO-DIMMs (4 rows populated)
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•Minimum amount of memory supported is 128 MB (16 MB x 16-b x 4 devices x 1 rows = 128 MB) using
256-MB technology
•Maximum amount of memory supported is 2 GB using 1-GB technology
•256-MB, 512-MB and 1-GB technology using x8 and x16 devices
•Three memory channel organizations are supported for DDR / DDR2
--- Single channel
--- dual channel interleaved
--- dual channel asymmetric
•Supports DDR 333 devices and DDR2 400 /533 devices
--- Supports on-die termination (ODT) for DDR2
•Supports Fast Chip Select mode
•Supports partial write to memory using Data Mask signal (DM)
•Supports high-density memory package for DDR or DDR2 type devices
PCI Express Interface
•One x16 (16 lanes) PCI Express port intended for graphics attach
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•Maximum theoretical realized bandwidth on interface of 4 GB/s in each direction simultaneously, for an
average of 8 GB/s when x16
•Automatic discovery, negotiation and training of link out of reset
•Supports traditional PCI style traffic (asynchronous snooped, PCI ordering)
•Supports traditional AGP style traffic (asynchronous non-snooped, PCI-X relaxed ordering)
•Supports only 1.5-V AGP electricals
•32 deep AGP request queue
•Hierarchical PCI-compliant configuration mechanism for downstream devices
Internal Graphics Controller
•Intel Dual-Frequency Graphics Technology support
•3D Graphics Engine
--- DirectX* 9.0 support
--- OpenGL* 1.5 and 2.0 support
--- Zone rendering 2.0 support
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•Analog CRT DAC Interface Support
--- Supports max DAC frequency up 400 MHz
--- 24-bit RAMDAC support
--- DDC2B compliant
•Analog TV-Out Interface Support
--- Integrated TV-Out device support on display pipes A and B
--- NTSC/PAL encoder standard formats supported
--- 480p/720p/1080i/1080p modes supported
--- Tri-level Sync signal
--- Multiplexed output interface:
- Composite video with S-Video
-S-Video
- Component Video
--- Up to 1024 x 768 resolution supported for NTSC/PAL
--- Macrovision, over scan scaling, and flicker filtering support
•Serial digital video out Port (SDVO) interface Support
--- Two SDVO port are muxed with a subset of the external graphics interface using PCI Express*
Architecture signals
--- Each SDVO port support display pixel rates up to 200MP/s
- The two SDVO ports can be combined into a gang mode to support pixel rates up to 400 MP/s
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--- Supports a variety display devices such as DVI, TV-Out, LVDS, etc.
--- Supports hot plug and display
--- Supports for Macrovision on SDVO TV-Out devices
--- Supports for HDCP SDVO devices
--- External port adds alpha out
•Digital LVDS Interface Support
--- Integrated dual channel LVDS interface supported on display pipe B only
--- Supports 25-MHz to 112-MHz single/dual channel LVDS LCD interface with support for following
format of :
- 1x18 bpp for TFT panels with single channel LVDS
- 2x18 bbp for TFT panels with dual channels LVDS
--- Panel Fitting, Panning, and Center mode supported
--- Spread spectrum clocking (SSC) supported
--- Panel Power Sequencing compliant with SPWG timing specification
--- Integrated PWM interface for LCD backlight inverter control
•Direct Media Interface (DMI)
--- Chip-to-chip interconnect between the GMCH and ICH6-M
--- DMI x2 and DMI x4 configuration supported
--- Bit swapping is supported
--- Lane reversal is not supported
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The ICH6 Provides Extensive I/O Support, Functions and Capabilities Include
•PCI Express Base Specification, Revision 1.0a-compliant
•PCI Local Bus Specification, Revision 2.3-compliant with support for 33 MHz PCI operations(supports up to
seven Req/Gnt pairs).
•ACPI Power Management Logic Support
•Enhanced DMA controller, interrupt controller, and timer functions
•Integrated Serial ATA host controller with independent DMA operation on two ports and AHCI support
•Integrated IDE controller supports Ultra ATA100/66/33
•USB host interface with support for three USB ports; three UHCI host controllers; one EHCI high-speed
USB2.0 Host controller
•Integrated LAN controller
•System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C devices
•Supports Audio Codec ’97, Revision 2.3 Specification (a.k.a.,AC ’97 Component Specification, Revision 2.3)
which provides a link for Audio and Telephony codecs (up to 7 channels)
1.3.4 I/O Controller Hub: Intel ICH6-M
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•Supports Intel High Definition Audio
•Low Pin Count (LPC) interface
•Firmware Hub (FWH) interface support
The PCI4510 Device Supports the Following Features
•PC Card Standard 8.0 compliant
•PCI Bus Power Management Interface Specification 1.1 compliant
•Advanced Configuration and Power Interface Specification 2.0 compliant
•PCI Local Bus Specification Revision 2.2 compliant
•PC 98/99 and PC2001 compliant
•Compliant with the PCI Bus Interface Specification for PCI-to-CardBus Bridges
•Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus and IEEE Std
1394a-2000
•Fully compliant with 1394 Open Host Controller Interface Specification 1.1
1.3.5 CardBus: PCI4510
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•Compatible with both TPS2211A and TPS2221 PC Card power switches
•1.8-V core logic and 3.3-V I/O cells with internal voltage regulator to generate 1.8-V core Vcc
•Universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
•Supports PC Card or CardBus with hot insertion and removal
•Supports 132-MBps burst transfers to maximize data throughput on both the PCI bus and the CardBus
•Supports serialized IRQ with PCI interrupts
•Programmable multifunction terminals
•Serial ROM interface for loading subsystem ID and subsystem vendor ID
•ExCA0compatible registers are mapped in memory or I/O space
•Intel 82365SL-DF register compatible
•Supports ring indicate , SUSPEND# , PCI CCLKRUN# protocol , and PCI bus lock (LOCK#)
•Provides VGA/palette memory and I/O , and subtractive decoding options , LED activity terminals
•Fully interoperable with FireWireTM and i.LINKTM implementations of IEEE Std 1394
•Compliant with Intel Mobile Power Guideline 2000
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•Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed
concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume
•Power-down features to conserve energy in battery-powered applications include: automatic device power
down during suspend, PCI power management for link-layer and inactive ports powered down, ultra low-
power sleep mode
•Two IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and 400M bits/s
•Cable power presence monitoring
•Separate cable bias (TPBIAS) for each port
•Physical write posting of up to three outstanding transactions
•PCI burst transfers and deep FIFO to tolerate large host latency
•External cycle timer control for customized synchronization
•Extended resume signaling for compatibility with legacy DV components
•PHY-Link logic performs system initialization and arbitration functions
•PHY-Link encode and decode functions included for data-strobe bit level encoding
•PHY-Link incoming data resynchronized to local clock
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•Low-cost 24.576MHz crystal provides transmit and receive data at 100M bits/s, 200M bits/s, and 400M
bits/s
•Node power class information signaling for system power management
•Register bits give software control of contender bit, power class bits, link active control bit, and IEEE Std
1394a-2000 features
•Isochronously receive dual-buffer mode
•Out-of-order pipelining for asynchronous transmit requests
•Register access fail interrupt when the PHY SCLK is not active
•PCI power-management D0, D1, D2, and D3 power states
•Initial bandwidth available and initial channels available registers
•PME# support per 1394 Open Host Controller Interface Specification
•Advanced sub micron, low-power CMOS technology
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