NXP Semiconductors PN5331B3HN User manual

1. General description
The PN533 is a highly integrated transceiver module for contactless communication at
13.56 MHz based on the 80C51 microcontroller core. It supports 6 different operating
modes:
•ISO/IEC 14443A/MIFARE Reader/Writer
•FeliCa Reader/Writer
•ISO/IEC 14443B Reader/Writer
•ISO/IEC 14443A/MIFARE Card MIFARE 1 KB or MIFARE 4 KB emulation
•FeliCa Card emulation
•ISO/IEC 18092, ECMA 340 Peer-to-Peer
The PN533 implements a demodulator and decoder for signals from
ISO/IEC 14443A/MIFARE compatible cards and transponders. The PN533 handles the
complete ISO/IEC 14443A framing and error detection (Parity & CRC).
The PN533 supports MIFARE 1 KB or MIFARE 4 KB emulation products. The PN533
supports contactless communication using MIFARE Higher transfer speeds up to
424 kbit/s in both directions.
The PN533 can demodulate and decode FeliCa coded signals. The PN533 handles the
FeliCa framing and error detection. The PN533 supports contactless communication
using FeliCa Higher transfer speeds up to 424 kbit/s in both directions.
The PN533 supports layers 2 and 3 of the ISO/IEC 14443 B Reader/Writer
communication scheme, except anticollision. This must be implemented in firmware as
well as upper layers.
In card emulation mode, the PN533 is able to answer to a Reader/Writer command either
according to the FeliCa or ISO/IEC 14443A/MIFARE card interface scheme. The PN533
generates the load modulation signals, either from its transmitter or from the LOADMOD
pin driving an external active circuit. A complete secure card functionality is only possible
in combination with a secure IC using the NFC-WI/S2C interface.
Compliant to ECMA 340 and ISO/IEC 18092 NFCIP-1 Passive and Active communication
modes, the PN533 offers the possibility to communicate to another NFCIP-1 compliant
device, at transfer speeds up to 424 kbit/s.The PN533 handles the complete NFCIP-1
framing and error detection.
The PN533 transceiver can be connected to an external antenna for Reader/Writer or
Card/PICC modes, without any additional active component.
PN5331B3HN
Near Field Communication (NFC) controller
Rev. 3.4 — 29 November 2017
157534 Product data sheet COMPANY PUBLIC

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The PN533 supports the following host interfaces:
•USB 2.0 full speed interface (bus powered or non bus powered)
•High Speed UART (HSU)
PN533 has also a master I2C interface enabling the drive on an I2C peripheral (i.e.
memory).
In addition, a power switch is included to supply power to a secure IC.

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2. Features and benefits
80C51 microcontroller core with 45056 bytes ROM and 1224 bytes RAM
Highly integrated demodulator and decoder
Buffered output drivers to connect an antenna with minimum number of external
components
Integrated RF level detector
Integrated data mode detector
Supports ISO/IEC 14443A/MIFARE
Supports ISO/IEC 14443B (Reader/Writer mode only)
Typical operating distance in Reader/Writer mode for communication to
ISO/IEC 14443A/MIFARE, ISO/IEC 14443B or FeliCa cards up to 50 mm depending
on antenna size and tuning
Typical operating distance in NFCIP-1 mode up to 50 mm depending on antenna size,
tuning and power supply
Typical operating distance in ISO/IEC 14443A/MIFARE or FeliCa card emulation mode
of approximately 100 mm depending on antenna size, tuning and external field
strength
Supports MIFARE 1 KB or MIFARE 4 KB emulation encryption in Reader/Writer mode
and MIFARE higher transfer speed communication at 212 kbit/s and 424 kbit/s
Supports contactless communication according to the FeliCa protocol at 212 kbit/s and
424 kbit/s
Integrated RF interface for NFCIP-1 up to 424 kbit/s
Possibility to communicate on the RF interface above 424 kbit/s using external analog
components
Supported host interfaces
USB 2.0 full speed interface
High-speed UART
Restricted I2C master interface to control an external I2C EEPROM
Dedicated host interrupts
Low power modes
Hard-Power-down mode
Soft-Power-down mode
Automatic wake-up on HSU interfaces when device is in Power-down mode
Programmable timers
27.12 MHz Crystal oscillator
On-Chip PLL to generate internally The 96 MHz for the USB interface
Power modes
USB bus power mode
2.5 V to 3.6 V power supply operating range in non USB bus power mode
Power switch for external secure companion chip
Dedicated IO ports for external device control
Integrated antenna detector for production tests
ECMA 373 NFC-WI interface to connect an external secure IC

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3. Applications
Computing application
Consumer applications
4. Quick reference data
[1] DVDD, AVDD and TVDD shall always be at the same supply voltage.
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VBUS USB Supply Voltage (USB
mode) 4.02 5 5.25 V
Supply Voltage (non USB mode) VBUS =D
VDDVSS = 0 V 2.5 3.3 3.6 V
TVDD, AVDD, DVDD Supply Voltage TVDD = AVDD = DVDD
VSS =0V [1] 2.5 3.3 3.6 V
PVDD Supply Voltage for host interface VSS =0V 1.6 3.6 V
SVDD Supply Voltage for SAM
interface VSS = 0 V (SVDD Switch Enabled) DVDD -0.1 DVDD V
IVBUS Maximum load current (USB
mode) measured on VBUS 150 mA
Maximum Inrush current
limitation At power up(curlimoff = 0) 100 mA
IHPD Hard Power Down Current (Not
powered from USB) AVDD = DVDD = TVDD = PVDD
= 3 V, RF level detector off 10 A
ISPD Soft Power down Current(Not
powered from USB) AVDD = DVDD = TVDD = PVDD = 3 V, RF level detector on 30 A
Isuspend USB suspend Current AVDD = DVDD = TVDD = PVDD
= 3 V, RF level detector on
(without resistor on DP/DM)
250 A
IDVDD Digital Supply Current AVDD = DVDD = TVDD = PVDD
= 3 V, RF level detector on,
SVDD switch off
[1] 15 mA
ISVDD SVDD Supply Current SVDD = 3 V, SVDD switch On 30 mA
IAVDD Analog Supply Current AVDD = DVDD = TVDD = PVDD
= 3 V, RF level detector on 6mA
ITVDD Transmitter Supply Current During RF Transmission,
TVDD=3V 60 100 mA
Ptot continuous total power
dissipation. Tamb =-30to+85C0.55W
Tamb operating ambient temperature -30 +85 C

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5. Ordering information
[1] Refer to Section 17.4 “Licenses”
6. Block diagram
Table 2. Ordering information
Type number Package
Name Description Version
PN5331B3HN/C270[1] HVQFN40 Heatsink Very thin Quad Flat package; 40 pins, plastic,
body 6 x 6 x 0.85 mm; leadless; MSL level 2. SOT618-1
Fig 1. Block diagram of PN533
USB PLL
VBUS
REGULATOR
POR
DVDD
USB
ROMif
Xramif
Hostif
I2c
Timer0/1
Timer2
Intc
SFRif
RAM
ROM
PCR
80C51
TCB
Ports
MATX
RAM
FIFO
Manager
Osc27
RSTPD_N
RF Demod Antenna
ADC
DriverDetector
FiFO
TIMER
MIFARE Classic Unit
Framing Gen. & Check
Signal Processing
Clock
Recovery
CL UART
Transmit
Control
TVDD
AVDD
PVDD
PN533
Clock
Generator
Sensor
VMID BG
UART
SVDD
SIGINSIGOUTP34
SVDDswitch
sam_switch_en
sam_switch_overload
HSU
I²2C
IOs
SWITCH
SDA/SCL

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7. Pinning information
7.1 Pinning
Fig 2. Pin configuration for HVQFN 40 (SOT618-1)

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7.2 Pin description
Table 3. PN533 Pin description
Symbol Pin Type Pad Ref
Voltage Description
DVSS 1 PWR Digital ground
LOADMOD 2 O DVDD Load Modulation output provides digital signal for FeliCa and MIFARE card
operating mode
TVSS1 3 PWR Transmitter ground: supplies the output stage of TX1 and TX2
TX1 4 O TVDD Transmitter 1: transmits modulated 13.56 MHz energy carrier
TVDD 5 PWR Transmitter power supply: supplies the output stage of TX1 and TX2
TX2 6 O TVDD Transmitter2: delivers the modulated 13.56 MHz energy carrier
TVSS2 7 PWR Transmitter ground: supplies the output stage of TX1 and TX2
AVDD 8 PWR Analog power supply
VMID 9 PWR AVDD Internal reference voltage: This pin delivers the internal reference voltage.
RX 10 I AVDD Receiver Input: Input pin for the reception signal, which is the load modulated
13.56 MHZ energy carrier from the antenna circuit
AVSS 11 PWR Analog ground
AUX1 12 O DVDD Auxiliary output 1: This pin delivers analog and digital test signals
AUX2 13 O DVDD Auxiliary output 2: This pin delivers analog and digital test signals
DVSS 14 PWR Digital Ground
OSCIN 15 I AVDD Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This
pin is also the input for an externally generated clock (fosc = 27.12 MHZ).
OSCOUT 16 O AVDD Crystal Oscillator output: Output of the inverting amplifier of the oscillator.
I0 17 I DVDD Interface mode lines: selects the used host interface (refer to Table 75
“Config I0_I1 register (address 6103h) bit allocation”for details).
In test mode I0 is used as test signals.
I1 18 I DVDD
TESTEN 19 I DVDD Test enable pin:
When set to 1 enable the test mode.
When set to 0 reset the TCB and disable the access to the test mode.
P35 20 IO DVDD General purpose IO signal
P70_IRQ 21 IO PVDD Interrupt request: Output to signal an interrupt event to the host (Port 7 bit 0)
RSTOUT 22 O PVDD Output reset signal. When Low it indicates that the circuit is in reset state.
DVSS 23 PWR Digital Ground
DM 24 IO PVDD USB D- data line in USB mode or TX in HSU mode (refer to Table 74 “HOST
interface selection” on page 47for details).
In test mode this signal is used as input and output test signal
DP 25 IO PVDD USB D+ data line in USB mode or RX in HSU mode (refer to Table 74 “HOST
interface selection” on page 47 for details).
In test mode this signal is used as input and output test signal.
PVDD 26 PWR IO pad power supply
DELATT 27 O PVDD Optional output for an external 1.5 KOhms resistor connection on D+.
P30 28 IO PVDD General purpose IO signal. Can be configured to act either as RX line of the
second serial interface UART or general purpose IO.
In test mode this signal is used as input and output test signal.

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P31 29 IO PVDD General purpose IO signal. Can be configured to act either as TX line of the
second serial interface UART or general purpose IO.
In test mode this signal is used as input and output test signal.
P32_INT0 30 IO PVDD General purpose IO signal. Can also be used as an interrupt source
In test mode this signal is used as input and output test signal.
P33_INT1 31 IO PVDD General purpose IO signal. Can be used to generate an HZ state on the
output of the selected interface for the Host communication and to enter into
power down mode without resetting the internal state of PN533.
In test mode this signal is used as input and output test signal.
SCL 32 IO DVDD I2C clock line - open drain in output mode
SDA 33 IO DVDD I2C data line - open drain in output mode
P34 34 IO SVDD General purpose IO signal or clk signal for the SAM
SIGOUT 35 O SVDD Contactless communication interface output: delivers a serial data stream
according to NFCIP-1 and output signal for the SAM.
In test mode this signal is used as test signal output.
SIGIN 36 I SVDD Contactless communication interface input: accepts a digital, serial data
stream according to NFCIP-1 and input signal from the SAM.
In test mode this signal is used as test signal input.
SVDD 37 PWR Output power for SAM power supply. Switched on by Firmware with an
overload detection. Used as a reference voltage for SAM communication.
RSTPD_N 38 I PVDD Reset and Power Down: When LOW, internal current sources are switched
off, the oscillator is inhibited, and the input pads are disconnected from the
outside world.
With a negative edge on this pin the internal reset phase starts.
DVDD 39 PWR Digital Power Supply
VBUS 40 PWR USB power supply.
Table 3. PN533 Pin description …continued
Symbol Pin Type Pad Ref
Voltage Description

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8. Functional description
8.1 80C51
The PN533 is controlled via an embedded 80C51 microcontroller core (for more details
http://www.standardics.nxp.com/support/documents/microcontrollers/?scope=80C51). Its
principle features are listed below:
•6-clock cycle CPU. One machine cycle comprises 6 clock cycles or states (S1 to S6).
An instruction needs at least one machine cycle.
•ROM interface
•RAM interface to embedded IDATA and XRAM memories (see Figure 4 on page 10)
•Peripheral interface (PIF)
•Power control module to manage the CPU power consumption
•Clock module to control CPU clock during Shutdown and Wake-up modes
•Port module interface to configure I/O pads
•Interrupt controller
•Three timers
•Debug UART
The block diagram describes the main blocks described in this 80C51 section.
Fig 3. PN533 80C51 block description
PN533

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8.1.1 PN533 memory map
The memory map of PN533 is composed of 2 main memory spaces: data memory and
program memory. The following figure illustrates the structure.
Fig 4. PN533 memory map overview
Special Function
Registers
DIRECT
FFH
SFR
128 BYTES RAM
INDIRECT
ADDRESSING
128 BYTES RAM
DIRECT
ADDRESSING
00H
7FH
RAM
5FFFH
0000H
FFFFH XRAM
7FFFH
ADDRESSING ONLY
&
INDIRECT
A000H
Data Memory Area Program Memory Area
IDATA
ROM
ROM
PERIPHERAL
AREA
PIF
976 BYTES
XRAM
RESERVED
45056 BYTES
RESERVED
RESERVED
FFFFH
0000H
03CFH
6000H
8000H
BFFFH

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8.1.2 Data memory
Data memory is itself divided into 2 spaces:
•384-byte IDATA with byte-wide addressing
–258-byte RAM
–128-byte SFR
•1 bank of 64 KB extended RAM (XRAM) with 2-byte-wide addressing
8.1.2.1 IDATA memory
The IDATA memory is mapped into 3 blocks, which are referred as Lower IDATA RAM,
Upper IDATA RAM, and SFR. Addresses to these blocks are byte-wide, which implies an
address space of only 256 bytes. However, 384 bytes can be addressed within IDATA
memory through the use of direct and indirect address mechanisms.
•Direct addressing: the operand is specified by an 8-bit address field in the instruction.
•Indirect addressing: the instruction specifies a register where the address of the
operand is stored.
For the range 80h to FFh, direct addressing will access the SFR space; indirect
addressing accesses Upper IDATA RAM. For the range 00h to 7Fh, Lower IDATA RAM is
accessed, regardless of addressing mode. This behavior is summarized in the table
below:
The SFRs and their addresses are described in the Table 5:
Table 4. IDATA memory addressing
Address Addressing mode
Direct Indirect
00h to 7Fh Lower IDATA RAM Lower IDATA RAM
80h to FFh SFRs Upper IDATA RAM

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Table 5. SFR map of NFC controller
Address Bit-
addressable Byte-addressable Address
F8h IP1 XRAMP P3CFGA P3CFGB FFh
F0h B P7CFGA P7CFGB P7 F7h
E8h IE1 CIU_Status2 CIU_FIFOData CIU_FIFOLevel CIU_WaterLevel CIU_Control CIU_BitFraming CIU_Coll EFh
E0h ACC E7h
D8h I2CC0N I2CSTA I2CDAT I2CADR CIU_Status1 DFh
D0h PSW CIU_Command CIU_CommIEn CIU_DivIEn CIU_CommIrq CIU_DivIrq CIU_Error D7h
C8h T2CON T2MOD RCAP2L RCAP2H T2L T2H CFh
C0h C7h
B8h IP0 BFh
B0h P3 B7h
A8h IE0 HSU_STA HSU_CTR HSU_PRE HSU_CNT AFh
A0h FITEN FDATA FSIZE A7h
98h S0CON SBUF RWL TWL FIFOFS FIFOFF SFF FIT 9Fh
90h 97h
88h T01CON T01MOD T0L T1L T0H T1H 8Fh
80h SP DPL DPH PCON 87h

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8.1.2.2 XRAM memory
The XRAM memory is divided into 2 memory spaces:
•0000h to 5FFFh: reserved for addressing embedded RAM. For the PN533, only
accesses between 0000h and 03C7h are valid.
•6000h to 7FFFh: reserved for addressing embedded peripherals. This space is
divided into 32 regions of 256 bytes each. Addressing can be performed using R0 or
R1 and the XRAMP SFR.
The Table 6 depicts the mapping of internal peripherals into XRAM.
XRAM is accessed via the dedicated MOVX instructions. There are two access modes:
•16-bit data pointer (DPTR): the full XRAM address space can be accessed.
•paging mechanism: the upper address byte is stored in the SFR register XRAMP; the
lower byte is stored in either R1 or R0.
The Figure 5 illustrates both mechanisms.
Table 6. Peripheral mapping into XRAM memory space
Base
Address End Address Description
6000h 60FFh Reserved.
6100h 61FFh IOs and miscellaneous registers configuration
Refer to Section 8.2 “General purpose IOs configurations” on page 37
6200h 62FFh Power Clock and Reset controller
Refer to Section 8.5.10 “PCR extension registers” on page 102
6300h 633Fh Contactless Unit Interface
Refer to Section 8.6 “Contactless Interface Unit (CIU)” on page 108
6340h FFFFh Reserved

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8.1.3 Program memory
PN533 program memory ranges from 0000h to AFFFh, which is physically mapped to the
44 KB ROM.
Fig 5. Indirect addressing of XRAM memory space
XRAM
XRAMP = 80h
XRAMP = 81h
XRAMP = 82h
XRAMP = FFh
6000H
7FFFH
0000H
5FFFH
8000H
FFFFH
XRAM
PERIPHERAL
AREA
40 kB
Reserved
XRAMP = 00h
XRAMP = 01h
00h
XRAMP = 02h
XRAMP = 3Fh
XRAMP = 3Eh
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
XRAMP = 40h Peripheral 1
XRAMP = 41h Peripheral 2
00h
XRAMP = 42h Peripheral 3
XRAMP = 5Fh Peripheral 32
XRAMP = 5Eh Peripheral 31
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
XRAMP = 60h
XRAMP = 61h
00h
XRAMP = 62h
XRAMP = 7Fh
XRAMP = 7Eh
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
XRAMP = FFh
MOVX @DPTR,A MOVX A,@DPTR
MOVX @Ri,A
MOVX A,@Ri

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8.1.4 PCON module
The Power Control (PCON) module is configured using the PCON SFR register.
8.1.5 Interrupt Controller
The interrupt controller has the following features:
•1interrupt source
•Interrupt enable registers IE0 and IE1
•Interrupt priority registers IP0 and IP1
•Wake-up from Power-down state
8.1.5.1 Interrupt vectors
The mapping between interrupt sources and interrupt vectors is shown in Table 9.
Table 7. PCON register (SFR: address 87h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol SMOD - CPU_PD -
Reset 000000 0 0
Access R/WRRRRRR/WR/W
Table 8. Description of PCON bits
Bit Symbol Description
7SMODSerial MODe:
When set to logic level 1, the baud rate of the Debug UART is doubled
6 to 2 - Reserved.
1CPU_PDPower-down:
When set to logic level 1, the microcontroller goes in Power-down mode
0 Reserved This bit should only ever contain logic level 0.
Table 9. Interrupt vector
Interrupt
number Interrupt vector Interrupt sources Incremental priority level (conflict resolution level)
0 0003h External P32_INT0 Highest
1 000Bh Timer0 interrupt
2 0013h External P33_INT1
3 001Bh Timer1 interrupt
4 0023h Debug UART interrupt
5 002Bh Timer2 interrupt
6 0033h NFC-WI interrupt
7003BhReserved
8 0043h Reserved
9 004Bh CIU interrupt 1
10 0053h CIU interrupt 0
11 005Bh I2C interrupt
12 0063h FIFO or HSU interrupts
13 006Bh USB interrupt
14 0073h General Purpose IRQ Lowest

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8.1.5.2 Interrupt enable: IE0 and IE1 registers
Each interrupt source can be individually enabled or disabled by setting a bit in IE0 or IE1.
In register IE0, a global interrupt enable bit can be set to logic level 0 to disable all
interrupts at once.
The 2 following tables describe IE0.
Table 10. Interrupt controller IE0 register (SFR: address A8h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol IE0_7 IE0_6 IE0_5 IE0_4 IE0_3 IE0_2 IE0_1 IE0_0
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 11. Description of IE0 bits
Bit Symbol Description
7 IE0_7 Global interrupt enable
When set to logic 1, the interrupts can be enabled.
When set to logic 0, all the interrupts are disabled.
6 IE0_6 NFC-WI counter interrupt enable
When set to logic 1, NFC-WI interrupt is enabled.
5 IE0_5 Timer2 interrupt enable
When set to logic 1, Timer2 interrupt is enabled.
4 IE0_4 Debug UART interrupt enable
When set to logic 1, Debug UART interrupt is enabled.
3 IE0_3 Timer1 interrupt enable
When set to logic 1, Timer1 interrupt is enabled
2 IE0_2 P33_INT1 interrupt enable
When set to logic 1, P33_INT1 pin interrupt is enabled.
The polarity of P33_INT1 can be inverted (see Table 75 on page 47).
1 IE0_1 Timer0 interrupt enable
When set to logic 1, Timer0 interrupt is enabled.
0 IE0_0 P32_INT0 interrupt enable
When set to logic 1, P32_INT0 pin interrupt is enabled.

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The 2 following tables describe IE1.
8.1.5.3 Interrupt prioritization: IP0 and IP1 registers
Each interrupt source can be individually programmed to be one of two priority levels by
setting or clearing a bit in the interrupt priority registers IP0 and IP1. If two interrupt
requests of different priority levels are received simultaneously, the request with the high
priority is serviced first. On the other hand, if the interrupts are of the same priority,
precedence is resolved by comparing their respective conflict resolution levels (see
Table 9 on page 15
for details). The processing of a low priority interrupt can be interrupted by one with a high
priority.
A RETI (Return From Interrupt) instruction jumps to the address immediately succeeding
the point at which the interrupt was serviced. The instruction found at the return address
will be executed, prior to servicing any pending interrupts.
Table 12. Interrupt controller IE1 register (SFR: address E8h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol IE1_7 IE1_6 IE1_5 IE1_4 IE1_3 IE1_2 - -
Reset 0 0 000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 13. Description of IE1 bits
Bit Symbol Description
7 IE1_7 General purpose IRQ interrupt enable.
When set to logic 1, enables interrupt function of P34, P35, P50_SCL and P71
according to their respective enable and level control bits. See Table 19 on
page 19, Table 138 on page 104 and Table 144 on page 107.
6 IE1_6 USB interrupt enable.
When set to logic level 1, enables USB interrupt.
5 IE1_5 FIFO and HSU interrupt enable.
When set to logic 1, enables FIFO interrupts, SPI interrupts, HSU interrupt.
4 IE1_4 I2C interrupt enable.
When set to logic 1, enables I2C interrupt.
3 IE1_3 CIU interrupt 0 enable.
When set to logic 1, enables CIU interrupt 0: CIU_IRQ_0.
2 IE1_2 CIU interrupt 1 enable.
When set to logic 1, enables the CIU interrupt 1: CIU_IRQ_1.
1 to 0 - Reserved. This bit must be set to logic level 0.

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The 2 following tables describe IP0.
The 2 following tables describe IP1.
Table 14. Interrupt controller IP0 register (SFR: address B8h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol IP0_7 IP0_6 IP0_5 IP0_4 IP0_3 IP0_2 IP0_1 IP0_0
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 15. Description of IP0 bits
Bit Symbol Description
7 IP0_7 Reserved
6 IP0_6 When set to logic level 1, NFC-WI interrupt is set to high priority.
5 IP0_5 When set to logic level 1, Timer2 interrupt is set to high priority.
4 IP0_4 When set to logic level 1, Debug UART interrupt is set to high priority.
3 IP0_3 When set to logic level 1, Timer1 interrupt is set to high priority.
2 IP0_2 When set to logic level 1, external P33_INT1 pin is set to high priority.
1 IP0_1 When set to logic level 1, Timer0 interrupt is set to high priority.
0 IP0_0 When set to logic level 1, external P32_INT0 pin is set to high priority.
Table 16. Interrupt controller IP1 register (SFR: address F8h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol IP1_7 IP1_6 IP1_5 IP1_4 IP1_3 IP1_2 -
Reset 000000 00
Access R/W R/W R/W R/W R/W R/W R/W
Table 17. Description of IP1 bits
Bit Symbol Description
7 IP1_7 When set to logic level 1, General Purpose IRQ interrupt is set to high
priority.
6 IP1_6 When set to logic level 1, USB interrupt is set to high priority.
5 IP1_5 When set to logic level 1, combined FIFO and HSU interrupt is set to
high priority.
4 IP1_4 When set to logic level 1, I2C interrupt is set to high priority.
3 IP1_3 When set to logic level 1, CIU interrupt 0 is set to high priority.
2 IP1_2 When set to logic level 1, CIU interrupt 1 is set to high priority.
1- Reserved. This bit must be set to logic level 0.
0 IP1_0 When set to logic level 1, interrupt number 7 is set to high priority.

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8.1.5.4 General purpose IRQ control
The general purpose interrupts are controlled by register GPIRQ.
NOTE: this is not a standard feature of the 8051.
Table 18. GPIRQ register (address 6107h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol gpirq_
level_
P71
gpirq_
level_
DP
gpirq_
level_
P35
gpirq_
level_
P34
gpirq_
enable
_P71
gpirq_
enable_
DP
gpirq_
enable_
P35
gpirq_
enable_
P34
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 19. Description of GPIRQ bits
Bit Symbol Description
7-
6 gpirq_level_DP Configures the polarity of signal on P50 to generate a GPIRQ
interrupt event (assuming gpirq_enable_P50 is set).
When set to logic 0, an interrupt will be generated if P50_SCL is at logic 0.
When set to logic 1, an interrupt will be generated if P50_SCL is at logic 1.
5 gpirq_level_P35 Configures the polarity of signal on P35 to generate a GPIRQ
interrupt event (assuming gpirq_enable_P35 is set).
When set to logic 0, an interrupt will be generated if P35 is at logic 0.
When set to logic 1, an interrupt will be generated if P35 is at logic 1.
4 gpirq_level_P34 Configures the polarity of signal on P34 to generate a GPIRQ
interrupt event (assuming gpirq_enable_P34 is set).
When set to logic 0, an interrupt will be generated if P34 is at logic 0.
When set to logic 1, an interrupt will be generated if P34 is at logic 1.
Remark: If hide_svdd_sig of the register control_rngpower is set and
gpirq_enable_P34 is also set then this bit will be asserted independently
of the level on the pad P34.
3-
2 gpirq_enable_DP When set to logic 1, enables pad DP to generate a GPIRQ interrupt event.
1 gpirq_enable_P35 When set to logic 1, enables pad P35 to generate a GPIRQ interrupt
event.
0 gpirq_enable_P34 When set to logic 1, enables pad P34 to generate a GPIRQ interrupt
event.

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8.1.6 Timer0/1 description
Timer0/1 are general purpose timer/counters. Timer0/1 has the following functionality:
•Configurable edge or level detection interrupts
•Timer or counter operation
•4 timer/counter modes
•Baud rate generation for Debug UART
Timer0/1 comprises two 16-bit timer/counters: Timer0 and Timer1. Both can be configured
as either a timer or an event counter.
Each of the timers can operate in one of four modes:
•Mode 0: 13-bit timer/counter
•Mode 1: 16-bit timer/counter
•Mode 2: 8-bit timer/counter with programmable preload value
•Mode 3: two individual 8-bit timer/counters (Timer0 only)
In the ‘timer’ function, the timer/counter is incremented every machine cycle. The count
rate is 1/6 of the CPU clock frequency (CPU_CLK).
In the ‘counter’ function, the timer/counter is incrementedin response to a 1-to-0 transition
on the input pins P34 / SIC_CLK (Timer0) or P35 (Timer1). In this mode, the external input
is sampled during state S5 of every machine cycle. If the associated pin is at logic level 1
for a machine cycle, followed by logic level 0 on the next machine cycle, the count is
incremented. The new count value appears in the timer/counter in state S3 of the machine
cycle following the one in which the transition was detected. The maximum count rate is
1/12 of the CPU_CLK frequency. There are no restrictions on the duty cycle of the
external input signal but to ensure that a given level is sampled at least once before it
changes, it should be held for at least one full machine cycle.
The overflow output ‘t1_ovf’ of Timer1 can be used as a baud rate generator for the
Debug UART. The Timer1 interrupt should be disabled in this case. For most applications
which drive the Debug UART, Timer1 is configured for ‘timer’ operation and in auto-reload
mode.