NXP Semiconductors PN5331B3HN User manual

1. General description
The PN533 is a highly integrated transceiver module for contactless communication at
13.56 MHz based on the 80C51 microcontroller core. It supports 6 different operating
modes:
•ISO/IEC 14443A/MIFARE Reader/Writer
•FeliCa Reader/Writer
•ISO/IEC 14443B Reader/Writer
•ISO/IEC 14443A/MIFARE Card MIFARE 1 KB or MIFARE 4 KB emulation
•FeliCa Card emulation
•ISO/IEC 18092, ECMA 340 Peer-to-Peer
The PN533 implements a demodulator and decoder for signals from
ISO/IEC 14443A/MIFARE compatible cards and transponders. The PN533 handles the
complete ISO/IEC 14443A framing and error detection (Parity & CRC).
The PN533 supports MIFARE 1 KB or MIFARE 4 KB emulation products. The PN533
supports contactless communication using MIFARE Higher transfer speeds up to
424 kbit/s in both directions.
The PN533 can demodulate and decode FeliCa coded signals. The PN533 handles the
FeliCa framing and error detection. The PN533 supports contactless communication
using FeliCa Higher transfer speeds up to 424 kbit/s in both directions.
The PN533 supports layers 2 and 3 of the ISO/IEC 14443 B Reader/Writer
communication scheme, except anticollision. This must be implemented in firmware as
well as upper layers.
In card emulation mode, the PN533 is able to answer to a Reader/Writer command either
according to the FeliCa or ISO/IEC 14443A/MIFARE card interface scheme. The PN533
generates the load modulation signals, either from its transmitter or from the LOADMOD
pin driving an external active circuit. A complete secure card functionality is only possible
in combination with a secure IC using the NFC-WI/S2C interface.
Compliant to ECMA 340 and ISO/IEC 18092 NFCIP-1 Passive and Active communication
modes, the PN533 offers the possibility to communicate to another NFCIP-1 compliant
device, at transfer speeds up to 424 kbit/s.The PN533 handles the complete NFCIP-1
framing and error detection.
The PN533 transceiver can be connected to an external antenna for Reader/Writer or
Card/PICC modes, without any additional active component.
PN5331B3HN
Near Field Communication (NFC) controller
Rev. 3.4 — 29 November 2017
157534 Product data sheet COMPANY PUBLIC

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Product data sheet
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NXP Semiconductors PN5331B3HN
Near Field Communication (NFC) controller
The PN533 supports the following host interfaces:
•USB 2.0 full speed interface (bus powered or non bus powered)
•High Speed UART (HSU)
PN533 has also a master I2C interface enabling the drive on an I2C peripheral (i.e.
memory).
In addition, a power switch is included to supply power to a secure IC.

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Product data sheet
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NXP Semiconductors PN5331B3HN
Near Field Communication (NFC) controller
2. Features and benefits
80C51 microcontroller core with 45056 bytes ROM and 1224 bytes RAM
Highly integrated demodulator and decoder
Buffered output drivers to connect an antenna with minimum number of external
components
Integrated RF level detector
Integrated data mode detector
Supports ISO/IEC 14443A/MIFARE
Supports ISO/IEC 14443B (Reader/Writer mode only)
Typical operating distance in Reader/Writer mode for communication to
ISO/IEC 14443A/MIFARE, ISO/IEC 14443B or FeliCa cards up to 50 mm depending
on antenna size and tuning
Typical operating distance in NFCIP-1 mode up to 50 mm depending on antenna size,
tuning and power supply
Typical operating distance in ISO/IEC 14443A/MIFARE or FeliCa card emulation mode
of approximately 100 mm depending on antenna size, tuning and external field
strength
Supports MIFARE 1 KB or MIFARE 4 KB emulation encryption in Reader/Writer mode
and MIFARE higher transfer speed communication at 212 kbit/s and 424 kbit/s
Supports contactless communication according to the FeliCa protocol at 212 kbit/s and
424 kbit/s
Integrated RF interface for NFCIP-1 up to 424 kbit/s
Possibility to communicate on the RF interface above 424 kbit/s using external analog
components
Supported host interfaces
USB 2.0 full speed interface
High-speed UART
Restricted I2C master interface to control an external I2C EEPROM
Dedicated host interrupts
Low power modes
Hard-Power-down mode
Soft-Power-down mode
Automatic wake-up on HSU interfaces when device is in Power-down mode
Programmable timers
27.12 MHz Crystal oscillator
On-Chip PLL to generate internally The 96 MHz for the USB interface
Power modes
USB bus power mode
2.5 V to 3.6 V power supply operating range in non USB bus power mode
Power switch for external secure companion chip
Dedicated IO ports for external device control
Integrated antenna detector for production tests
ECMA 373 NFC-WI interface to connect an external secure IC

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Product data sheet
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NXP Semiconductors PN5331B3HN
Near Field Communication (NFC) controller
3. Applications
Computing application
Consumer applications
4. Quick reference data
[1] DVDD, AVDD and TVDD shall always be at the same supply voltage.
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VBUS USB Supply Voltage (USB
mode) 4.02 5 5.25 V
Supply Voltage (non USB mode) VBUS =D
VDDVSS = 0 V 2.5 3.3 3.6 V
TVDD, AVDD, DVDD Supply Voltage TVDD = AVDD = DVDD
VSS =0V [1] 2.5 3.3 3.6 V
PVDD Supply Voltage for host interface VSS =0V 1.6 3.6 V
SVDD Supply Voltage for SAM
interface VSS = 0 V (SVDD Switch Enabled) DVDD -0.1 DVDD V
IVBUS Maximum load current (USB
mode) measured on VBUS 150 mA
Maximum Inrush current
limitation At power up(curlimoff = 0) 100 mA
IHPD Hard Power Down Current (Not
powered from USB) AVDD = DVDD = TVDD = PVDD
= 3 V, RF level detector off 10 A
ISPD Soft Power down Current(Not
powered from USB) AVDD = DVDD = TVDD = PVDD = 3 V, RF level detector on 30 A
Isuspend USB suspend Current AVDD = DVDD = TVDD = PVDD
= 3 V, RF level detector on
(without resistor on DP/DM)
250 A
IDVDD Digital Supply Current AVDD = DVDD = TVDD = PVDD
= 3 V, RF level detector on,
SVDD switch off
[1] 15 mA
ISVDD SVDD Supply Current SVDD = 3 V, SVDD switch On 30 mA
IAVDD Analog Supply Current AVDD = DVDD = TVDD = PVDD
= 3 V, RF level detector on 6mA
ITVDD Transmitter Supply Current During RF Transmission,
TVDD=3V 60 100 mA
Ptot continuous total power
dissipation. Tamb =-30to+85C0.55W
Tamb operating ambient temperature -30 +85 C

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Product data sheet
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NXP Semiconductors PN5331B3HN
Near Field Communication (NFC) controller
5. Ordering information
[1] Refer to Section 17.4 “Licenses”
6. Block diagram
Table 2. Ordering information
Type number Package
Name Description Version
PN5331B3HN/C270[1] HVQFN40 Heatsink Very thin Quad Flat package; 40 pins, plastic,
body 6 x 6 x 0.85 mm; leadless; MSL level 2. SOT618-1
Fig 1. Block diagram of PN533
USB PLL
VBUS
REGULATOR
POR
DVDD
USB
ROMif
Xramif
Hostif
I2c
Timer0/1
Timer2
Intc
SFRif
RAM
ROM
PCR
80C51
TCB
Ports
MATX
RAM
FIFO
Manager
Osc27
RSTPD_N
RF Demod Antenna
ADC
DriverDetector
FiFO
TIMER
MIFARE Classic Unit
Framing Gen. & Check
Signal Processing
Clock
Recovery
CL UART
Transmit
Control
TVDD
AVDD
PVDD
PN533
Clock
Generator
Sensor
VMID BG
UART
SVDD
SIGINSIGOUTP34
SVDDswitch
sam_switch_en
sam_switch_overload
HSU
I²2C
IOs
SWITCH
SDA/SCL

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Product data sheet
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NXP Semiconductors PN5331B3HN
Near Field Communication (NFC) controller
7. Pinning information
7.1 Pinning
Fig 2. Pin configuration for HVQFN 40 (SOT618-1)

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Product data sheet
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NXP Semiconductors PN5331B3HN
Near Field Communication (NFC) controller
7.2 Pin description
Table 3. PN533 Pin description
Symbol Pin Type Pad Ref
Voltage Description
DVSS 1 PWR Digital ground
LOADMOD 2 O DVDD Load Modulation output provides digital signal for FeliCa and MIFARE card
operating mode
TVSS1 3 PWR Transmitter ground: supplies the output stage of TX1 and TX2
TX1 4 O TVDD Transmitter 1: transmits modulated 13.56 MHz energy carrier
TVDD 5 PWR Transmitter power supply: supplies the output stage of TX1 and TX2
TX2 6 O TVDD Transmitter2: delivers the modulated 13.56 MHz energy carrier
TVSS2 7 PWR Transmitter ground: supplies the output stage of TX1 and TX2
AVDD 8 PWR Analog power supply
VMID 9 PWR AVDD Internal reference voltage: This pin delivers the internal reference voltage.
RX 10 I AVDD Receiver Input: Input pin for the reception signal, which is the load modulated
13.56 MHZ energy carrier from the antenna circuit
AVSS 11 PWR Analog ground
AUX1 12 O DVDD Auxiliary output 1: This pin delivers analog and digital test signals
AUX2 13 O DVDD Auxiliary output 2: This pin delivers analog and digital test signals
DVSS 14 PWR Digital Ground
OSCIN 15 I AVDD Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This
pin is also the input for an externally generated clock (fosc = 27.12 MHZ).
OSCOUT 16 O AVDD Crystal Oscillator output: Output of the inverting amplifier of the oscillator.
I0 17 I DVDD Interface mode lines: selects the used host interface (refer to Table 75
“Config I0_I1 register (address 6103h) bit allocation”for details).
In test mode I0 is used as test signals.
I1 18 I DVDD
TESTEN 19 I DVDD Test enable pin:
When set to 1 enable the test mode.
When set to 0 reset the TCB and disable the access to the test mode.
P35 20 IO DVDD General purpose IO signal
P70_IRQ 21 IO PVDD Interrupt request: Output to signal an interrupt event to the host (Port 7 bit 0)
RSTOUT 22 O PVDD Output reset signal. When Low it indicates that the circuit is in reset state.
DVSS 23 PWR Digital Ground
DM 24 IO PVDD USB D- data line in USB mode or TX in HSU mode (refer to Table 74 “HOST
interface selection” on page 47for details).
In test mode this signal is used as input and output test signal
DP 25 IO PVDD USB D+ data line in USB mode or RX in HSU mode (refer to Table 74 “HOST
interface selection” on page 47 for details).
In test mode this signal is used as input and output test signal.
PVDD 26 PWR IO pad power supply
DELATT 27 O PVDD Optional output for an external 1.5 KOhms resistor connection on D+.
P30 28 IO PVDD General purpose IO signal. Can be configured to act either as RX line of the
second serial interface UART or general purpose IO.
In test mode this signal is used as input and output test signal.

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NXP Semiconductors PN5331B3HN
Near Field Communication (NFC) controller
P31 29 IO PVDD General purpose IO signal. Can be configured to act either as TX line of the
second serial interface UART or general purpose IO.
In test mode this signal is used as input and output test signal.
P32_INT0 30 IO PVDD General purpose IO signal. Can also be used as an interrupt source
In test mode this signal is used as input and output test signal.
P33_INT1 31 IO PVDD General purpose IO signal. Can be used to generate an HZ state on the
output of the selected interface for the Host communication and to enter into
power down mode without resetting the internal state of PN533.
In test mode this signal is used as input and output test signal.
SCL 32 IO DVDD I2C clock line - open drain in output mode
SDA 33 IO DVDD I2C data line - open drain in output mode
P34 34 IO SVDD General purpose IO signal or clk signal for the SAM
SIGOUT 35 O SVDD Contactless communication interface output: delivers a serial data stream
according to NFCIP-1 and output signal for the SAM.
In test mode this signal is used as test signal output.
SIGIN 36 I SVDD Contactless communication interface input: accepts a digital, serial data
stream according to NFCIP-1 and input signal from the SAM.
In test mode this signal is used as test signal input.
SVDD 37 PWR Output power for SAM power supply. Switched on by Firmware with an
overload detection. Used as a reference voltage for SAM communication.
RSTPD_N 38 I PVDD Reset and Power Down: When LOW, internal current sources are switched
off, the oscillator is inhibited, and the input pads are disconnected from the
outside world.
With a negative edge on this pin the internal reset phase starts.
DVDD 39 PWR Digital Power Supply
VBUS 40 PWR USB power supply.
Table 3. PN533 Pin description …continued
Symbol Pin Type Pad Ref
Voltage Description

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Product data sheet
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NXP Semiconductors PN5331B3HN
Near Field Communication (NFC) controller
8. Functional description
8.1 80C51
The PN533 is controlled via an embedded 80C51 microcontroller core (for more details
http://www.standardics.nxp.com/support/documents/microcontrollers/?scope=80C51). Its
principle features are listed below:
•6-clock cycle CPU. One machine cycle comprises 6 clock cycles or states (S1 to S6).
An instruction needs at least one machine cycle.
•ROM interface
•RAM interface to embedded IDATA and XRAM memories (see Figure 4 on page 10)
•Peripheral interface (PIF)
•Power control module to manage the CPU power consumption
•Clock module to control CPU clock during Shutdown and Wake-up modes
•Port module interface to configure I/O pads
•Interrupt controller
•Three timers
•Debug UART
The block diagram describes the main blocks described in this 80C51 section.
Fig 3. PN533 80C51 block description
PN533

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NXP Semiconductors PN5331B3HN
Near Field Communication (NFC) controller
8.1.1 PN533 memory map
The memory map of PN533 is composed of 2 main memory spaces: data memory and
program memory. The following figure illustrates the structure.
Fig 4. PN533 memory map overview
Special Function
Registers
DIRECT
FFH
SFR
128 BYTES RAM
INDIRECT
ADDRESSING
128 BYTES RAM
DIRECT
ADDRESSING
00H
7FH
RAM
5FFFH
0000H
FFFFH XRAM
7FFFH
ADDRESSING ONLY
&
INDIRECT
A000H
Data Memory Area Program Memory Area
IDATA
ROM
ROM
PERIPHERAL
AREA
PIF
976 BYTES
XRAM
RESERVED
45056 BYTES
RESERVED
RESERVED
FFFFH
0000H
03CFH
6000H
8000H
BFFFH