Renesas 8V19N850 User manual

Guide
8V19N850 HardwareDesign
X0120307 Rev.1.0
Mar 25, 2021
Page 1
© 2021 Renesas Electronics
This document contains general board-level hardware design information for the 8V19N850. It provides
recommendations for power rail handling, loop filter calculation,and input/output termination.
Contents
1. PowerRails.................................................................................................................................2
1.1 Bypass Capacitors................................................................................................................2
1.2 Power Supply Isolation..........................................................................................................3
1.3 Loop Filter...........................................................................................................................3
1.4 2nd Order Loop Filter.............................................................................................................3
1.5 Loop Filter Calculation Examples............................................................................................5
2. Input/Output Interface..................................................................................................................6
2.1 Input Termination for Reference Clock Input .............................................................................6
2.2 OX_DPLL Input (OCXO/TCXO) ..............................................................................................7
2.3 OSCI/OSCO Input (XTAL, XO, OCXO/TCXO)...........................................................................8
2.4 Output Terminations for QCLK and QREF Drivers .....................................................................9
2.4.1. LVPECL Type Driver Terminations .............................................................................9
2.4.2. LVDS Type Driver Terminations ...............................................................................14
3. Schematic Example ...................................................................................................................15
4. Revision History........................................................................................................................15
The simplified block diagramof 8V19N850 is shown in Figure 1. For a more detailed block diagram and in-depth
descriptions about the device, see the 8V19N850 Datasheet.
Figure 1. Simplified Block Diagram
A general reference schematic example is shown in Figure 2. A larger version can also be provided in a
separate document.In this schematic, the input and output interfaces are shown for illustration purposes.For
more examples, see the Input/Output Interface section.The input topology dependson the driver type, and the
output driver termination depends on the receiver specification and structure.

8V19N850 Hardware Design Guide
X0120307 Rev.1.0
Mar 25, 2021
Page 2
Figure 2. 8V19N850 Reference Schematic Example
1. Power Rails
1.1 Bypass Capacitors
To avoid signal interference, bypass capacitors are required to filter noise from switching power supplies and
other devices in the system. Figure 2 showsexamplesof bypass capacitors on the schematic. The type of
bypass capacitor will depend on the noise level and noise frequencies on the application board. The device
output driver switching can also cause power rail noise and interference with noise signalsfrom other devices on
the board, resulting in unwanted spurious tones in outputsignals. The bypass capacitors minimize these noise
sources.
The bypass capacitor values are usually in the range from 0.01µF to 0.1µF. Other values can also be used.
Typical capacitor sizes are 0603, 0402, or 0201 with a low Equivalent Series Resistance (ESR). The dielectric
types are typicallyX5R or X7R. A smaller size allows the capacitorto be placed closer to the powerpin ofthe
device with a reduced trace length.
LVDS Style Termination Ex ample
C22 0.1uF
Zo = 50
QCLK_D13
VDDO_R4
C6
1.0uF
C95
100pF
R7
R9
5.1k
R28 1
VDD_OSC
nQREF_R03
nQREF_R13
R24
100
C1
C70
0.1uF
C56
100pF
C43
0.1uF
nCLK1 2
C48 100pF
C59
10uF
C53
10uF
QREF_R53
Zo
C34 10uF
C49
10uF
C41
100pF
R20
1
VDDO_R23
VDDO_Dx
R27
1k
1k
R30
1
Keep close to DUT
Loop Filter - Keep close to DUT
C5 0.1uF
L18
220
C84 0.1uF
R1
100
QCLK_R0
R2
C30 10uF
L17
220
C47 0.1uF
C80 0.1uF
SDO_SDA 5
C23
10uF
R26
1k
1k
Keep close to DUT
L8220
C38
0.1uF
C9 0.1uF
C72
10uF
C96
0.1uF
QREF_R33
C15
0.1uF
L5 220
C20 0.1uF
C50
100pF
QCLK_R2
C1310uF
VDD_INP
GPIO_2
3
VDDO_REF
nQCLK_D23
VDD_APLL
Ro
PD
C55 0.1uF
QCLK_D03
VDD_DPLL0
C74
0.1uF
C10
22uF
R13
510
C93 0.1uF
nQCLK_D03
SPI_SEL2
R18
1
L9
220
C42
0.1uF
C37 100pF
R6
5.1K
SDI 5
QREF_R13
SCLK_SCL 5
C18
10uF
L7 220
C68 0.1uF
VDD_XO
CLK1 2
C82 100pF
U1
8V19N850
VDD_DPLL0
1
VDDO_REF_2
2
QREF_R0
3
nQREF_R0
4
QREF_R1
5
nQREF_R1
6
QREF_R2
7
nQREF_R2
8
QREF_R3
9
nQREF_R3
10
QREF_R4
11
nQREF_R4
12
QREF_R5
13
nQREF_R5
14
VDDO_REF_15
15
CAP_APLL
16
VDD_APLL
17
CP_APLL
18
GPIO_0
19
GPIO_1
20
GPIO_2
21
GPIO_3
22
VDD_GPIO
23
QCLK_D0
24
SPI_SEL
36 VDDO_D3
35 nQCLK_D3
34 QCLK_D3
33 VDDO_D2
32 nQCLK_D2
31 QCLK_D2
30 VDDO_D1
29 nQCLK_D1
28 QCLK_D1
27 VDDO_D0
26 nQCLK_D0
25
nQCLK_R4 48
VDDO_R4_47 47
DNU-46 46
DNU_45 45
VDD_RFVCO
44 CAP_RFPLL
43 CP_RFPLL
42 VDD_RFPLL
41 VDDO_R5_40
40 nQCLK_R5
39 QCLK_R5
38 VDDO_R5
37
QCLK_R4 49
VDDO_R4_50 50
VDDO_R23_51 51
nQCLK_R3 52
QCLK_R3 53
nQCLK_R2 54
QCLK_R2 55
VDDO_R23_56 56
VDDO_R01_57 57
nQCLK_R1 58
QCLK_R1 59
nQCLK_R0 60
QCLK_R0 61
VDDO_R01_62 62
VDD_DPLL1 63
CP_DPLL1 64
CAP_DPLL1 65
VDD_DC01 66
VDD_INP 67
nCLK1 68
CLK1 69
nCLK0 70
CLK0 71
VDD_SPI 72
nCS/ADR0 73
SCLK/SCL 74
SDO/SDA 75
SDI/ADR1 76
EXT_SYS 77
SCL_M 78
SDA_M 79
OSCO 80
OSCI 81
VREG_OSC_CAP 82
VDD_OSC 83
nXO_DPLL 84
XO_DPLL 85
VDD_XO 86
CP_DPLL0 87
CAP_DPLL0 88
EP 89
L1220
C3 0.1uF
VDD_GPIO
L6 220
C46 0.1uF
C69
33pF
VDD_RFPLL
C61 10uF
R17
1
L2 220
C65
10uF
C7 0.1uF
C77
10uF
QCLK_R53
C88
0.1uF
L21 220 C97
0.1uF
nQREF_R43
nQCLK_R3
R21
300
VDDO_Dx
R8
100
C63
22uF
VCC=3.3V
L20
220
C92 0.1uF
GPIO_0
3
C25 0.1uF
QCLK_D23
C86 100pF
C58
0.1uF
GPIO_1
3C52
0.1uF
CLK
nCLK
nQREF_R23
R321
nQCLK_R1
C36 0.1uF
L14 220
C66 0.1uF
VDD_DPLL1
nCS 5
nQCLK_R0
C32
10uF
Keep close to DUT
VDDO_Dx
C83 10uF
Ro
C31 0.1uF
C79 10uF
L13
220
SDA_M 5
R10 1
PD
C27
22uF
OCXO/TCXO LVCMOS
L12220
C39
10uF
C71
0.1uF
L19
220 C89
0.1uF
C87
100pF
C21 10uF
Zo = 50
C140.1uF
R23 1
VDDO_Dx
C26
33pF
C54
33pF
QREF_R43
EXT_SYS 2
VCC=3.3V
VDD
C24
470pF
QCLK_R3
R33
1
nQCLK_D33
R29
1
QREF_R03
Keep close to DUT
C44
10uF
C57
0.1uF
L11
220
C51
0.1uF
VDDO_REF
C19
0.1uF
C35 0.1uF
R19
1
JP2
GPIO_1
Loop Filter - Keep close to DUT
C4 10uF
QREF_R23
XO/OCXO/TCXO LVCMOS
QCLK_R1
R5
100
C33 0.1uF
C29 0.1uF
C94 100pF
nQCLK_D13
C45 10uF
C62 0.1uF
JP1
GPIO_0
R14 1
C8 10uF
C76
0.1uF
L16
220 C73
0.1uF
C98
10uF
C16
22uF
LVDS Driver
L3220
C120.1uF
R311
nQCLK_R53
SCL_M 5
VDDO_R01
VDDO_R5
C64
0.1uF
R16
2k
C75
22uF
C11
0.1uF
nQREF_R53
R12
NP
R3
100
C91 10uF
VDD_DCO1
Update pin name
R4
100
PU
Zo = 50
Zo = 50
L4220
C17
0.1uF
C67 10uF
VDD_SPI
QCLK_D33
PU
C2
Loop Filter - Keep
close to DUT
GPIO_3
3
nQREF_R33
C85 0.1uF
nQCLK_R2
L10
220
R22
1
R25
200
C81 0.1uF
C60 0.1uF
VDD_RFVCO
C28
0.1uF
VDD_XO
Zo
L15
220
C40
0.1uF
C78
0.1uF
C90
10uF
R11
1

8V19N850 Hardware Design Guide
X0120307 Rev.1.0
Mar 25, 2021
Page 3
To minimize ESR between power pins and the bypasscapacitors,it is recommended to place at least one
bypass capacitor at each VDD power pin, with a placement as near as possible to therespective power pin of
the device. A thick trace width between the bypasscapacitor and power pin helps to reduce ESR. It is
recommended to combine multiple capacitors atdifferent resonance frequenciesto achieve band pass filter
characteristics at the critical noise frequencies.
1.2 Power Supply Isolation
The power rails should be as noise-free as possible to support the low phase noise performance of the device
PLLs. The 8V19N850 also integratesLDOs for additional noise filtering. An external ultra-low noise LDO may not
be required but it is recommended for further reducing power supply noise. AnLDO should have a noise level of
less than 6.5uVrms from 10Hz to100kHz. The Renesas RAA214020 is a suitable LDO.
It is recommended to isolate the analog power rail from other high noise power rails, VDDO_x and VDD_INPUT.
The isolation can be implemented through an RC low pass filter.The larger RCcomponent values can further
reduce the cutoff frequency and clean up lower frequency noise. For the outputsupplies VDDO_x, to reduce
output frequency interference, the powerrails between the output banksthat operate at different output
frequencies can be isolated using separate LDOs or using 1 to 2 ohm resistors if they share the same power
source. Additionalsmaller value capacitors(e.g., 100pF) in parallel with theexisting 0.1µF near the power pins
can provide additional higher frequency noise filtering.
1.3 Loop Filter
1.4 2nd Order Loop Filter
The 8V19N850 contains four Analog PLLs: APLL0,APLL1, APLL2,and RFPLL. These analog PLLsrequire
board-level 2nd order loop filter. The approximate VCO frequency and VCO gains for each APLL isdisplayed in
Table 1. The VCO gain Kvco depend on the operating region.
Table 1. 2nd Order LoopFilter
APLL
ApproximateVCO
Frequency(GHz) Kvco (MHz/V)
APLL0
2.5
30
APLL1
3.93216
48
APLL2
3.75
52
RFPLL
2.94912
38
The following section provides a general design of a 2nd order loop filter for PLL. A typical 2nd order loop filter is
shown in Figure 3. The design shows a step-by-step calculation todetermine Rs, Cs,and Cp values. The
required parameters for this part are also provided. A spreadsheet or software tool for calculating the loop filter
values are also available.
Figure 3. Typical 2nd Order Loop Filter
Cp
Charge Pump Driver
Rs
Loop Filter Return
Cs

8V19N850 Hardware Design Guide
X0120307 Rev.1.0
Mar 25, 2021
Page 4
1. Determine desired loop bandwidth fc. The fc must satisfy the following condition:
20
>>
fc
Fpd
Where, Fpd is phase detector input frequency.
2. Calculate Rs
 =2∗π∗fc ∗N
Icp ∗Kvco
Where,
Icpis charge pump current.
Kvcois VCO gain.
N is effective feedback divider.
Fpd
Fvco
N=
Fvco is vco frequency.
Fpd is the phase detector input frequency.
3. Calculate Cs
 =α
2∗∗ ∗
Where,
α is ratio between loop bandwidth and the zero frequency at zero, α = fc / fz, recommend α greater than 3.
fz is frequency at zero.
4. Calculate Cp
 =Cs
α ∗ β
Where,
βis ratio between frequency at pole and loop bandwidth, β = fp / fc, recommend β greater than 3.
fp is frequency at pole.
5. Verify maximum Phase Margin, PM
)
*2
1
arctan( b
b
PM − =
Where,
b = 1 + 

PM should be greater than 50 degrees.

8V19N850 Hardware Design Guide
X0120307 Rev.1.0
Mar 25, 2021
Page 5
1.5 Loop Filter Calculation Examples
This section provides calculation examplesfor APLL0 loop filter value for loop bandwidth of ~150kHz. In this
example, the reference OCXO input frequency = 48MHz after multiplied by 2, the phase detectorinput frequency
Fpd = 96MHz. This satisfies the condition of Fpd/Fc>> 20.
The APLL0 VCO frequency, Fvco = 2500MHz, the effective feedback divider.
N = Mv= Fvcxo/ Fpd ~ 26
Rs can be calculated from the equation,
 =2∗π∗fc ∗N
Icp ∗Kvco
The APLL0 VCO gain, Kvco ~30MHz/V.
The charge pump current is set as 1.7mAin thisexample.
Rs = 510 Ohm
Cs can be calculated from the following equation,
 =α
2∗∗ ∗
For α = 10, Cs is calculated to be ~20 nF. Csgreater than this value can be used to assure that the α is greater
than 10. For example, the actual chosen value can be 100 nF from a standard capacitor value to allow room for
charge pump current adjustment.
Cp can be calculated from the equation,
 =Cs
α ∗ β
For β = 3, Cp is calculated to be ~650pF. Less than thisvalue can be used for Cp to assure that the β is greater
than 3 (e.g., the actual selected value Cp can be 470 nF).
Phase margin = 67 degrees
The following table shows Loop Filter Value Examples for APLL0, APLL1,APLL2, and RFPLL.The loop filter
values will vary based on the application requirement. Other loop values can also be used as long as the PLLs
operate at the stable region.
Table 2. 8V19N850 Analog PLLs Loop Filter Values Examples
APLL0
APLL1
APLL2
RFPLL
LoopBandwidth(Hz)
150k
600k
80k
80k
PDF
96MHz
96Mhz
78.125MHz
245.76MHz
Feedbackdivider, N
26
40
48
24
Charge Pumpcurrent
setting
Can be setbetw een0.7mA
to 2.2mA
1.7mA
1.7mA
1.7mA
1.7mA
Rs (Ohm )
510
2k
300
200
Cs
100nF
100nF
100nF
100nF
Cp
470pF
~33pF
~33pF
~33pF

8V19N850 Hardware Design Guide
X0120307 Rev.1.0
Mar 25, 2021
Page 6
2. Input/Output Interface
2.1 Input Termination for Reference Clock Input
The 8V19N850 reference clock input CLK/nCLK is a high impedance differential receiver. The inverting input
nCLK has weak bias to ~1.65V. The input can accepta signal from a standard 3.3VLVPECL or an LVDS driver
directly in DC coupling. The board-level termination at the CLK/nCLK inputis determined by the driver type.
Figure 4 and Figure 5 provide examples of input interface without AC coupling.Figure 6 and Figure 7 provide
examples ofinput driven by a differential driver with AC coupling. This section provides only few examples.
Other termination topologiescan also be used.Forsingle-ended driving the differential input, please refer to the
example in the OX_DPLL Input (OCXO/TCXO) input section.
Figure 4. Input TerminationExample – 8V19N850 Reference Clock Input CLK/nCLK, Driven by a 3.3V LVPECL Driver
Figure 5. Input TerminationExample – 8V19N850 Reference Clock Input CLK/nCLK Driven by a 3.3V LVDS Driver
Clock Input
CLK
nCLK
VCC=3.3V
R4
82.5
R2
82.5
R3
133
R1
133
VCC=3.3V
Zo = 50
Zo = 50
LVPECL Driver
VCC=3.3V
VCC=3.3V
Zo = 50
Zo = 50
LVDS Driver
VCC=3.3V
R1
100 Clock Input
CLK
nCLK

8V19N850 Hardware Design Guide
X0120307 Rev.1.0
Mar 25, 2021
Page 7
Figure 6. 8V19N850 Reference Clock Input CLK/nCLK AC Coupling Termination– Example 1
Figure 7. 8V19N850 Reference Clock Input CLK/nCLK AC Coupling Termination– Example 2
2.2 OX_DPLL Input (OCXO/TCXO)
The XO_DPLL input receives a stable frequency source from OCXO/TCXO mainly for SysAPLL and SysDPLL.
This input can also be used for APLL0, APLL1,and APLL2 phase frequencydetector input. The limitation of
frequency range is provided in the 8V19N850 datasheet. When the XO_DPLL input is only used for SysAPLLor
SysDPLL, a stable frequency TCXO/OCXO is required. Low frequency (e.g., 10MHz to 20MHz) is fine. Phase
noise performance is not critical.When the TCXO/OCXO is used for both SysAPLL/SysDPLL and APLL0,
APLL1, both stable frequency and good phase noiseperformance are required. Higher frequency (e.g.,~ 38MHz
to 54MHz) is recommended for better phase noise performance.
XO_DPLL/nXO_DPLL is a differential high-impedance input with built-in weak pull-up and pull-down resistors.
The input termination is dictated by the signal source driver type. Ifthe driver is a differential driver, see the
examples provided in “Input Termination for Reference Clock Input”. Since most OCXO/TCXO drivers are single-
ended drivers, Figure 8 provides an example of single-ended to XO_DPLL input layout. Not all componentsin
the footprint are required to be populated because ofthe varying strength ofthe driver and trace length in the
layout.
VCC=3.3V
Clock Input
CLK
nCLK
R4
10K
R2
10K
R3
5.1K
R1
5.1K
VCC=3.3V
C1
C2
Differential Signal
Zo
Zo
R5
2 x Zo
VCC=3.3V
Clock Input
CLK
nCLK
C1
C2
DifferentialSignal
Zo
Zo
R5
Zo
R4 10K
R3 5.1K
R5
Zo
VCC=3.3V

8V19N850 Hardware Design Guide
X0120307 Rev.1.0
Mar 25, 2021
Page 8
Figure 8. GeneralLayout Example for Single-endedLVCMOStoXO_DPLL
2.3 OSCI/OSCO Input (XTAL, XO, OCXO/TCXO)
The OSCIinput receives a signal from a crystal. It can be overdriven by oscillation sourceslike XO, OCXO, and
TCXO. The limitation of the frequency range is provided in the datasheet. The OSCI input mainly provides a
signal source for APLL0, APLL1, and APLL2. The OCSI source can also be usedto SysAPLL. The OCSI source
cannot be used for SysDPLL. The OCSI signal source phase noise needsto have good performance so that it
provides a good close-end phase noise performance at the 8V19N850output. The OCSI signal source can be
XO, OCXO, or TCXO.
When an XO to OSCI is used in conjunctionwith an OCXO at the XO_DPLL input, the XO is used for APLL0,
APLL1, or APLL2. This OCSI input must be a good phase noise performance and higher frequency (~38MHz to
54MHz). The OCXO to the XO_DPLL to the SysDPLL/SysDPLL must be frequency stable but it doesnot need to
have as good phase noise performance as the XO to the OSCI. The OCXO can be lower frequency (e.g.,
10MHz to 20MHz).
The OCSI/OSCO input containsan oscillation circuitand can interface with a crystal. Figure 9 provides an
example ofa parallel resonant crystal to OCSI/OSCOinput interface. The OCSIinput can also be overdriven by
an oscillator with a single-ended driver. Figure 10 shows an example of a single-ended oscillator overdrive OSCI
input with AC coupling. The unused OCSO can be left floating.
Figure 9. Crystal to OSCI input interface Example
C1
VCC=3.3V
Zo
R3
R2
5.1k
XO_DPLL Input
+
-
OCXO/TCXO LVCMOS
R1
5.1K
R5
100
Ro
R4
100
CL1
8V19N850 OSCI input
OSCI
OSCO
CL2
X1

8V19N850 Hardware Design Guide
X0120307 Rev.1.0
Mar 25, 2021
Page 9
Figure 10. Single-endedOscillator Overdrive OSCI Example
Notes:
1. When OSCIor XO_DPLL is used forinput ofAPLL0 or APLL1 with DPLL0 or DPLL1 active, the selected
frequency cannot cause the APLL0 or APLL1 feedback divider to set to an integer. For example, ifAPLL0
VCO= 2.5GHz, OSCI = 50MHz,the APLL0 PDF =2x50MHz =100MHz, the APLL0 feedbackmust be set to
25. The feedback divider = 25 is an integer. IfDPLL0 is not active, there is no issue. IfDPLL0 is active, this
will create a problem and cause DPLL0 to be unstable; therefore, a 50MHzoscillator cannotbe used under
this condition.
2. When both XO_DPLL and OCSIare used, the two frequencies should not be close to each other.
The following list shows a few examples of OCXO:
■Rakon U7842 or different frequency in the same product family.
■TXC OG48070001 or different frequency in the same product family.
■CTS17 or different frequency in the same product family.
2.4 Output Terminations for QCLK and QREF Drivers
The output stage of the 8V19N850 QCLK drivers can be configured to be LVPECL style driver or LVDS style
driver.
2.4.1. LVPECL Type Driver Terminations
When the 8V19N850 output is configured to LVPECL, the driver is an open emitter type that requires a DC
current path to the termination voltage VTT through the pull-down resistor. A standard LVPECL driver termination
is shown in Figure 10, and Figure 12 to Figure 14 show alternative terminations. The LVPECL output driver is
configurable and the applicable termination voltage VTT depends on the output amplitude setting and output
supply voltage VDDO_v. Refer to the VTT and termination resistor value tables beloweach diagram.
C1
Zo
R3
R2
100
R1
100
Ro
8V19N850 OSCI input
OSCI
OSCO
VDD
OCXO/TCXO LVCMOS

8V19N850 Hardware Design Guide
X0120307 Rev.1.0
Mar 25, 2021
Page 10
Figure 11. LVPECL Style Termination
Table 3. VTValues for Output Termination inFigure 11
Output SupplyVoltage
Output Amplitude
V
TT
V
DDO_V
=1.8V
350mV
V
DDO_v
–1.50V
500mV
V
DDO_v
–1.75V
V
DDO_V
=2.5V
350mV
V
DDO_v
–1.50V
500mV
V
DDO_v
–1.75V
V
DDO_V
=3.3V
350mV
V
DDO_v
–1.50V
500mV
V
DDO_v
–1.75V
750mV
V
DDO_v
–2.0V
1000mV
V
DDO_v
–2.25V
High Impedance Input
+
-
Zo = 50 R1
50 No Built-in Termination
VDDO_v
VTT
Zo = 50
LVPECL Driver R2
50