Renesas M16C/62P Series User manual

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REJ09B0185-0241
16 M16C/62P Group (M16C/62P, M16C/62PT)
Hardware Manual
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
M16C FAMILY / M16C/60 SERIES
Rev.2.41
Revision Date:Jan 10, 2006
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Keep safety first in your circuit designs!
Notes regarding these materials
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with ap-
propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
flammable material or (iii) prevention against any malfunction or mishap.
1. These materials are intended as a reference to assist our customers in the selection of the
Renesas Technology Corp. product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of
any third-party's rights, originating in the use of any product data, diagrams, charts, pro-
grams, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, pro-
grams and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corp. without notice due to
product improvements or other reasons. It is therefore recommended that customers con-
tact Renesas Technology Corp. or an authorized Renesas Technology Corp. product dis-
tributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other
loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by vari-
ous means, including the Renesas Technology Corp. Semiconductor home page (http://
www.renesas.com).
4. When using any or all of the information contained in these materials, including product
data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa-
tion as a total system before making a final decision on the applicability of the information
and products. Renesas Technology Corp. assumes no responsibility for any damage, liabil-
ity or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a
device or system that is used under circumstances in which human life is potentially at
stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology
Corp. product distributor when considering the use of a product contained herein for any
specific purposes, such as apparatus or systems for transportation, vehicular, medical,
aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or repro-
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they must be exported under a license from the Japanese government and cannot be im-
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or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the
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How to Use This Manual
1. Introduction
This hardware manual provides detailed information on the M16C/62P Group (M16C/62P, M16C/62PT) of
microcomputers.
Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers.
2. Register Diagram
The symbols, and descriptions, used for bit function in each register are shown below.
*1Blank: Set to “0” or “1” according to the application
0: Set to “0”
1: Set to “1”
X: Nothing is assigned
*2RW: Read and write
RO: Read only
WO: Write only
−: Nothing is assigned
*3•Reserved bit
Reserved bit. Set to specified value.
*4•Nothing is assigned
Nothing is assigned to the bit concerned. As the bit may be use for future functions,
set to “0” when writing to this bit.
•Do not set to this value
The operation is not guaranteed when a value is set.
•Function varies depending on mode of operation
Bit function varies depending on peripheral function mode.
Refer to respective register for each mode.
XXX Register
Symbol Address After Reset
XXX XXX 00h
Bit NameBit Symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
XXX Bit 1 0: XXX
0 1: XXX
1 0: Avoid this setting
1 1: XXX
b1 b0
XXX1
XXX0
XXX4
Reserved Bit
XXX5
XXX7
XXX6
Function
Nothing is assigned.
When write, should set to “0”. When read, its content is indeterminate.
XXX Bit
Function varies depending on each operation
mode
Must set to “0”
0
(b3)
(b2)
RW
RW
RW
RW
WO
RW
RO
XXX Bit
0: XXX
1: XXX
*1
*2
*3
*4
*5
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3. M16C Family Documents
The following documents were prepared for the M16C family. (1)
NOTES:
1. Before using this material, please visit the our website to confirm that this is the most current
document available.
Document Contents
Short Sheet Hardware overview
Data Sheet Hardware overview and electrical characteristics
Hardware Manual Hardware specifications (pinassignments, memory maps,peripheral
specifications, electrical characteristics, timing charts)
Software Manual Detailed description of assembly instructions and microcomputer
performance of each instruction
Application Note • Application examples of peripheral functions
• Sample programs
• Introduction to the basic functions in the M16C family
• Programming method with Assembly and C languages
RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product, a document,
etc.
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A - 1
SFR Page Reference B - 1
1. Overview 1
1.1 Applications.................................................................................................1
1.2 Performance Outline ...................................................................................2
1.3 Block Diagram.............................................................................................5
1.4 Product List .................................................................................................7
1.5 Pin Configuration.......................................................................................14
1.6 Pin Description..........................................................................................25
2. Central Processing Unit (CPU) 30
2.1 Data Registers (R0, R1, R2 and R3).........................................................30
2.2 Address Registers (A0 and A1).................................................................31
2.3 Frame Base Register (FB) ........................................................................31
2.4 Interrupt Table Register (INTB).................................................................31
2.5 Program Counter (PC) ..............................................................................31
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP).....................31
2.7 Static Base Register (SB)..........................................................................31
2.8 Flag Register (FLG)...................................................................................31
2.8.1 Carry Flag (C Flag).............................................................................31
2.8.2 Debug Flag (D Flag)...........................................................................31
2.8.3 Zero Flag (Z Flag)...............................................................................31
2.8.4 Sign Flag (S Flag)...............................................................................31
2.8.5 Register Bank Select Flag (B Flag)....................................................31
2.8.6 Overflow Flag (O Flag).......................................................................31
2.8.7 Interrupt Enable Flag (I Flag)..............................................................31
2.8.8 Stack Pointer Select Flag (U Flag).....................................................32
2.8.9 Processor Interrupt Priority Level (IPL) ..............................................32
2.8.10 Reserved Area....................................................................................32
3. Memory 33
4. Special Function Register (SFR) 34
5. Reset 40
5.1 Hardware Reset 1 .....................................................................................40
5.1.1 Reset on a Stable Supply Voltage......................................................40
5.1.2 Power-on Reset..................................................................................40
Table of Contents
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A - 2
5.2 Brown-out Detection Reset (Hardware Reset 2).......................................42
5.3 Software Reset..........................................................................................43
5.4 Watchdog Timer Reset.............................................................................43
5.5 Oscillation Stop Detection Reset...............................................................43
5.6 Internal Space...........................................................................................44
6. Voltage Detection Circuit 45
6.1 Low Voltage Detection Interrupt................................................................49
6.2 Limitations on Exiting Stop Mode.............................................................51
6.3 Limitations on Exiting Wait Mode..............................................................51
6.4 Cold Start-up / Warm Start-up Determine Function ..................................52
7. Processor Mode 54
7.1 Types of Processor Mode .........................................................................54
7.2 Setting Processor Modes..........................................................................55
8. Bus 59
8.1 Bus Mode..................................................................................................59
8.1.1 Separate Bus......................................................................................59
8.1.2 Multiplexed Bus..................................................................................59
8.2 Bus Control................................................................................................60
8.2.1 Address Bus.......................................................................................60
8.2.2 Data Bus.............................................................................................60
8.2.3 Chip Select Signal..............................................................................60
8.2.4 Read and Write Signals......................................................................63
8.2.5 ALE Signal..........................................................................................63
8.2.6 RDY Signal.........................................................................................64
8.2.7 HOLD Signal.......................................................................................65
8.2.8 8.2.8 BCLK Output .............................................................................65
8.2.9 External Bus Status When Internal Area Accessed ..........................67
8.2.10 Software Wait.....................................................................................68
9. Memory Space Expansion Function 72
9.1 1-Mbyte Mode ...........................................................................................72
9.2 4-Mbyte Mode ...........................................................................................72
9.2.1 9.2.1 Addresses 04000h to 3FFFFh, C0000h to FFFFFh..................72
9.2.2 9.2.2 Addresses 40000h to BFFFFh ..................................................72
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A - 3
10. Clock Generation Circuit 82
10.1 Types of the Clock Generation Circuit.......................................................82
10.1.1 Main Clock..........................................................................................89
10.1.2 Sub Clock...........................................................................................90
10.1.3 On-chip Oscillator Clock.....................................................................91
10.1.4 PLL Clock...........................................................................................91
10.2 CPU Clock and Peripheral Function Clock................................................93
10.2.1 CPU Clock and BCLK.........................................................................93
10.2.2 Peripheral Function Clock (f1, f2, f8, f32, f1SIO, f2SIO, f8SIO,
f32SIO, fAD, fC32)..............................................................................93
10.3 Clock Output Function...............................................................................93
10.4 Power Control............................................................................................94
10.4.1 Normal Operating Mode.....................................................................94
10.4.2 Wait Mode ..........................................................................................96
10.4.3 Stop Mode..........................................................................................98
10.5 System Clock Protection Function ..........................................................102
10.6 Oscillation Stop and Re-oscillation Detect Function................................103
10.6.1 Operation When CM27 bit = 0 (Oscillation Stop Detection Reset)...103
10.6.2 Operation When CM27 bit = 0 (Oscillation Stop and Re-oscillation
Detect Interrupt)................................................................................103
10.6.3 How to Use Oscillation Stop and Re-oscillation Detect Function.....104
11. Protection 105
12. Interrupt 106
12.1 Type of Interrupts....................................................................................106
12.2 Software Interrupts..................................................................................107
12.2.1 Undefined Instruction Interrupt.........................................................107
12.2.2 Overflow Interrupt.............................................................................107
12.2.3 BRK Interrupt....................................................................................107
12.2.4 INT Instruction Interrupt....................................................................107
12.3 Hardware Interrupts.................................................................................108
12.3.1 Special Interrupts..............................................................................108
12.3.2 Peripheral Function Interrupts..........................................................108
12.4 Interrupts and Interrupt Vector ................................................................109
12.4.1 Fixed Vector Tables..........................................................................109
12.4.2 Relocatable Vector Tables ...............................................................110
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A - 4
12.5 Interrupt Control ......................................................................................111
12.5.1 I Flag.................................................................................................113
12.5.2 IR Bit.................................................................................................113
12.5.3 ILVL2 to ILVL0 Bits and IPL .............................................................113
12.5.4 Interrupt Sequence...........................................................................114
12.5.5 Interrupt Response Time..................................................................115
12.5.6 Variation of IPL when Interrupt Request is Accepted.......................115
12.5.7 Saving Registers ..............................................................................116
12.5.8 Returning from an Interrupt Routine.................................................118
12.5.9 Interrupt Priority................................................................................118
12.5.10 Interrupt Priority Level Select Circuit................................................119
12.6 INT Interrupt............................................................................................120
12.7 NMI Interrupt ...........................................................................................121
12.8 Key Input Interrupt...................................................................................121
12.9 Address Match Interrupt..........................................................................122
13. Watchdog Timer 124
13.1 Count source protective mode ................................................................125
14. DMAC 126
14.1 Transfer Cycles.......................................................................................132
14.1.1 Effect of Source and Destination Addresses....................................132
14.1.2 Effect of BYTE Pin Level..................................................................132
14.1.3 Effect of Software Wait.....................................................................132
14.1.4 Effect of RDY Signal.........................................................................132
14.2 DMA Transfer Cycles..............................................................................134
14.3 DMA Enable............................................................................................135
14.4 DMA Request..........................................................................................135
14.5 Channel Priority and DMA Transfer Timing.............................................136
15. Timers 137
15.1 Timer A....................................................................................................139
15.1.1 Timer Mode ......................................................................................144
15.1.2 Event Counter Mode.........................................................................146
15.1.3 One-shot Timer Mode.......................................................................151
15.1.4 Pulse Width Modulation (PWM) Mode..............................................153
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A - 5
15.2 Timer B....................................................................................................156
15.2.1 Timer Mode ......................................................................................159
15.2.2 Event Counter Mode.........................................................................160
15.2.3 Pulse Period and Pulse Width Measurement Mode.........................162
16. Three-Phase Motor Control Timer Function 165
17. Serial Interface 176
17.1 UARTi (i=0 to 2) ......................................................................................176
17.1.1 Clock Synchronous Serial I/O Mode.................................................189
17.1.2 Clock Asynchronous Serial I/O (UART) Mode..................................197
17.1.3 Special Mode 1 (I2C mode)..............................................................205
17.1.4 Special Mode 2.................................................................................215
17.1.5 Special Mode 3 (IE mode)................................................................220
17.1.6 Special Mode 4 (SIM Mode) (UART2)..............................................222
17.2 SI/O3 and SI/O4......................................................................................227
17.2.1 SI/Oi Operation Timing.....................................................................231
17.2.2 CLK Polarity Selection......................................................................231
17.2.3 Functions for Setting an SOUTi Initial Value....................................232
18. A/D Converter 233
18.1 Mode Description ....................................................................................238
18.1.1 One-Shot Mode................................................................................238
18.1.2 Repeat Mode....................................................................................240
18.1.3 Single Sweep Mode..........................................................................242
18.1.4 Repeat Sweep Mode 0.....................................................................244
18.1.5 Repeat Sweep Mode 1.....................................................................246
18.2 Function...................................................................................................248
18.2.1 Resolution Select Function...............................................................248
18.2.2 Sample and Hold..............................................................................248
18.2.3 Extended Analog Input Pins.............................................................248
18.2.4 18.2.4 External Operation Amplifier (Op-Amp) Connection Mode....248
18.2.5 18.2.5 Current Consumption Reducing Function .............................249
18.2.6 Output Impedance of Sensor under A/D Conversion.......................249
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A - 6
19. D/A Converter 251
20. CRC Calculation 253
21. Programmable I/O Ports 255
21.1 Port Pi Direction Register (PDi Register, i = 0 to 13) ..............................256
21.2 Port Pi Register (Pi Register, i = 0 to 13) ................................................256
21.3 Pull-up Control Register 0 to Pull-up Control Register 3
(PUR0 to PUR3 Registers).....................................................................256
21.4 Port Control Register (PCR Register) .....................................................256
22. Flash Memory Version 270
22.1 Memory Map ...........................................................................................272
22.1.1 Boot Mode........................................................................................273
22.2 Functions To Prevent Flash Memory from Rewriting..............................273
22.2.1 ROM Code Protect Function ............................................................273
22.2.2 ID Code Check Function ..................................................................273
22.3 CPU Rewrite Mode..................................................................................275
22.3.1 EW0 Mode........................................................................................276
22.3.2 EW1 Mode........................................................................................276
22.3.3 Flash memory Control Register (FIDR, FMR0 and FMR1 registers)276
22.3.4 Precautions on CPU Rewrite Mode..................................................284
22.3.5 Software Commands.......................................................................286
22.3.6 Data Protect Function.......................................................................291
22.3.7 Status Register.................................................................................291
22.3.8 Full Status Check .............................................................................293
22.4 Standard Serial I/O Mode........................................................................295
22.4.1 ID Code Check Function ..................................................................295
22.4.2 Example of Circuit Application in the Standard Serial I/O Mode ......301
22.5 Parallel I/O Mode.....................................................................................303
22.5.1 User ROM and Boot ROM Areas .....................................................303
22.5.2 ROM Code Protect Function ............................................................303
23. Electrical Characteristics 304
23.1 Electrical Characteristics (M16C/62P).....................................................304
23.2 Electrical Characteristics (M16C/62PT) ..................................................346
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A - 7
24. Precautions 359
24.1 SFR.........................................................................................................359
24.1.1 Register Settings..............................................................................359
24.2 Reset.......................................................................................................360
24.3 Bus..........................................................................................................361
24.4 PLL Frequency Synthesizer....................................................................362
24.5 Power Control..........................................................................................363
24.6 Protect.....................................................................................................365
24.7 Interrupt...................................................................................................366
24.7.1 Reading address 00000h .................................................................366
24.7.2 Setting the SP...................................................................................366
24.7.3 The NMI Interrupt .............................................................................366
24.7.4 Changing the Interrupt Generate Factor...........................................367
24.7.5 INT Interrupt .....................................................................................367
24.7.6 Rewrite the Interrupt Control Register..............................................368
24.7.7 Watchdog Timer Interrupt.................................................................368
24.8 DMAC......................................................................................................369
24.8.1 Write to DMAE Bit in DMiCON Register...........................................369
24.9 Timers .....................................................................................................370
24.9.1 Timer A.............................................................................................370
24.9.2 Timer B.............................................................................................372
24.10 Serial interface ........................................................................................373
24.10.1 Clock Synchronous Serial I/O...........................................................373
24.10.2 UART................................................................................................374
24.10.3 SI/O3, SI/O4.....................................................................................374
24.11 A/D Converter..........................................................................................375
24.12 Programmable I/O Ports..........................................................................377
24.13 Electric Characteristic Differences Between Mask ROM
and Flash Memory Version Microcomputers...........................................378
24.14 Mask ROM ..............................................................................................378
24.15 Flash Memory Version ............................................................................379
24.15.1 Functions to Inhibit Rewriting Flash Memory Rewrite ......................379
24.15.2 Stop mode........................................................................................379
24.15.3 Wait mode ........................................................................................379
24.15.4 Low power dissipation mode, on-chip oscillator low power dissipation mode ....379
24.15.5 Writing command and data...............................................................379
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A - 8
24.15.6 Program Command..........................................................................379
24.15.7 Lock Bit Program Command ............................................................379
24.15.8 Operation speed...............................................................................380
24.15.9 Instructions inhibited against use .....................................................380
24.15.10Interrupts ..........................................................................................380
24.15.11How to access..................................................................................380
24.15.12Writing in the user ROM area...........................................................380
24.15.13DMA transfer ....................................................................................381
24.15.14Regarding Programming/Erasing Endurance and Execution Time..381
24.16 Noise.......................................................................................................382
25. Differences Depending on Manufacturing Period 383
Appendix 1. Package Dimensions 385
Appendix 2. Difference between M16C/62P and M16C/30P 387
Register Index 390
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B - 1
NOTES:
1. Blank columns are all reserved space. No access is allowed.
Address Register Symbol Page
0000h
0001h
0002h
0003h
0004h Processor Mode Register 0 PM0 56
0005h Processor Mode Register 1 PM1 57
0006h System Clock Control Register 0 CM0 84
0007h System Clock Control Register 1 CM1 85
0008h Chip Select Control Register CSR 61
0009h Address Match Interrupt Enable Register AIER 123
000Ah Protect Register PRCR 105
000Bh Data Bank Register DBR 73
000Ch Oscillation Stop Detection Register CM2 86
000Dh
000Eh Watchdog Timer Start Register WDTS 125
000Fh Watchdog Timer Control Register WDC 53, 125
0010h Address Match Interrupt Register 0 RMAD0 123
0011h
0012h
0013h
0014h Address Match Interrupt Register 1 RMAD1 123
0015h
0016h
0017h
0018h
0019h Voltage Detection Register 1 VCR1 46
001Ah Voltage Detection Register 2 VCR2 46
001Bh Chip Select Expansion Control Register CSE 68
001Ch PLL Control Register 0 PLC0 88
001Dh
001Eh Processor Mode Register 2 PM2 87
001Fh Low Voltage Detection Interrupt Register D4INT 47
0020h DMA0 Source Pointer SAR0 131
0021h
0022h
0023h
0024h DMA0 Destination Pointer DAR0 131
0025h
0026h
0027h
0028h DMA0 Transfer Counter TCR0 131
0029h
002Ah
002Bh
002Ch DMA0 Control Register DM0CON 130
002Dh
002Eh
002Fh
0030h DMA1 Source Pointer SAR1 131
0031h
0032h
0033h
0034h DMA1 Destination Pointer DAR1 131
0035h
0036h
0037h
0038h DMA1 Transfer Counter TCR1 131
0039h
003Ah
003Bh
003Ch DMA1 Control Register DM1CON 130
003Dh
003Eh
003Fh
Address Register Symbol Page
0040h
0041h
0042h
0043h
0044h INT3 Interrupt Control Register INT3IC 112
0045h Timer B5 Interrupt Control Register TB5IC 111
0046h Timer B4 Interrupt Control Register, UART1 BUS
Collision Detection Interrupt Control Register TB4IC, U1BCNIC 111
0047h Timer B3 Interrupt Control Register, UART0 BUS
Collision Detection Interrupt Control Register TB3IC, U0BCNIC 111
0048h SI/O4 Interrupt Control Register, INT5 Interrupt
Control Register S4IC, INT5IC 112
0049h SI/O3 Interrupt Control Register, IINT4 Interrupt
Control Register S3IC, INT4IC 112
004Ah UART2 Bus Collision Detection Interrupt Control Register BCNIC 111
004Bh DMA0 Interrupt Control Register DM0IC 111
004Ch DMA1 Interrupt Control Register DM1IC 111
004Dh Key Input Interrupt Control Register KUPIC 111
004Eh A/D Conversion Interrupt Control Register ADIC 111
004Fh UART2 Transmit Interrupt Control Register S2TIC 111
0050h UART2 Receive Interrupt Control Register S2RIC 111
0051h UART0 Transmit Interrupt Control Register S0TIC 111
0052h UART0 Receive Interrupt Control Register S0RIC 111
0053h UART1 Transmit Interrupt Control Register S1TIC 111
0054h UART1 Receive Interrupt Control Register S1RIC 111
0055h Timer A0 Interrupt Control Register TA0IC 111
0056h Timer A1 Interrupt Control Register TA1IC 111
0057h Timer A2 Interrupt Control Register TA2IC 111
0058h Timer A3 Interrupt Control Register TA3IC 111
0059h Timer A4 Interrupt Control Register TA4IC 111
005Ah Timer B0 Interrupt Control Register TB0IC 111
005Bh Timer B1 Interrupt Control Register TB1IC 111
005Ch Timer B2 Interrupt Control Register TB2IC 111
005Dh INT0 Interrupt Control Register INT0IC 112
005Eh INT1 Interrupt Control Register INT1IC 112
005Fh INT2 Interrupt Control Register INT2IC 112
0060h
0061h
0062h
0062h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
SFR Page Reference
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B - 2
NOTES:
1. Blank columns are all reserved space. No access is allowed.
Address Register Symbol Page
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
to
01AFh
01B0h
01B2h
01B3h
01B4h Flash Identification Register FIDR 276
01B5h Flash Memory Control Register 1 FMR1 278
01B6h
01B7h Flash Memory Control Register 0 FMR0 277
01B8h Address Match Interrupt Register 2 RMAD2 123
01B9h
01BAh
01BBh Address Match Interrupt Enable Register 2 AIER2 123
01BCh Address Match Interrupt Register 3 RMAD3 123
01BDh
01BEh
01BFh
01C0h
to
02AFh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh Peripheral Clock Select Register PCLKR 87
025Fh
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
to
0335h
0336h
0337h
0338h
0339h
033Ah
033Bh
033Ch
033Dh
033Eh
033Fh
Address Register Symbol Page
0340h Timer B3, 4, 5 Count Start Flag TBSR 158
0341h
0342h Timer A1-1 Register TA11 169
0343h
0344h Timer A2-1 Register TA21 169
0345h
0346h Timer A4-1 Register TA41 169
0347h
0348h Three-Phase PWM Control Register 0 INVC0 167
0349h Three-Phase PWM Control Register 1 INVC1 168
034Ah Three-Phase Output Buffer Register 0 IDB0 170
034Bh Three-Phase Output Buffer Register 1 IDB1 170
034Ch Dead Time Timer DTT 171
034Dh Timer B2 Interrupt Occurrence Frequency Set
Counter ICTB2 169
034Eh
034Fh
0350h Timer B3 Register TB3 157
0351h
0352h Timer B4 Register TB4 157
0353h
0354h Timer B5 Register TB5 157
0355h
0356h
0357h
0358h
0359h
035Ah
035Bh Timer B3 Mode Register TB3MR 157
035Ch Timer B4 Mode Register TB4MR 157
035Dh Timer B5 Mode Register TB5MR 157
035Eh Interrupt Factor Select Register 2 IFSR2A 120
035Fh Interrupt Factor Select Register IFSR 120
0360h SI/O3 Transmit/Receive Register S3TRR 229
0361h
0362h SI/O3 Control Register S3C 228
0363h SI/O3 Bit Rate Generator S3BRG 229
0364h SI/O4 Transmit/Receive Register S4TRR 229
0365h
0366h SI/O4 Control Register S4C 228
0367h SI/O4 Bit Rate Generator S4BRG 229
0368h
0369h
036Ah
036Bh
036Ch UART0 Special Mode Register 4 U0SMR4 188
036Dh UART0 Special Mode Register 3 U0SMR3 187
036Eh UART0 Special Mode Register 2 U0SMR2 187
036Fh UART0 Special Mode Register U0SMR 186
0370h UART1 Special Mode Register 4 U1SMR4 188
0371h UART1 Special Mode Register 3 U1SMR3 187
0372h UART1 Special Mode Register 2 U1SMR2 187
0373h UART1 Special Mode Register U1SMR 186
0374h UART2 Special Mode Register 4 U2SMR4 188
0375h UART2 Special Mode Register 3 U2SMR3 187
0376h UART2 Special Mode Register 2 U2SMR2 187
0377h UART2 Special Mode Register U2SMR 186
0378h UART2 Transmit/Receive Mode Register U2MR 183
0379h UART2 Bit Rate Generator U2BRG 182
037Ah UART2 Transmit Buffer Register U2TB 181
037Bh
037Ch UART2 Transmit/Receive Control Register 0 U2C0 184
037Dh UART2 Transmit/Receive Control Register 1 U2C1 185
037Eh UART2 Receive Buffer Register U2RB 181
037Fh
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B - 3
NOTES:
1. Blank columns are all reserved space. No access is allowed.
Address Register Symbol Page
0380h Count Start Flag TABSR 141, 158
0381h Clock Prescaler Reset Fag CPSRF 143, 158
0382h One-Shot Start Flag ONSF 142
0383h Trigger Select Register TRGSR 142
0384h Up-Down Flag UDF 141
0385h
0386h Timer A0 Register TA0 140
0387h
0388h Timer A1 Register TA1 140
0389h
038Ah Timer A2 Register TA2 140
038Bh
038Ch Timer A3 Register TA3 140
038Dh
038Eh Timer A4 Register TA4 140
038Fh
0390h Timer B0 Register TB0 157
0391h
0392h Timer B1 Register TB1 157
0393h
0394h Timer B2 Register TB2 157
0395h
0396h Timer A0 Mode Register TA0MR 140
0397h Timer A1 Mode Register TA1MR 140
0398h Timer A2 Mode Register TA2MR 140
0399h Timer A3 Mode Register TA3MR 140
039Ah Timer A4 Mode Register TA4MR 140
039Bh Timer B0 Mode Register TB0MR 157
039Ch Timer B1 Mode Register TB1MR 157
039Dh Timer B2 Mode Register TB2MR 157
039Eh Timer B2 Special Mode Register TB2SC 170
039Fh
03A0h UART0 Transmit/Receive Mode Register U0MR 183
03A1h UART0 Bit Rate Generator U0BRG 182
03A2h UART0 Transmit Buffer Register U0TB 181
03A3h
03A4h UART0 Transmit/Receive Control Register 0 U0C0 184
03A5h UART0 Transmit/Receive Control Register 1 U0C1 185
03A6h UART0 Receive Buffer Register U0RB 181
03A7h
03A8h UART1 Transmit/Receive Mode Register U1MR 183
03A9h UART1 Bit Rate Generator U1BRG 182
03AAh UART1 Transmit Buffer Register U1TB 181
03ABh
03ACh UART1 Transmit/Receive Control Register 0 U1C0 184
03ADh UART1 Transmit/Receive Control Register 1 U1C1 185
03AEh UART1 Receive Buffer Register U1RB 181
03AFh
03B0h UART Transmit/Receive Control Register 2 UCON 186
03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h
03B8h DMA0 Request Factor Select Register DM0SL 128
03B9h
03BAh DMA1 Request Factor Select Register DM1SL 129
03BBh
03BCh CRC Data Register CRCD 253
03BDh
03BEh CRC Input Register CRCIN 253
03BFh
Address Register Symbol Page
03C0h A/D Register 0 AD0 237
03C1h
03C2h A/D Register 1 AD1 237
03C3h
03C4h A/D Register 2 AD2 237
03C5h
03C6h A/D Register 3 AD3 237
03C7h
03C8h A/D Register 4 AD4 237
03C9h
03CAh A/D Register 5 AD5 237
03CBh
03CCh A/D Register 6 AD6 237
03CDh
03CEh A/D Register 7 AD7 237
03CFh
03D0h
03D1h
03D2h
03D3h
03D4h A/D Control Register 2 ADCON2 236
03D5h
03D6h A/D Control Register 0 ADCON0 235
03D7h A/D Control Register 1 ADCON1 235
03D8h D/A Register 0 DA0 252
03D9h
03DAh D/A Register 1 DA1 252
03DBh
03DCh D/A Control Register DACON 252
03DDh
03DEh Port P14 Control Register PC14 264
03DFh Pull-Up Control Register 3 PUR3 264
03E0h Port P0 Register P0 263
03E1h Port P1 Register P1 263
03E2h Port P0 Direction Register PD0 262
03E3h Port P1 Direction Register PD1 262
03E4h Port P2 Register P2 263
03E5h Port P3 Register P3 263
03E6h Port P2 Direction Register PD2 262
03E7h Port P3 Direction Register PD3 262
03E8h Port P4 Register P4 263
03E9h Port P5 Register P5 263
03EAh Port P4 Direction Register PD4 262
03EBh Port P5 Direction Register PD5 262
03ECh Port P6 Register P6 263
03EDh Port P7 Register P7 263
03EEh Port P6 Direction Register PD6 262
03EFh Port P7 Direction Register PD7 262
03F0h Port P8 Register P8 263
03F1h Port P9 Register P9 263
03F2h Port P8 Direction Register PD8 262
03F3h Port P9 Direction Register PD9 262
03F4h Port P10 Register P10 263
03F5h Port P11 Register P11 263
03F6h Port P10 Direction Register PD10 262
03F7h Port P11 Direction Register PD11 262
03F8h Port P12 Register P12 263
03F9h Port P13 Register P13 263
03FAh Port P12 Direction Register PD12 262
03FBh Port P13 Direction Register PD13 262
03FCh Pull-Up Control Register 0 PUR0 265
03FDh Pull-Up Control Register 1 PUR1 265
03FEh Pull-Up Control Register 2 PUR2 266
03FFh Port Control Register PCR 266
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REJ09B0185-0241
M16C/62P Group (M16C/62P, M16C/62PT)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1. Overview
The M16C/62P Group (M16C/62P, M16C/62PT) of single-chip microcomputers are built using the high performance
silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 80-pin, 100-pin and 128-pin
plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level
of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In
addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction processing
capability, makes it suitable for control of various OA, communication, and industrial equipment which requires high-
speed arithmetic/logic operations.
1.1 Applications
Audio, cameras, television, home appliance, office/communications/portable/industrial equipment, automobile,
etc.
Specifications written in this manual are believed to be accurate,
but are not guaranteed to be entirely free of error. Specifications in
this manual may be changed for functional or performance
improvements. Please make sure your manual is the latest edition.
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M16C/62P Group (M16C/62P, M16C/62PT) 1.Overview
Rev.2.41 Jan 10, 2006 Page 2 of 390
REJ09B0185-0241
1.2 Performance Outline
Table 1.1 to 1.3 list Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version).
NOTES:
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See Table 1.8 Product Code for the program and erase endurance, and operating ambient temperature.
In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release
schedule.
4. All options are on request basis.
Table 1.1 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version)
Item Performance
M16C/62P
CPU Number of Basic Instructions 91 instructions
Minimum Instruction Execution
Time 41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Operating Mode Single-chip, memory expansion and microprocessor mode
Address Space 1 Mbyte (Available to 4 Mbytes by memory space expansion
function)
Memory Capacity See Table 1.4 to 1.5 Product List
Peripheral
Function Port Input/Output : 113 pins, Input : 1 pin
Multifunction Timer Timer A : 16 bits x 5 channels,
Timer B : 16 bits x 6 channels,
Three phase motor control circuit
Serial Interface 3 channels
Clock synchronous, UART, I2C bus(1), IEBus(2)
2 channels
Clock synchronous
A/D Converter 10-bit A/D converter: 1 circuit, 26 channels
D/A Converter 8 bits x 2 channels
DMAC 2 channels
CRC Calculation Circuit CCITT-CRC
Watchdog Timer 15 bits x 1 channel (with prescaler)
Interrupt Internal: 29 sources, External: 8 sources, Software: 4 sources,
Priority level: 7 levels
Clock Generation Circuit 4 circuits
Main clock generation circuit (*),
Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Oscillation Stop Detection
Function Stop detection of main clock oscillation, re-oscillation detection function
Voltage Detection Circuit Available (option(4))
Electric
Characteristics Supply Voltage VCC1=3.0 to 5.5 V, VCC2=2.7V to VCC1 (f(BCLK=24MHz) VCC1=2.7 to 5.5 V, VCC2=2.7V to VCC1 (f(BCLK=10MHz)
Power Consumption 14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz)
1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode)
0.7µA (VCC1=VCC2=3V, stop mode)
Flash memory
version Program/Erase Supply Voltage 3.3±0.3 V or 5.0±0.5 V
Program and Erase Endurance 100 times (all area)
or 1,000 times (user ROM area without block A and block 1)
/ 10,000 times (block A, block 1) (3)
Operating Ambient Temperature -20 to 85°C,
-40 to 85°C (3)
Package 128-pin plastic mold LQFP
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M16C/62P Group (M16C/62P, M16C/62PT) 1.Overview
Rev.2.41 Jan 10, 2006 Page 3 of 390
REJ09B0185-0241
NOTES:
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient
temperature.
In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release
schedule.
4. Use the M16C/62PT on VCC1=VCC2
5. All options are on request basis.
Table 1.2 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(100-pin version)
Item Performance
M16C/62P M16C/62PT(4)
CPU Number of Basic Instructions 91 instructions
Minimum Instruction
Execution Time
41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)
Operating Mode Single-chip, memory expansion
and microprocessor mode Single-chip
Address Space 1 Mbyte (Available to 4 Mbytes by
memory space expansion function) 1 Mbyte
Memory Capacity See Table 1.4 to 1.7 Product List
Peripheral
Function Port Input/Output : 87 pins, Input : 1 pin
Multifunction Timer Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels,
Three phase motor control circuit
Serial Interface 3 channels
Clock synchronous, UART, I2C bus(1), IEBus(2)
2 channels
Clock synchronous
A/D Converter 10-bit A/D converter: 1 circuit, 26 channels
D/A Converter 8 bits x 2 channels
DMAC 2 channels
CRC Calculation Circuit CCITT-CRC
Watchdog Timer 15 bits x 1 channel (with prescaler)
Interrupt
Internal: 29 sources, External: 8 sources, Software: 4 sources, Priority level: 7 levels
Clock Generation Circuit 4 circuits
Main clock generation circuit (*), Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Oscillation Stop
Detection Function Stop detection of main clock oscillation, re-oscillation detection function
Voltage Detection Circuit Available (option (5))Absent
Electric
Characteristics
Supply Voltage VCC1=3.0 to 5.5 V, VCC2=2.7V to
VCC1 (f(BCLK=24MHz)
VCC1=2.7 to 5.5 V, VCC2=2.7V to
VCC1 (f(BCLK=10MHz)
VCC1=VCC2=4.0 to 5.5V
(f(BCLK=24MHz)
Power Consumption
14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz)
1.8
µ A (VCC1=VCC2=3V, f(XCIN)=32kHz,
wait mode)
0.7
µ A (VCC1=VCC2=3V, stop mode)
14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
2.0
µ A (VCC1=VCC2=5V, f(XCIN)=32kHz,
wait mode)
0.8
µ A (VCC1=VCC2=5V, stop mode)
Flash memory
version
Program/Erase Supply Voltage 3.3±0.3 V or 5.0±0.5 V 5.0±0.5 V
Program and Erase
Endurance 100 times (all area) or 1,000 times (user ROM area without block A and block 1)
/ 10,000 times (block A, block 1) (3)
Operating Ambient Temperature -20 to 85°C,
-40 to 85°C (3) T version : -40 to 85°C
V version : -40 to 125°C
Package 100-pin plastic mold QFP, LQFP
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M16C/62P Group (M16C/62P, M16C/62PT) 1.Overview
Rev.2.41 Jan 10, 2006 Page 4 of 390
REJ09B0185-0241
NOTES:
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient
temperature.
In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release
schedule.
4. All options are on request basis.
Table 1.3 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(80-pin version)
Item Performance
M16C/62P M16C/62PT(4)
CPU Number of Basic Instructions 91 instructions
Minimum Instruction
Execution Time
41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)
Operating Mode Single-chip mode
Address Space 1 Mbyte
Memory Capacity See Table 1.4 to 1.7 Product List
Peripheral
Function Port Input/Output : 70 pins, Input : 1 pin
Multifunction Timer Timer A : 16 bits x 5 channels (Timer A1 and A2 are internal timer),
Timer B : 16 bits x 6 channels (Timer B1 is internal timer)
Serial Interface 2 channels
Clock synchronous, UART, I2C bus(1), IEBus(2)
1 channel
Clock synchronous, I2C bus(1), IEBus(2)
2 channels
Clock synchronous (1 channel is only transmission)
A/D Converter 10-bit A/D converter: 1 circuit, 26 channels
D/A Converter 8 bits x 2 channels
DMAC 2 channels
CRC Calculation Circuit CCITT-CRC
Watchdog Timer 15 bits x 1 channel (with prescaler)
Interrupt
Internal: 29 sources, External: 5 sources, Software: 4 sources, Priority level: 7 levels
Clock Generation Circuit 4 circuits
Main clock generation circuit (*), Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Oscillation Stop
Detection Function Stop detection of main clock oscillation, re-oscillation detection function
Voltage Detection Circuit Available (option (4))Absent
Electric
Characteristics
Supply Voltage VCC1=3.0 to 5.5 V, (f(BCLK=24MHz)
VCC1=2.7 to 5.5 V, (f(BCLK=10MHz) VCC1=4.0 to 5.5V, (f(BCLK=24MHz)
Power Consumption 14 mA (VCC1=5V, f(BCLK)=24MHz)
8 mA (VCC1=3V, f(BCLK)=10MHz)
1.8
µ A (VCC1=3V, f(XCIN)=32kHz,
wait mode)
0.7µA (VCC1=3V, stop mode)
14 mA (VCC1=5V, f(BCLK)=24MHz)
2.0 µ A (VCC1=5V, f(XCIN)=32kHz,
wait mode)
0.8µA (VCC1=5V, stop mode)
Flash memory
version
Program/Erase Supply Voltage 3.3 ± 0.3V or 5.0 ± 0.5V 5.0 ± 0.5V
Program and Erase
Endurance 100 times (all area) or 1,000 times (user ROM area without block A and block 1)
/ 10,000 times (block A, block 1) (3)
Operating Ambient Temperature -20 to 85°C,
-40 to 85°C (3) T version : -40 to 85°C
V version : -40 to 125°C
Package 80-pin plastic mold QFP
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M16C/62P Group (M16C/62P, M16C/62PT) 1.Overview
Rev.2.41 Jan 10, 2006 Page 5 of 390
REJ09B0185-0241
1.3 Block Diagram
Figure 1.1 is a M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram,
Figure 1.2 is a M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram.
Figure 1.1 M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram
Output (timer A): 5
Input (timer B): 6
Internal peripheral functions
Watchdog timer
(15 bits)
DMAC
(2 channels)
D/A converter
(8 bits X 2 channels)
Memory
ROM (1)
RAM (2)
A/D converter
(10 bits X8 channels
Expandable up to 26 channels)
UART or
clock synchronous serial I/O
(8 bits X 3 channels)
System clock
generation circuit
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
M16C/60 series16-bit CPU core
Port P0
8
Port P1
8
Port P2
8 8 8 8
Port P6
8
8
R0LR0H
R1H R1L
R2
R3
A0
A1
FB
SB
ISP
USP
INTB
CRC arithmetic circuit (CCITT )
(Polynomial : X16+X12+X5+1)
Multiplier
7 8 8
Port P10
Port P9
Port P8_5Port P8
Port P7
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. Ports P11 to P14 exist only in 128-pin version.
4. Use M16C/62PT on VCC1= VCC2.
Port P5
Port P4Port P3
Clock synchronous serial I/O
(8 bits X 2 channels)
PC
FLG
Timer (16-bit)
Three-phase motor
control circuit
8 8 82
Port P11 Port P12Port P14 Port P13
(3)
<VCC2 ports>(4) <VCC1 ports>(4)
<VCC1 ports>(4)
<VCC2 ports>(4)<VCC1 ports>(4)
(3) (3) (3)
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