Renesas P9235A-RB User manual

P9235A-RB Layout Guide
© 2019 Integrated Device Technology, Inc.
1
March 19, 2019
Contents
1. Introduction...................................................................................................................................................................................................2
Key Points for Optimal Layout.............................................................................................................................................................2
2. Tx Power Circuits.........................................................................................................................................................................................3
Resonance Capacitors........................................................................................................................................................................8
VCC5V VIN, VCC5V, LDO33, LDO18, VBRG_IN, PE Circuit and DRV_VIN Pin Capacitors...............................................................9
Sensitive Circuits...............................................................................................................................................................................10
Boost Capacitors and Gate Drive Lines.............................................................................................................................................11
5V Step Down Switching Regulator...................................................................................................................................................12
Flash Circuit.......................................................................................................................................................................................13
3. PCB Footprint Design.................................................................................................................................................................................14
4. Audible Noise Suppression........................................................................................................................................................................15
5. Schematics, Bill of Materials (BOM), and Board Layout.............................................................................................................................16
6. Revision History..........................................................................................................................................................................................22
List of Figures
Figure 1. Schematic with Main Power Path (Orange) and Main (Noisy) AC Power Loops(Red).......................................................................3
Figure 2. Recommended Orientation for the P9235A-RB and Generic Placement Guide for Select Critical Components................................4
Figure 3. Actual Placement for the P9235A-RB EVK. Select Critical Components are circled in Yellow...........................................................5
Figure 4. P9235A-RB Physical Layout from P9235A-RB-EVK EvaluationBoard (2nd Layer (L1))....................................................................6
Figure 5. P9235A-RB Physical Layout from P9235A-RB-EVK EvaluationBoard (3rd Layer (L2)).....................................................................6
Figure 6. P9235A-RB Physical Layout from Demo PCBof Bottom Layer..........................................................................................................7
Figure 7. Resonance Capacitors........................................................................................................................................................................8
Figure 8. VIN, VCC5V, LDO33, LDO18, VBRG_IN, and DRV_VINPin Capacitors Placed Close to P9235A-RB with 0.1µF Placed Closest..9
Figure 9. P9235A-RB Typical GNDNoise Areas and Sensitive Circuit Placement..........................................................................................10
Figure 10. Boost Capacitors and Gate Drive Lines.............................................................................................................................................11
Figure 11. 5V Step Down Switching Regulator...................................................................................................................................................12
Figure 12. Flash Circuit.......................................................................................................................................................................................13
Figure 13. P9235A-RB Recommended PCB Land Pattern Drawing..................................................................................................................14
Figure 14. Application Schematic.......................................................................................................................................................................16
Figure 15. Silkscreen – Top of Board.................................................................................................................................................................19
Figure 16. Copper – Top Layer...........................................................................................................................................................................19
Figure 17. Copper L1 Layer................................................................................................................................................................................20
Figure 18. Copper L2 Layer................................................................................................................................................................................20
Figure 19. Copper Bottom..................................................................................................................................................................................21

P9235A-
RB Layout Guide
© 2019 Integrated Device Technology, Inc
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March 19, 2019
1. Introduction
The P9235A-RB Wireless Power Receiver (Tx) is an integrated circuit (IC) consisting of multiple high-power blocks and noise-sensitive
circuits controlled by a microprocessor. When implementing the application circuit on a printed circuit board (PCB), there are often tradeoffs
associated with managing the critical current paths. To optimize the design, place components on the circuit board based on circuit function to
guarantee best performance. The thermal management of the P9235A-RB is also important to the product’s performance and should be
optimized when designing the PCB. Use the following guidance to place the components in order of priority based on operation.
There are three main categoriesof circuitry:
Power circuits
Sensitive circuits
Non-sensitive circuits
Key Points for Optimal Layout
Route the power connectionswide and on the same side of the PCB as the P9235A-RB (≥ 100mils).
Use the layer under the P9235A-RB side of the board as a solid ground plane.
Connect the exposed thermal pad (EP) in the center of the P9235A-RB to all other layers withan array of 4x5 10 mil vias.
Avoid unnecessary layer transitions of the AC power connections (LC node, LC tank driving FETs, and GND).
Place the P9235A-RB as close as possible to thecenter of the board. Avoid placing it along the PCB edge.
Connect as much copper aspossible to every pin of the P9235A-RB, including pins that do not carry high current.
Use low ESR resonance capacitors (Cs/Cd) to decrease losses in the LC and AC1 current path(C0G preferred).
Place components in the following order:
•POWER CIRCUITS – NON H BRIDGE POWER STAGE:
CIN, CBOOST: Place all IC pin input voltage capacitors and boost capacitors close to their related pins (VIN, LDO33, LDO18,
VDDIO, BST_BRG1, BST_BRG2, DRV_ VIN, VBRG_IN:).
Buck Regulator L, Cout: Placethe inductor as close as possibleto the switch node pin to reduce the switching noise of that node.
Place the buck regulator inductance and output capacitance such that they formthe smallest possible current loop to minimize
EMI transmissions.
•SENSITIVE CIRCUITS – VOLTAGE AND CURRENT MEASUREMENT:
Current Sense: Place the bridgeinput current sense resistor directly in the current path to the tank FET drivers. Place thefiltering
components close to the sense resistor and tightly together.
Current Demodulation: Place the current demodulation circuit components tightlytogether and close to their related IC pins
(ISNS_OUT, IDEMI).
Voltage Demodulation: Place the voltage demodulation circuit components tightlytogether and close to their related IC pin
(VDEM1).
•POWER CIRCUITS – H BRIDGE POWER STAGE:
H Bridge: Place H bridge FETs (Q5, Q7) and LC tank capacitance (C44, C47, C48, C49) close to each other, to form a small current
loop, to avoid EMI emissions.
H Bridge Cin: Place the V_BRG FET-H-Bridge capacitors such that the traces are short. This isthe large DC and AC current path.
•SENSITIVE CIRCUITS – FET GATE DRIVER COMPONENTS:
Gate driver circuit: Place the Low Side FET Gate and HighSide Gate Rs close to their respective pins (GH_BRG1, 2, GL_BRG1, 2)
and connect the Output RC Snubbers directly onto their respective the H Bridge switch nodes.
Gate driver traces: Avoid running under the H Bridge switchnodes. Run these traces under the relatively quiet VBRGnode instead.
Place a ground layer betweenthese traces and the top signal level. Surround these traceswith the ground plane to provide a
tight loop AC signal return pathto avoid EMI noise.

P9235A-
RB Layout Guide
© 2019 Integrated Device Technology, Inc
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2. Tx Power Circuits
The main power circuit of the P9235A-RB device includes the current sense resistor, the four FETs of the H bridge resonant tank driver, and
the resonant tank. Secondary power circuits are the VCC5V, LDO33, and LDO18 regulators.
Figure 1. Schematic with Main Power Path (Orange) and Main (Noisy) AC Power Loops (Red)

P9235A-
RB Layout Guide
© 2019 Integrated Device Technology, Inc
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March 19, 2019
Figure 2. Recommended Orientation for the P9235A-RB and Generic Placement Guide for Select
Critical Components
CSP
CSN
VIN
Peak
Detector
VDEM1
Coil Assembly
P9235A-RB
SW_S
LDO33
LDO18
PREG
GPIOA6 LED1 LED2
VIN_LDO
R
SNS
GH_BRG1
SW_BRG1
GL_BRG1
GH_BRG2
SW_BRG2
GL_BRG2
MISO
MOSI
L
P
C
P
L
Ext.
Memory
Flash
1
SS
SCLK
Note:
1.External memory is required for the P9235A-RB.
SCL
SDA GND
GPIOA2
Recommendation: Once the final shape of the production or development PCB has been determined and the connection points for the power
transfer coil (LTX) have been chosen, place the P9235A-RB on the board as close to the center of the PCB as possible, taking into
consideration the mechanical requirements of the system under design. Determine its orientation based on the ability to route connections
and place the required components in the following order of priority. First place the input and boost capacitors as close to theirrespective pins
in this order of priority: VIN, LDO33, LDO18, BST_BRG1, BST_BRG2, DRV_VIN, and VBRG_IN. The main power current path the connection
from VIN through the sense resistor (RSNS), through 1 of the two half bridge power FETs, through the tank capacitor, through the Tx coil (Coil
Assembly) and out through 1 of the other half bridge power FETs. Figure 2 represents the optimal orientation of the P9235A-RB relative to the
other main components. Not allnecessary connections are shown in Figure 2. For a completediagram of the recommended connections, see
the schematic in Section 5. Trace widths are not to scale.

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RB Layout Guide
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Figure 3. Actual Placement for the P9235A-RB EVK. Select Critical Components are circled in Yellow
There are many things to take note of on this top layer with respect to creating an optimal layout (notes refer to the listing embedded in
Figure 3):
Closeness of CIN and Cboost caps to their respective pins (notes 1,6,15)
Tight (small) AC loops of FETs in relation to the LC tank (notes 9-12)
Tight loops of the FETs in relation to the H bridge Cin capacitors (notes 9,10)
Closeness of current and voltage demodulation to the IC (notes 5,13)
Closeness of H bridge FET gatedriver resistors to the IC (note 14)
Tight loop of LC of 5V switchingregulator for low loop inductance/noise(note 2)
Closeness of L to its respectiveswitching node for minimum noise(note 2)
The H bridge FETs produce themost heat. Therefore, FET GND pads are connected to GNDwith the maximum number of 10mil vias for
the best thermal performance.

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RB Layout Guide
© 2019 Integrated Device Technology, Inc
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Figure 4. P9235A-RB Physical Layout from P9235A-RB-EVK Evaluation Board (2nd Layer (L1))
Solid GND Plane with minimal connections, direct contact to GND plane 10mil vias for thermal transfer.
The ground layer (L1) is between the top layer signal plane and layer 3 (second middle layer - L2) gate drive signal layer below.
Figure 5. P9235A-RB Physical Layout from P9235A-RB-EVK Evaluation Board (3rd Layer (L2))
Gate driver traces under VIN, GND planes (quiet planes), thick power traces, and ground plane with minimal traces especially around the
P9235A-RB.
1
1
2
4
5
3

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RB Layout Guide
© 2019 Integrated Device Technology, Inc
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Routing of the FET gate driver lines away from switching nodes as much as possible (note 1). The traces are routed under the VIN and GND
planes (electrically quite areas). Also note the thick 30mil traces for the supply voltages (5V-note 2, 4; LDO33-note 5) and for the step down
switching regulator’s switch node (note 3). These thick traces prevent voltage drops when delivering the power, increasing reliability and
efficiency.
Figure 6. P9235A-RB Physical Layout from Demo PCB of Bottom Layer
GND Plane with Minimal Traces for Maximum Thermal Transfer
The outer layers of the PCB will be the most effective at transferring heat from the board to the ambient air or other objects. Spreading the
heat into internal layers is also effective for lowering the operating temperature. Internal layers can effectively spread heat horizontally when
they are not interrupted by traces and through-holes along their surface. An ideal layout will result in the entire PCB being close to the same
temperature; however, to obtain this result, ensure that all board layers have planes that are continuous and in direct contact with the
P9235A-RB thermal vias.
Select a single internal layer for routing most of the inner row/column pins to the rest of the PCB. The third layer is preferred for this purpose.
The required nodes for connecting heat spreading planes are GND, the VIN sources to the H bridge (V_BRIDGE, drain of Q2), and the switch
nodes (VLX1, VLX2). The other connections will spread heat due to natural thermodynamics, but the listed nodes contact the primary heat
sources of the P9235A-RB.

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RB Layout Guide
© 2019 Integrated Device Technology, Inc
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Resonance Capacitors
Next, place the resonance components. The C44, C47, C48, C49, and C51 capacitors should have wide copper planes connected to them
and be in-line from the P9235A-RB to the Tx coil. C0G capacitors will offer the highest performance and are recommended. X7R and X5R
can be substituted, but low-ESR components should be used. Since all the load current and the current required to transmit energy to the
receiver flows through the resonance capacitors, the heat developed within the resonance capacitors (Class II only) should be given
opportunity to spread into largecopper planes.
Figure 7. Resonance Capacitors

P9235A-
RB Layout Guide
© 2019 Integrated Device Technology, Inc
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VCC5V VIN, VCC5V, LDO33, LDO18, VBRG_IN, PE Circuit and DRV_VIN Pin
Capacitors
The VCC5V node, VIN, LDO33, LDO18, VBRG_IN, and DRV_VIN pin capacitors (C42, C50, C53, C34, C35) are used to stabilize internal
voltage supplies used for normal operation. These capacitors must be located close to the P9235A-RB. A 10µF decoupling capacitor is
recommended to be placed as close as possible to GND from the VIN, VCC5V, and DRV_VIN nodes. A 1µF decoupling capacitor is
recommended for LDO33 and LDO18 regulated output pins. A 0.1µF capacitor is also recommended in parallel with aforementioned
decoupling capacitor. This will reduce the ESR of the decoupling which will reduce noise at the pin. VBRG_IN requires a 0.1µF capacitor
only.
Figure 8. VIN, VCC5V, LDO33, LDO18, VBRG_IN, and DRV_VIN Pin Capacitors Placed Close to
P9235A-RB with 0.1µF Placed Closest
6
1:Cin(C42)
3:Cout,LDO33(C50)
4:Cout,LDO18(C53)
6:Cdrv,vin(C34,35)
1
3
4
6

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RB Layout Guide
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Sensitive Circuits
The term “sensitive circuits” refers to noise-sensitive circuits that should be referenced to GND in the “quiet” ground area. AC coupling, the
thermistor bypass capacitors, and other capacitors are for decoupling noise. The resonance nodes generate the highest harmonic noise,
which must be filtered with decoupling capacitor. Place the current sense circuitry, the voltage demodulation circuitry, and the current
demodulation circuitry, in quietground areas away from the resonance nodes.
Figure 9. P9235A-RB Typical GND Noise Areas and Sensitive Circuit Placement
8
13
12
11
sensitive
5:Isns,demod(C21,28,29,R28)
8:inputcurrentsense(R22,25,26,C37)
13:vsns demod(D2,R20,23,70,72,C18,19,20,69,70)
noise
11:tank resonantcaps(C44,47,48,49)
12:coil(L5)
5

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RB Layout Guide
© 2019 Integrated Device Technology, Inc
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Boost Capacitors and Gate Drive Lines
Place the boost capacitors (C38, C46) close to their respective pins for maximum transfer of the capacitive energies. Place the gate driver
resistors (R35, R40, R44, R47) close to their respective pins. This limits the switching noise generated. Place the FET gate bleed resistors
(R36, R42, R45, R48) close to their respective FET gate pad/pin.
Figure 10. Boost Capacitors and Gate Drive Lines
14:mosfetdriverresistor(R35,40,44,47)
15:Cboost(C38,46)
17:mosfetbleedingresistor(C36,42,45,48)
14
14
14
15
15
17
17

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RB Layout Guide
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5V Step Down Switching Regulator
Keep the switch node small by moving the inductor close to the switch node. This is only after placing all CIN capacitors as close to their
respective pins as possible. Make the L, COUT loop small to limit the loop inductance and related noise. Place the COUT such that the ground
end of the capacitor is close to the nearest ground pin (pin 6).
Figure 11. 5V Step Down Switching Regulator
35
2:L,Cout,buck(L4,C45)

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RB Layout Guide
© 2019 Integrated Device Technology, Inc
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Flash Circuit
In the flash programming application, P9235A-RB only contains the bootloader, the other program and data are stored into the flash. When
P9235A-RB works, it will fetch the instructions or data from flash frequently. Therefore, for keeping signal integrity and minimize the EMI, it’s
recommended that: 1) the trace of SS, SCLK, MOSI, and MISO should be as short as possible. 2) Place the trace of SS, SCLK, MOSI, and
MISO above or below the ground plane. 3) No bare pad is placed on the trace of SS, SCLK,MOSI, and MISO.
Figure 12. Flash Circuit

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RB Layout Guide
© 2019 Integrated Device Technology, Inc
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3. PCB Footprint Design
The P9235A-RB package is a fine-pitch 40-VFQFN device.
Figure 13. P9235A-RB Recommended PCB Land Pattern Drawing

P9235A-
RB Layout Guide
© 2019 Integrated Device Technology, Inc
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March 19, 2019
4. Audible Noise Suppression
Wireless power receiver solutions have been observed to produce audible noise. If sound is detected, there are several steps that can be
taken to reduce or eliminate the noise. The first priority is identifying the source (i.e., the rectifier capacitors, the Tx coil ferrite, communication
capacitors). Typically, the rectifier capacitors are the components that generate the audible noise. The reason the noise is present and
associated with the rectifier capacitors is due to the WPC communication signals being generated in the audible frequency range and the use
of small-form factor ceramic capacitors. The noise occurs due to the piezoelectric effect of ceramic capacitors. The capacitors constrict and
expand while providing the communication pulses, and this noise is amplified as it flexes thePCB.
The primary solution to this issue is to use low-acoustic noise capacitors. Alternatively, higher voltage rated components can have superior
piezoelectric properties that can reduce the audible noise. Additionally, placing the capacitors on both sides of the PCB (directly above and
below each other) counters the piezoelectric forces applied to the PCB (cancels the force by each capacitor). Another method is to add slots
through the PCB on both outer sides of the capacitors or directly under each capacitor. One additional approach is to place additional lower
capacitance value components in parallel to reduce the mechanical force of the piezoelectric effect per component.
For any additional questions, contact IDT technical support (see last page for contact information.

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RB Layout Guide
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5. Schematics, Bill of Materials (BOM), and Board Layout
Figure 14. Application Schematic
C27 NP
SCL
SCLK
R72 10k 0402
LED_PATT/FOD_ADJ
R31 NP
R2 0 1206
R40 22 0402
VBRIDGE
C24 NP 10V 0603
IDEM
VSNS_IN1
LDO33
C70 5.6nF 25V 0603
R47 22 0402
C76 NP
VDEM1
R70 47K 0402
CSP
VIN_SEL
FOD_ADJ
C20 680pF 10V 0402
LDO18
C18 22nF 25V 0402
GPIOA6
R27 NP
LED2
D2 BAV21WS SOD-323
VCC_5V
LED1 2 1
C30 0.1uF 10V 0402
C26 NP
LDO33
R26 0.02 0805
THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY TO Integrated Device Technology, Inc. (IDT). USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION OF AN OFFICER OF IDT IS EXPRESSLY FORBIDDEN
C43 1uF 10V
0603
D3
NP
C7 10uF 10V 0603
BRG1_HG
TS
U7
W25X40CLUXIG
CS#
1
DO
2
WP#
3
GND
4DI 5
CLK 6
HLD# 7
VCC 8
EPAD
9
TS
SDA
SW_BRG1
Q7
AM7930N
2
3
4
6
5 1
SW_BRG1
GND4
MISO
R23 200K 0402
C3 NP 10V 0402
R9 0 1206
R59 NP
VIN
SW_BRG2
MISO
SW_BRG2
C8 0.1uF 10V 0402
GND1
L5 NP
LDO33
R35 22 0402
C56 10uF 10V 0603
C37 1uF 10V 0603
VIN
SW_BRG1
Vcoil
R52 5.1k 0402
C44 100nF 50V
1206
LDO33
Vsns
C66 0.1uF 10V 0402
LDO33
SCLK
R57
100K
0402
R60 10k 0402
SCL
Only use COG caps
C69 22nF 16V 0402
VCC_5V SW_BRG2
R77 NP
C29 680pF 10V 0402
OPTIONAL
FOD_ADJ
VCC5V
USB-MICRO CONNECTOR
R76 10k 0402
VCC_5V
Vsns
VCOIL
GND
SS
C81 NP 10V 0603
LED_PATT
R25 10 0402
C35 10uF 10V 0603
R36 100K 0402
BRG2_HG
SCL
R22 10 0402
VIN
LED_PATT
MOSI
C51 NP
C34 0.1uF 10V 0402
GND_SEL
SDA
C42 10uF 10V 0603
C21 22nF 16V 0402
C46
0.1uF 10V
0402
C47 100nF 50V
1206
FOD_ADJ
C19 5.6nF 25V 0603
C67 0.1uF 10V 0402
SDA
MOSI
P9235A-RB
U3
EN
1
GND
2
PREG
3
VIN
4
SW_S
5
GND1
6
LDO33
7
VIN_LDO
8
LDO18
9
LED1
10
LED2
11
VDDIO
12
SS
20
SCLK 21
MISO 22 MOSI 23
GH_BRG2 24
BST_BRG2 25
SW_BRG2 26
GL_BRG2 27
GND2 28
GL_BRG1 29
SW_BRG1 30
EP
41
BST_ BRG1 31
GH_BRG1 32
DRV_VIN 33
VBRG_IN 34
GND3 35
VDEM1 36
IDEMI 37
ISNS_OUT 38
CSN 39
CSP 40
SCL
13
SDA
14
GPIOA2
15
GPIOA3
16
GPIOA4
17
GPIOA5
18
GPIOA6
19
SS
CSP
MISO
RED
t
TH_Coil1
0603 10K
GND2
R34
NP
C45 10uF 10V 0603
SCLK
SS
D-
CSN
CSN
R43 1K 0402
R61 10k 0402
D+
C48 100nF 50V
1206
VIN_SEL
SLD SLD
VCC
D-
D+
ID
GND
J11
usb_micro_ab
1 2 3 4 56
7 8 9
10 11
LED2 2 1
R44 22 0402
TS
MOSI
COIL TEMPERATURE SENSING
BRG2_LG
C32 10uF 10V 0603
R45 100K 0402
Title Size Document Number Rev
Date: Sheet of
0.0
P9235A-RB DEVELOPEMENT BOARD V1P1
Custom
1 1Thursday, February 14, 2019
R48
100K
0402
LDO33
LDO33
Vcoil
C50 1uF 6.3V 0603
C68 0.1uF 10V 0402
L1
NP
1 2 3
4
BRG1_LG
C77 NP
R20 2.4K 0603
C28 56pF 50V 0402
R62 NP
C55 10uF 10V 0603
C38 0.1uF 10V 0402
R50 5.1k 0402
R30
NP
C2 NP 10V 0603
R42
100K
0402
GPIOA6
VDEM1
R39 0 0402
C59 22nF 16V 0603 R49 0 0402
CSN
C57 0.1uF 10V 0402
C53 1uF 6.3V 0603
LDO18
SW_BRG2
J4
Prog Conn
11 22 33
44 55
FOR DEVELOPMENT ONLY
R41 1K 0402
LDO33
Vcoil
C39 22nF 16V 0603
LDO33
LDO33
C49 100nF 50V
1206
SDA
C33 0.1uF 10V 0402
C31 10uF 10V 0603
GREEN R46
680 0402
R16 NP
R58 10k 0402
R28 10k 0402
LX1
SW_BRG1
R29
NP
CSP
GND3
LED1
LED_PATT
C36 NP
Q5
AM7930N
2
3
4
6 5 1
SCL
L4 4.7uH 0603
P9235A-RB DEVELOPEMENT BOARD V1P1

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Table 1. Application Board Bill of Materials (BOM)
Item Quantity Reference Part Description Part Number PCB
Footprint
1 8 C7,C31,C32,C35,
C42,C45,C55,C56 10µF CAP CER 10µF 10V X5R 0603 GRM188R61A106KE69D 603
2 10 C8,C30,C33,C34,
C38,C46,C57,C66,
C67,C68
0.1µF CAP CER 0.1µF 10V X7R 0402 GRM155R71A104KA01D 402
3 1 C18 22nF CAP CER 0.022µF 25V X5R 0402 GCM155R71E223KA55J 402
4 2 C19,C70 5.6nF CAP CER 5600pF 25V X7R 0603 GRM188R71E562KA01D 603
5 2 C20,C29 680pF CAP CER 680pF 10V X7R 0402 8.85012E+11 402
6 2 C21,C69 22nF CAP CER 0.022µF 16V X5R 0402 GRM155R61C223KA01D 402
7 1 C28 56pF CAP CER 56pF 50V C0G/NP0 0402 GRM1555C1H560FA01D 402
8 2 C37,C43 1µF CAP CER 1µF 10V X5R 0603 GRM188R61A105KA61D 603
9 2 C39,C59 47nF CAP CER 0.047µF 16V X7R 0603 GRM188R71C473KA01D 603
10 4 C44,C47,C48,C49 100nF CAP CER 0.1µF 50V C0G/NP0 1206 GRM31C5C1H104JA01L 1206
11 2 C50,C53 1µF CAP CER 1µF 6.3V X5R 0603 GRM188R61A105KA61D 603
12 1 D2 BAV21
WS DIODE GEN PURP 200V 200MA SOD323 BAV21WS-7-F SOD-323
13 7 GND1,GND2,GND3,
GND4,VIN_SEL,
VIN,GND
TP TEST POINT PC MINIATURE SMT 5015 test_pt_sm
_135x70
14 1 J4 Prog
Conn BERGSTIK II .100" SR STRAIGHT 68000-105HLF sip5
15 1 J11 5P CON 005 F RA OTH PC NLK SRW 800
MINIUSB 90080004 usb_micro _ab
16 1 LED1 LED LED RED CLEAR 0603 SMD 150060RS75000 603
17 1 LED2 LED LED GREEN CLEAR 0603 SMD 150060GS75000 603
18 1 L4 4.7µH FIXED IND 4.7µH 620MA 550 MOHM LQM18PN4R7MFRL 603
19 1 L5 NP
20 2 Q5,Q7 AM793
0N Dual N-Channel 30-V (D-S) MOSFET AM7930N DFN-5X6- 8Ld-N1
21 2 R2,R9 0 RES SMD 0ΩJUMPER 1/4W 1206 RC1206JR-070RL 1206
22 1 R20 2.4K RES SMD 2.4kΩ1% 1/10W 0603 RC0603FR-072K4L 603
23 2 R22,R25 10 RES SMD 10Ω0.5% 1/16W 0402 RT0402DRE0710RL 402
24 1 R23 200K RES SMD 200kΩ1%1/10W 0402 ERJ-2RKF2003X 402
25 1 R26 0.02 RES 0.02Ω1% 1/8W 0805 PF0805FRM7P0R02L 805
26 6 R28,R58,R60,R6,
R72,R76 10k RES SMD 10kΩ1% 1/16W 0402 RC0402FR-0710KL 402

P9235A-
RB Layout Guide
© 2019 Integrated Device Technology, Inc
18
March 19, 2019
Item Quantity Reference Part Description Part Number PCB
Footprint
27 4 R35,R40,R44,R47 22 RES SMD 22Ω1% 1/10W 0402 RC1005F220CS 402
28 5 R36,R42,R45,R48,
R57 100K RES SMD 100kΩ1% 1/16W 0402 RC0402FR-07100KL 402
29 2 R39,R49 0 RES SMD 0ΩJUMPER 1/16W 0402 RC0402JR-070RP 402
30 2 R41,R43 1K RES SMD 1kΩ5% 1/16W 0402 RC0402JR-071KL 402
31 1 R46 680 RES SMD 680Ω5% 1/16W 0402 RC0402JR-07680RL 402
32 2 R50,R52 5.1k RES SMD 5.1kΩ5% 1/16W 0402 RC0402JR-075K1L 402
33 1 R70 47K RES SMD 47kΩ1% 1/16W 0402 RC0402FR-0747KL 402
34 1 TH_Coil1 10K NTC THERMISTOR 10kΩ1% 0603 ERT-J1VG103FA 603
35 1 U3 P9235
A-RB IC wireless power transmitter P9235A-RB qfn40_5x5 _N
36 1 U7 W25X4
0CLUX
IG
IC FLASH 4MBIT 104MHZ 8USON W25X40CLUXIG TR uson_2x3_
8LD

P9235A-
RB Layout Guide
© 2019 Integrated Device Technology, Inc
19
March 19, 2019
Figure 15. Silkscreen – Top of Board
Figure 16. Copper – Top Layer

P9235A-
RB Layout Guide
© 2019 Integrated Device Technology, Inc
20
March 19, 2019
Figure 17. Copper L1 Layer
Figure 18. Copper L2 Layer