Renesas IDT 89EBPES48H12G2 User manual

®
May 2009
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: [phone] • [phone] • FAX: [phone]
Printed in U.S.A.
©2009 Integrated Device Technology, Inc.
IDT®89EBPES48H12G2
Evaluation Board Manual
(Eval Board: 18-677-000)

DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.
Boards that fail to function should be returned to IDT for replacement. Credit will not be given for the failed boards nor will a
Failure Analysis be performed.
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Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to
such intended use is executed between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform,
when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device
or system, or to affect its safety or effectiveness.
IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc.

Notes
EB48H12G2 Eval Board Manual i May 7, 2009
Table of Contents
®
Description of the EB48H12G2 Eval Board
Introduction .....................................................................................................................................1-1
Board Features ...............................................................................................................................1-2
Hardware ................................................................................................................................1-2
Software..................................................................................................................................1-2
Other.......................................................................................................................................1-2
Revision History..............................................................................................................................1-2
Installation of the EB48H12G2 Eval Board
EB48H12G2 Installation..................................................................................................................2-1
Hardware Description .....................................................................................................................2-1
Reference Clocks............................................................................................................................2-1
Power Sources................................................................................................................................2-2
External Power Source...........................................................................................................2-2
PCI Express Analog High Power Voltage Converter..............................................................2-2
PCI Express Analog Power Voltage Converter ......................................................................2-2
PCI Express Transmitter Analog Voltage Converter ..............................................................2-2
Core Logic Voltage Converter ................................................................................................2-2
2.5V I/O Voltage Regulator.....................................................................................................2-3
Power-up Sequence for PES48H12G2 (PCIe Gen2 device).................................................. 2-3
Power-up Sequence for PES48H12 (PCIe Gen1 device).......................................................2-3
Reset ......................................................................................................................................2-3
Fundamental Reset ................................................................................................................2-3
Downstream Reset .................................................................................................................2-3
Boot Configuration Vector...............................................................................................................2-4
SMBus Interfaces............................................................................................................................2-5
SMBus Slave Interface ...........................................................................................................2-5
SMBus Master Interface .........................................................................................................2-6
JTAG Header.................................................................................................................................. 2-6
Attention Buttons.............................................................................................................................2-6
Miscellaneous Jumpers, Headers................................................................................................... 2-7
LEDs ...............................................................................................................................................2-8
PCI Express Connectors.................................................................................................................2-9
EB48H12G2 Board Figure............................................................................................................2-11
Software for the EB48H12G2 Eval Board
Introduction .....................................................................................................................................3-1
Device Management Software........................................................................................................3-1
Schematics
Schematics .....................................................................................................................................4-1

IDT Table of Contents
EB48H12G2 Eval Board Manual ii May 7, 2009
Notes

Notes
EB48H12G2 Eval Board Manual iii May 7, 2009
List of Tables
®
Table 2.1 Clock Source Selection .......................................................................................................2-1
Table 2.2 SMA Connectors - Onboard Reference Clock ....................................................................2-2
Table 2.3 External Power Connector - J4 ...........................................................................................2-2
Table 2.4 Downstream Reset Selection .............................................................................................2-4
Table 2.5 Boot Configuration Vector Signals ......................................................................................2-4
Table 2.6 Boot Configuration Vector Switches S3 & S13 (ON=0, OFF=1) .........................................2-5
Table 2.7 Slave SMBus Interface Connector ......................................................................................2-5
Table 2.8 JTAG Connector Pin Out ....................................................................................................2-6
Table 2.9 Attention Buttons ................................................................................................................2-6
Table 2.10 Miscellaneous Jumpers, Headers .......................................................................................2-7
Table 2.11 LED Indicators ....................................................................................................................2-8
Table 2.12 PCI Express x8 Connector Pinout ......................................................................................2-9

IDT List of Tables
EB48H12G2 Eval Board Manual iv May 7, 2009
Notes

Notes
EB48H12G2 Eval Board Manual v May 7, 2009
List of Figures
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Figure 1.1 Function Block Diagram of the EB48H12G2 Eval Board ...................................................1-1

IDT List of Figures
EB48H12G2 Eval Board Manual vi May 7, 2009
Notes

Notes
EB48H12G2 Eval Board Manual 1 - 1 May 7, 2009
®
Chapter 1
Description of the
EB48H12G2 Eval Board
Introduction
The 89HPES48H12G2 switch (also referred to as PES48H12G2 in this manual) is a member of IDT’s
PCI Express® standard based line of products. It is a PCIe® Base Specification 2.0 compliant (Gen2) 12-
port switch. There are twelve x4 lanes ports. Two x4 ports can be merged to form one x8 port in
PES48H12G2. One upstream port is provided for connecting to the root complex (RC), and up to eleven
downstream ports are available for connecting to PCIe endpoints or to another switch. More information on
this device can be found in the 89HPES48H12G2 User Manual.
The 89EBPES48H12G2 Evaluation Board (also referred to as EB48H12G2 in this manual) provides an
evaluation platform for the PES48H12G2 switch. It is also a cost effective way to add PCIe ports (slots) to
an existing system with limited number of PCIe ports/slots. The EB48H12G2 board is designed to function
as an add-on card to be plugged into a x8 PCIe slot available on a motherboard hosting an appropriate root
complex and microprocessor(s). The EB48H12G2 is a vehicle to test and evaluate the functionality of the
PES48H12G2 switch. It is also designed to work with the PES48H12 (Gen 1) switch. Refer to application
note AN-550 for detail information on Designing Gen2-Ready boards for IDT’s 48-lane, 12-port PCIe
Switches. Customers can use this board to get a headstart on software development prior to the arrival of
their own hardware. The EB48H12G2 is also used by IDT to reproduce system-level hardware or software
issues reported by customers. Figure 1.1 illustrates the functional block diagram representing the main
parts of the EB48H12G2 board.
Figure 1.1 Function Block Diagram of the EB48H12G2 Eval Board
JTAG
Header
Main
Reset
I/O Expander
MAX7311
PCIe x8 Upstream Edge
EEPROM
24LC512
SMBUS
HEADER
PES48H12G2
PCI Express
Switch
External Power
PCIe x8 Downstream Slot
PCIe x8 Downstream Slot
x8
25 MHz Crystal
Clock
Generator
Clock
Fanout
SMBus
PCIe x8 Downstream Slot
Voltages on board
+12V, +3.3V, +2.5V, +1.0V
Connector
Power
Module
PTH08T240
x8
x4
x8
Port 4
Port 6
Port 8
Port 0 PCIe x8 Downstream Slot
Port 2 x8

IDT Description of the EB48H12G2 Eval Board
EB48H12G2 Eval Board Manual 1 - 2 May 7, 2009
Notes Board Features
Hardware
PES48H12G2 PCIe Gen2 switch
– Up to twelve x4 or six x8 ports - 48 PCIe lanes
– PCIe Base Specification Revision 2.0 compliant (Gen2 SerDes speeds of 5 GT/S)
– Up to 2048 byte maximum Payload Size
– Automatic lane reversal and polarity inversion supported on all lanes
– Automatic per port link width negotiation to x8, x4, x2, x1
– Load configuration from an optional serial EEPROM via SMBUS
Upstream, Downstream Port
– One edge connector on the upstream port, to be plugged into a slot with at least x8 capable on a
host motherboard
– Four slot connectors on the downstream ports, for PCIe endpoint add-on cards to be plugged in.
These slot connectors are x8 mechanically and electrically connected as three x8 and one x4, but
open-ended for card widths greater than x8 (e.g. x16).
Numerous user selectable configurations set using onboard jumpers and DIP-switches
– Source of clock - host clock or onboard clock generator
– Two clock rates (100/125 MHz) from an onboard clock generator
– Boot mode selection
SMBUS Slave Interface (4 pin header)
SMBUS Master Interface connected to the Serial EEPROMs through I/O expander
“Attention” button for each downstream port to initiate a hot swap event on each port
Four pin connector for optional external power supply
Push button for Warm Reset
Several LEDs to display status, reset, power, “Attention”, etc.
One 10-pin JTAG connector (pitch 2.54 mm x 2.54 mm)
Software
There is no software or firmware executed on the board. However, useful software is provided along
with the Evaluation Board to facilitate configuration and evaluation of the PES48H12G2 within host systems
running popular operating systems.
Installation programs
– Operating Systems Supported: Windows Server 2003, Windows Server 2008, WindowsXP, Vista,
Linux
GUI based application for Windows and Linux
– Allows users to view and modify registers in the PES48H12G2
– Binary file generator for programming the serial EEPROMs attached to the SMBUS.
Other
A metal bracket is provided to firmly hold in place three endpoints plugged into the EB48H12G2
board.
An external power supply may be required under some conditions.
SMBUS cable may be required for certain evaluation exercises.
SMA connectors are provided on the EB48H12G2 board for clock outputs.
Revision History
January 5, 2009: Initial publication of eval board manual.

IDT Description of the EB48H12G2 Eval Board
EB48H12G2 Eval Board Manual 1 - 3 a
Notes May 7, 2009: On page 2-2, changed reference to 25MHz oscillator (Y1) to (X1). In PCI Express Analog
Power Voltage Converter section, changed DC-DC Converter (U4) to (U14). In PCI Express Transmitter
Analog Power Voltage Converter section, changed DC-DC converter (U14) to (U4). In the SMBus Slave
Interface section of Chapter 2, the slave interface default address was changed to 0b1110111. In Table 2.6,
signal S3[1] was changed from ON to OFF. In Table 2.11, locations were changed for the following signals:
port 4: power-is-good; port 6 power-is-good; port 4: power indicator; port 6: power indicator; port 4: attention
indicator; port 6: attention indicator.

IDT Description of the EB48H12G2 Eval Board
EB48H12G2 Eval Board Manual 1 - 4 May 7, 2009
Notes

Notes
EB48H12G2 Eval Board Manual 2 - 1 May 7, 2009
®
Chapter 2
Installation of the
EB48H12G2 Eval Board
EB48H12G2 Installation
This chapter discusses the steps required to configure and install the EB48H12G2 evaluation board. All
available DIP switches and jumper configurations are explained in detail.
The primary installation steps are:
1. Configure jumper/switch options suitable for the evaluation or application requirements.
2. Connect PCI Express endpoint cards to the downstream port PCIe slots on the evaluation board.
3. Make sure that the host system (motherboard with root complex chipset) is powered off.
4. Insert the evaluation board into the host system.
5. Apply power to the host system.
The EB48H12G2 board is typically shipped with all jumpers and switches configured to their default
settings. In most cases, the board does not require further modification or setup.
Hardware Description
The PES48H12G2 is a 48-lane, 12-port PCI Express® switch. It is a peripheral chip that performs PCI
Express based switching with a feature set optimized for high performance applications such as servers
and storage. It provides switching functions between a PCI Express upstream port and downstream ports or
peer-to-peer switching between downstream ports.
The EB48H12G2 has four PCI Express downstream ports, accessible through four x8 connectors.
Three ports are capable of negotiating a x1, x2, x4 and x8 link width and one port is capable of negotiating
a x1, x2, or x4 link width. All endpoint cards connected to the PES48H12G2 must support one of these link
widths.
Basic requirements for the board to run are:
–Host system with a PCI Express root complex supporting at least x8 configuration through a PCI
Express x8 or larger slot.
–x1, x2, x4 or x8 PCI Express Endpoint Cards.
Reference Clocks
The PES48H12G2 requires two differential reference clocks while the PES48H12 requires four. Also,
AC coupling is not required on the PES48H12G2’s reference input clocks, therefore capacitors C348,
C350, C352, and C354 need to be removed and capacitors C347, C349, C351, and C353 should be
replaced with 0 ohm resistors when the Gen2 part is installed. The EB48H12G2 derives these clocks from a
common source which is user-selectable. The common source can be either the host system’s reference
clock or it can be the onboard clock generator. Selection is made by stuffing resistors as in Table 2.1.
Clock Configuration Stuffing Option
W6 and W7 Clock Source
Pins 2 and 3 Onboard Reference Clock – Use onboard clock generator
Pins 1 and 2 Upstream Reference Clock – Host system provides clock (Default)
Table 2.1 Clock Source Selection

IDT Installation of the EB48H12G2 Eval Board
EB48H12G2 Eval Board Manual 2 - 2 May 7, 2009
Notes The source for the onboard clock is the ICS841484 clock generator device (U10) connected to a 25MHz
oscillator (X1). When using the onboard clock generator, the output frequency is fixed at 100MHz, therefore
FSEL0 (S2, pin 2) should be in the ON position as the default setting.
The outputs of the onboard clock generator and clock buffer (ICS9DB803) are accessible through two
SMA connectors located on the Evaluation Board. See Table 2.2. This can be used to connect a scope for
probing or capturing purposes and cannot be used to drive the clock from an external source.
Power Sources
The EB48H12G2 and all downstream ports are powered from the upstream port slot power. If add-in
cards require more power than the upstream slot can support, an external source is required to supply this
extra power via an auxiliary 4-pin power connector on the board. Header W1, W2, and W3 (see Table 2.10)
are used to select proper power source for the switch and all downstream ports.
External Power Source
If necessary, external power is supplied to the EB48H12G2 board through a 4-pin auxiliary power
connector attached to J4. The external power supply provides +12V to the EB48H12G2 as described in
Table 2.3. The +5V is unused.
PCI Express Analog High Power Voltage Converter
A DC-DC converter (U5) provides a 2.5V PCI Express analog high power voltage (shown as VDDPEHA)
to the PES48H12G2. Install R224 (56 ohm resistor) to provide a 1.5V PCI Express serial data transmit
termination voltage (shown as VTTPE) when the PES48H12 is installed.
PCI Express Analog Power Voltage Converter
A separate DC-DC converter (U14) provides a 1.0V PCI Express analog power voltage (shown as
VDDPEA) to the PES48H12G2.
PCI Express Transmitter Analog Voltage Converter
A separate DC-DC converter (U4) provides a 1.0V PCI Express transmitter analog voltage (shown as
VDDPETA) to the PES48H12G2.
Core Logic Voltage Converter
A separate DC-DC converter (U3) provides the 1.0V core voltage (VDDCORE) to the PES48H12G2.
Onboard Reference Clock Output (Differential) – J7, J9, J10-J15
J7, J9, J12, J14 Positive Reference Clock
J10, J11, J13, J15 Negative Reference Clock
Table 2.2 SMA Connectors - Onboard Reference Clock
Pin Signal
1+12V
2GND
3GND
4+5V
Table 2.3 External Power Connector - J4

IDT Installation of the EB48H12G2 Eval Board
EB48H12G2 Eval Board Manual 2 - 3 May 7, 2009
Notes 2.5V I/O Voltage Regulator
This evaluation board can be stuffed to host the PES48H12G2 (PCIe Gen2) device or the PES48H12
(PCIe Gen1) device. Depending on which device is populated on the board, appropriate settings can be
made. A 12V to 3.3V voltage regulator (VR2) provides the 2.5V I/O voltage (VDDI/O) to the PES48H12G2.
Install R145 (2.49 ohm) to provide the 3.3V I/O voltage when the PES48H12 is installed instead.
Power-up Sequence for PES48H12G2 (PCIe Gen2 device)
During power supply ramp-up, VDDCORE must remain at least 1.0V below VDDI/O at all times. There
are no other power-up sequence requirements for the various operating supply voltages.
Power-up Sequence for PES48H12 (PCIe Gen1 device)
The power -up sequence must be as following:
1. VDDI/O — 3.3V
2. VDDCORE, VDDPE, VDDAPE — 1.0V
3. VTTPE — 1.5V
When powering up, each voltage level must ramp up and stabilize prior to applying the next voltage in
the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations
between sequential valid power level requirements.
Reset
The PES48H12G2 supports two types of reset mechanisms as described in the PCI Express specifica-
tion:
–Fundamental Reset: This is a system-generated reset that propagates along the PCI Express tree
through a single side-band signal PERST# which is connected to the Root Complex, the
PES48H12G2, and the endpoints.
–Hot Reset: This is an In-band Reset, communicated downstream via a link from one device to
another. Hot Reset may be initiated by software. This is further discussed in the PES48H12G2
User Manual. The EB48H12G2 evaluation board provides seamless support for Hot Reset.
Fundamental Reset
There are two types of Fundamental Resets which may occur on the EB48H12G2 evaluation board:
–Cold Reset: During initial power-on, the onboard voltage monitor (TLC7733D) will assert the PCI
Express Reset (PERSTN) input pin of the PES48H12G2.
–Warm Reset: This is triggered by hardware while the device is powered on. Warm Reset can be
initiated by two methods:
•Pressing a push-button switch (S1) located on EB48H12G2 board
•The host system board IO Controller Hub asserting PERST# signal, which propagates through
the PCIe upstream edge connector of the EB48H12G2. Note that one can bypass the onboard
voltage monitor (TLC7733D) by moving the shunt from pin 1-2 to pin 2-3 (default) on W4.
Both events cause the onboard voltage monitor (TLC7733D) to assert the PCI Express Reset
(PERSTN) input of the PES48H12G2 while power is on.
Downstream Reset
The PES48H12G2 provides a a choice of either a software-controlled reset for each downstream port
through GPIO pins or a fundamental reset through PERST#. Selection is made by jumpers described in
Table 2.4.

IDT Installation of the EB48H12G2 Eval Board
EB48H12G2 Eval Board Manual 2 - 4 May 7, 2009
Notes
Boot Configuration Vector
A boot configuration vector consisting of the signals listed in Table 2.5 is sampled by the PES48H12G2
during a fundamental reset (while PERSTN is active). The boot configuration vector defines the essential
parameters for switch operation and is set using DIP switches S3 and S13 as defined in Table 2.6.
Port # Jumper Selection
2 W9 [1-2] Software controlled reset through I/O Expander 0
[2-3] Fundamental reset PERST# (default)
4 W5 [1-2] Software controlled reset through I/O Expander 2
[2-3] Fundamental reset PERST# (default)
6 W19 [1-2] Software controlled reset through I/O Expander 2
[2-3] Fundamental reset PERST# (default)
8 W8 [1-2] Software controlled reset through I/O Expander 4
[2-3] Fundamental reset PERST# (default)
Table 2.4 Downstream Reset Selection
Signal Description
CCLKDS Common Clock Downstream (for 48H12). The assertion of this pin indicates that all
downstream ports are using the same clock source as that provided to downstream
devices. This pin is used as the initial value of the Slot Clock Configuration bit in all of the
Link Status Registers for downstream ports. The value may be overridden by modifying the
SCLK bit in the downstream port’s PCIELSTS register. Default: 0x1
CCLKUS Common Clock Upstream (for PES48H12). The assertion of this pin indicates that the
upstream port is using the same clock source as the upstream device. This pin is used as
the initial value of the Slot Clock Configuration bit in the Link Status Register for the
upstream port. The value may be overridden by modifying the SCLK bit in the
P0_PCIELSTS register. Default: 0x1
CLKMODE[2:0] Initial Port Clocking mode (for PES48H12G2). Default: 0x0
0x0 - Global Clock mode on all ports. Port0/2/4/8 SCLK = 0
0x1 - Global Clock mode on all ports. Port0 SCLK =1, Port2 SCLK =0, Port4/8 SCLK =0
0x2 - Global Clock mode on all ports. Port0 SCLK =0, Port2 SCLK =1, Port4/8 SCLK =1
0x3 - Global Clock mode on all ports. Port0 SCLK =1, Port2 SCLK =1, Port4/8 SCLK =1
0x4 - Local Clock mode on Port0/1. Port0 SCLK =1, Port2 SCLK =1, Port4/8 SCLK =1
0x5 - Global Clock mode on Port0, Local Clock mode on Port1, Port0 SCLK =0, Port2
SCLK =1, Port4/8 SCLK =1
0x6 - Global Clock mode on Port0, Local Clock mode on Port1, Port0 SCLK =1, Port2
SCLK =1, Port4/8 SCLK =1
0x7 - Reserved
SWMODE[3:0] Switch Mode. These configuration pins determine the PES48H12G2 switch operating
mode. Default: 0x0
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM-based initialization
0x2 through 0xF - Reserved
Table 2.5 Boot Configuration Vector Signals

IDT Installation of the EB48H12G2 Eval Board
EB48H12G2 Eval Board Manual 2 - 5 May 7, 2009
Notes
SMBus Interfaces
The System Management Bus (SMBus) is a two-wire interface through which various system compo-
nent chips can communicate. It is based on the principles of operation of I2C. Implementation of the SMBus
signals in the PCI Express connector is optional and may not be present on the host system. The SMBus
interface consists of an SMBus clock pin and an SMBus data pin.
The PES48H12G2 contains two SMBus interfaces: a slave SMBus interface and a master SMBus inter-
face. The slave SMBus interface allows a SMBus Master device full access to all software-visible registers.
The Master SMBus interface provides connection to the external serial EEPROM used for initialization and
the I/O expanders used for hot-plug signals.
SMBus Slave Interface
On the PES48H12G2 board, the slave SMBus interface is accessible through the PCI Express edge
connector as well as a 4-pin header as described in Table 2.7.
Note: The SMBus signals to the PCI Express edge connector is disabled by default. To enable
them, place 0-ohm resistors at locations R160 and R161.
.
A fixed slave SMBus address specified by the SSMBADDR[5,2:1] pins is used. For a fixed address, the
SMBus address of the PES48H12G2 slave interface is 0b1110111 by default.
The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master.
Initiation of any SMBus transaction other than those listed above produces undefined results. See the
SMBus 2.0 specification for a detailed description of the following transactions:
–Byte and Word Write/Read
–Block Write/Read
Signal Description Default
S13[1] CLKMODE2 OFF
S13[2] CLKMODE1/CCLKDS OFF
S13[3] CLKMODE0/CCLKUS OFF
S3[1] SWMODE[0] OFF
S3[2] SWMODE[1] ON
S3[3] SWMODE[2] ON
S3[4] SWMODE[3] ON
Table 2.6 Boot Configuration Vector Switches S3 & S13 (ON=0, OFF=1)
Slave SMBus Interface Connector J8
Pin Signal
1N/C
2SCL
3GND
4SDA
Table 2.7 Slave SMBus Interface Connector

IDT Installation of the EB48H12G2 Eval Board
EB48H12G2 Eval Board Manual 2 - 6 May 7, 2009
Notes SMBus Master Interface
Connected to the master SMBus interface are seven 16-bit I/O Expanders (MAX7311) and a serial
EEPROM (24LC512). Six I/O Expanders are used as the interface for the onboard hot-plug controllers
(MIC2591B). The SMbus address for the I/O Expander0/2/4/8/12/13 are fixed as 0x20, 0x24, 0x22, 0x26,
0x28, 0x2A and 0x2C, respectively.
Note: Hot-plug is not implemented when PES48H12 is installed.
The seven bits address for the selected EEPROM device is fixed at 0b1010_000 by default.
JTAG Header
The PES48H12G2 provides a JTAG connector J5 for access to the PES48H12G2 JTAG interface. The
connector is a 2.54 x 2.54 mm pitch male 10-pin connector. Refer to Table 2.8 for the JTAG Connector J5
pin out.
Attention Buttons
The PES48H12G2 features three attention buttons, shown in Table 2.9. Each button corresponds to a
particular port and is used to initiate hot-swapping events.
JTAG Connector J5
Pin Signal Direction Pin Signal Direction
1 /TRST - Test reset Input 2 GND —
3 TDI - Test data Input 4 GND —
5 TDO - Test data Output 6 GND —
7 TMS - Test mode select Input 8 GND —
9 TCK - Test clock Input 10 GND —
Table 2.8 JTAG Connector Pin Out
Button Description
S7 Port 2 Attention Button
S12 Port 4 Attention Button
S6 Port 6 Attention Button
S11 Port 8 Attention Button
Table 2.9 Attention Buttons

IDT Installation of the EB48H12G2 Eval Board
EB48H12G2 Eval Board Manual 2 - 7 May 7, 2009
Notes Miscellaneous Jumpers, Headers
Miscellaneous Jumpers, Headers
Ref.
Designator Type Default Description
W1-W3 Header 1-2 Shunted 1-2: 12.0V source from Upstream Port (Default)
2-3: 12.0V source from external power connector
W38 Header Shunted Disable EEPROM Write protect feature (Default)
S9[1] Switch ON ON: Port2, Force hot-plug controller on (Default)
OFF: Port2, Power Enable bit controls hot-plug controller
S10[1] Switch ON ON: Port4, Force hot-plug controller on (Default)
OFF: Port4, Power Enable bit controls hot-plug controller
S10[2] Switch ON ON: Port6, Force hot-plug controller on (Default)
OFF: Port6, Power Enable bit controls hot-plug controller
S9[2] Switch ON ON: Port8, Force hot-plug controller on (Default)
OFF: Port8, Power Enable bit controls hot-plug controller
W45 Header 2-3 Shunted 2-3: Port 2, +12V source from Upstream port (Default)
1-2: Port 2, +12V source from hot-plug controller
W51 Header 2-3 Shunted 2-3: Port 4, +12V source from Upstream port (Default)
1-2: Port 4, +12V source from hot-plug controller
W52 Header 2-3 Shunted 2-3: Port 6, +12 source from Upstream port (Default)
1-2: Port 6, +12 source from hot-plug controller
W46 Header 2-3 Shunted 2-3: Port 8, +12 source from Upstream port (Default)
1-2: Port 8, +12 source from hot-plug controller
W47 Header 2-3 Shunted 2-3: Port 2, +3.3V source from Upstream port (Default)
1-2: Port 2, +3.3V source from hot-plug controller
W53 Header 2-3 Shunted 2-3: Port 4, +3.3V source from Upstream port (Default)
1-2: Port 4, +3.3V source from hot-plug controller
W54 Header 2-3 Shunted 2-3: Port 6, +3.3V source from Upstream port (Default)
1-2: Port 6, +3.3V source from hot-plug controller
W48 Header 2-3 Shunted 2-3: Port 8, +3.3V source from Upstream port (Default)
1-2: Port 8, +3.3V source from hot-plug controller
W49 Header 2-3 Shunted 2-3: Port 2, +3.3AUX source from upstream port (Default)
1-2: Port 2, +3.3V source from hot-plug controller
W55 Header 2-3 Shunted 2-3: Port 4, +3.3AUX source from upstream port (Default)
1-2: Port 4, +3.3V source from hot-plug controller
W56 Header 2-3 Shunted 2-3: Port 6, +3.3AUX source from upstream port (Default)
1-2: Port 6, +3.3V source from hot-plug controller
W50 Header 2-3 Shunted 2-3: Port 8, +3.3AUX source from upstream port (Default)
1-2: Port 8, +3.3V source from hot-plug controller
Table 2.10 Miscellaneous Jumpers, Headers

IDT Installation of the EB48H12G2 Eval Board
EB48H12G2 Eval Board Manual 2 - 8 May 7, 2009
Notes LEDs
There are several LED indicators on the EB48H12G2 which convey status feedback. A description of
each is provided in Table 2.11.
Location Color Definition
DS14 Green Port 2: Power-is-good Indicator
DS20 Green Port 4: Power-is-good Indicator
DS17 Green Port 6: Power-is-good Indicator
DS24 Green Port 8: Power-is-good Indicator
DS16 Green Port 2: Power Indicator
DS23 Green Port 4: Power Indicator
DS19 Green Port 6: Power Indicator
DS26 Green Port 8: Power Indicator
DS15 Yellow Port 2: Attention Indicator
DS21 Yellow Port 4: Attention Indicator
DS18 Yellow Port 6: Attention Indicator
DS25 Yellow Port 8: Attention Indicator
DS27 Green Port 0: Activity Indicator
DS28 Green Port 2: Activity Indicator
DS29 Green Port 4: Activity Indicator
DS30 Green Port 6: Activity Indicator
DS31 Green Port 8: Activity Indicator
DS8 Green Port 0: Linkup Indicator
DS9 Green Port 2: Linkup Indicator
DS10 Green Port 4: Linkup Indicator
DS11 Green Port 6: Linkup Indicator
DS12 Green Port 8: Linkup Indicator
DS3 Red Port 2/8: Power Fault Indicator
DS7 Red Port 4/6: Power Fault Indicator
DS33 Green GPIO7
DS34 Green GPIO6
DS35 Green GPIO5
DS36 Green GPIO4
DS37 Green GPIO3
DS38 Green GPIO2
DS39 Green GPIO1
DS40 Green GPIO0
Table 2.11 LED Indicators