Renesas IDT 89EBPES48H12G2 User manual

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May 2009
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: [phone] • [phone] • FAX: [phone]
Printed in U.S.A.
©2009 Integrated Device Technology, Inc.
IDT®89EBPES48H12G2
Evaluation Board Manual
(Eval Board: 18-677-000)

DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.
Boards that fail to function should be returned to IDT for replacement. Credit will not be given for the failed boards nor will a
Failure Analysis be performed.
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to
such intended use is executed between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform,
when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device
or system, or to affect its safety or effectiveness.
IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc.

Notes
EB48H12G2 Eval Board Manual i May 7, 2009
Table of Contents
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Description of the EB48H12G2 Eval Board
Introduction .....................................................................................................................................1-1
Board Features ...............................................................................................................................1-2
Hardware ................................................................................................................................1-2
Software..................................................................................................................................1-2
Other.......................................................................................................................................1-2
Revision History..............................................................................................................................1-2
Installation of the EB48H12G2 Eval Board
EB48H12G2 Installation..................................................................................................................2-1
Hardware Description .....................................................................................................................2-1
Reference Clocks............................................................................................................................2-1
Power Sources................................................................................................................................2-2
External Power Source...........................................................................................................2-2
PCI Express Analog High Power Voltage Converter..............................................................2-2
PCI Express Analog Power Voltage Converter ......................................................................2-2
PCI Express Transmitter Analog Voltage Converter ..............................................................2-2
Core Logic Voltage Converter ................................................................................................2-2
2.5V I/O Voltage Regulator.....................................................................................................2-3
Power-up Sequence for PES48H12G2 (PCIe Gen2 device).................................................. 2-3
Power-up Sequence for PES48H12 (PCIe Gen1 device).......................................................2-3
Reset ......................................................................................................................................2-3
Fundamental Reset ................................................................................................................2-3
Downstream Reset .................................................................................................................2-3
Boot Configuration Vector...............................................................................................................2-4
SMBus Interfaces............................................................................................................................2-5
SMBus Slave Interface ...........................................................................................................2-5
SMBus Master Interface .........................................................................................................2-6
JTAG Header.................................................................................................................................. 2-6
Attention Buttons.............................................................................................................................2-6
Miscellaneous Jumpers, Headers................................................................................................... 2-7
LEDs ...............................................................................................................................................2-8
PCI Express Connectors.................................................................................................................2-9
EB48H12G2 Board Figure............................................................................................................2-11
Software for the EB48H12G2 Eval Board
Introduction .....................................................................................................................................3-1
Device Management Software........................................................................................................3-1
Schematics
Schematics .....................................................................................................................................4-1

IDT Table of Contents
EB48H12G2 Eval Board Manual ii May 7, 2009
Notes

Notes
EB48H12G2 Eval Board Manual iii May 7, 2009
List of Tables
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Table 2.1 Clock Source Selection .......................................................................................................2-1
Table 2.2 SMA Connectors - Onboard Reference Clock ....................................................................2-2
Table 2.3 External Power Connector - J4 ...........................................................................................2-2
Table 2.4 Downstream Reset Selection .............................................................................................2-4
Table 2.5 Boot Configuration Vector Signals ......................................................................................2-4
Table 2.6 Boot Configuration Vector Switches S3 & S13 (ON=0, OFF=1) .........................................2-5
Table 2.7 Slave SMBus Interface Connector ......................................................................................2-5
Table 2.8 JTAG Connector Pin Out ....................................................................................................2-6
Table 2.9 Attention Buttons ................................................................................................................2-6
Table 2.10 Miscellaneous Jumpers, Headers .......................................................................................2-7
Table 2.11 LED Indicators ....................................................................................................................2-8
Table 2.12 PCI Express x8 Connector Pinout ......................................................................................2-9

IDT List of Tables
EB48H12G2 Eval Board Manual iv May 7, 2009
Notes

Notes
EB48H12G2 Eval Board Manual v May 7, 2009
List of Figures
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Figure 1.1 Function Block Diagram of the EB48H12G2 Eval Board ...................................................1-1

IDT List of Figures
EB48H12G2 Eval Board Manual vi May 7, 2009
Notes

Notes
EB48H12G2 Eval Board Manual 1 - 1 May 7, 2009
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Chapter 1
Description of the
EB48H12G2 Eval Board
Introduction
The 89HPES48H12G2 switch (also referred to as PES48H12G2 in this manual) is a member of IDT’s
PCI Express® standard based line of products. It is a PCIe® Base Specification 2.0 compliant (Gen2) 12-
port switch. There are twelve x4 lanes ports. Two x4 ports can be merged to form one x8 port in
PES48H12G2. One upstream port is provided for connecting to the root complex (RC), and up to eleven
downstream ports are available for connecting to PCIe endpoints or to another switch. More information on
this device can be found in the 89HPES48H12G2 User Manual.
The 89EBPES48H12G2 Evaluation Board (also referred to as EB48H12G2 in this manual) provides an
evaluation platform for the PES48H12G2 switch. It is also a cost effective way to add PCIe ports (slots) to
an existing system with limited number of PCIe ports/slots. The EB48H12G2 board is designed to function
as an add-on card to be plugged into a x8 PCIe slot available on a motherboard hosting an appropriate root
complex and microprocessor(s). The EB48H12G2 is a vehicle to test and evaluate the functionality of the
PES48H12G2 switch. It is also designed to work with the PES48H12 (Gen 1) switch. Refer to application
note AN-550 for detail information on Designing Gen2-Ready boards for IDT’s 48-lane, 12-port PCIe
Switches. Customers can use this board to get a headstart on software development prior to the arrival of
their own hardware. The EB48H12G2 is also used by IDT to reproduce system-level hardware or software
issues reported by customers. Figure 1.1 illustrates the functional block diagram representing the main
parts of the EB48H12G2 board.
Figure 1.1 Function Block Diagram of the EB48H12G2 Eval Board
JTAG
Header
Main
Reset
I/O Expander
MAX7311
PCIe x8 Upstream Edge
EEPROM
24LC512
SMBUS
HEADER
PES48H12G2
PCI Express
Switch
External Power
PCIe x8 Downstream Slot
PCIe x8 Downstream Slot
x8
25 MHz Crystal
Clock
Generator
Clock
Fanout
SMBus
PCIe x8 Downstream Slot
Voltages on board
+12V, +3.3V, +2.5V, +1.0V
Connector
Power
Module
PTH08T240
x8
x4
x8
Port 4
Port 6
Port 8
Port 0 PCIe x8 Downstream Slot
Port 2 x8

IDT Description of the EB48H12G2 Eval Board
EB48H12G2 Eval Board Manual 1 - 2 May 7, 2009
Notes Board Features
Hardware
PES48H12G2 PCIe Gen2 switch
– Up to twelve x4 or six x8 ports - 48 PCIe lanes
– PCIe Base Specification Revision 2.0 compliant (Gen2 SerDes speeds of 5 GT/S)
– Up to 2048 byte maximum Payload Size
– Automatic lane reversal and polarity inversion supported on all lanes
– Automatic per port link width negotiation to x8, x4, x2, x1
– Load configuration from an optional serial EEPROM via SMBUS
Upstream, Downstream Port
– One edge connector on the upstream port, to be plugged into a slot with at least x8 capable on a
host motherboard
– Four slot connectors on the downstream ports, for PCIe endpoint add-on cards to be plugged in.
These slot connectors are x8 mechanically and electrically connected as three x8 and one x4, but
open-ended for card widths greater than x8 (e.g. x16).
Numerous user selectable configurations set using onboard jumpers and DIP-switches
– Source of clock - host clock or onboard clock generator
– Two clock rates (100/125 MHz) from an onboard clock generator
– Boot mode selection
SMBUS Slave Interface (4 pin header)
SMBUS Master Interface connected to the Serial EEPROMs through I/O expander
“Attention” button for each downstream port to initiate a hot swap event on each port
Four pin connector for optional external power supply
Push button for Warm Reset
Several LEDs to display status, reset, power, “Attention”, etc.
One 10-pin JTAG connector (pitch 2.54 mm x 2.54 mm)
Software
There is no software or firmware executed on the board. However, useful software is provided along
with the Evaluation Board to facilitate configuration and evaluation of the PES48H12G2 within host systems
running popular operating systems.
Installation programs
– Operating Systems Supported: Windows Server 2003, Windows Server 2008, WindowsXP, Vista,
Linux
GUI based application for Windows and Linux
– Allows users to view and modify registers in the PES48H12G2
– Binary file generator for programming the serial EEPROMs attached to the SMBUS.
Other
A metal bracket is provided to firmly hold in place three endpoints plugged into the EB48H12G2
board.
An external power supply may be required under some conditions.
SMBUS cable may be required for certain evaluation exercises.
SMA connectors are provided on the EB48H12G2 board for clock outputs.
Revision History
January 5, 2009: Initial publication of eval board manual.