Renesas P9412 User manual

P9412 Evaluation Board Manual
P9412
Wireless Power TRx WattS
hareTM Solution for Wireless Charging for Wireless Power Charging
Rev.1.7
Jul.8.20
Page 1
Description
The P9412 CSP TRx evaluation board can be used
to demonstrate the features and performance of the
P9412 Wireless Power Transceiver solution for
Mobile Device with a custom Rx only or TRx coils.
The intuitive top-level placement of components,
layout, and controls simplify the design-in process,
optimizes the user experience, and emphasizes the
impressive level of integration and abundance of
useful features that this device offers.
The device is powered by a Renesas Proprietary
TRx coil that can be copied when used with
Renesas products (Worldwide patent pending). The
P9412 operates in RX mode or TX mode depending
on the setting and the firmware loaded to its
Multiple-Time Programmable memory (MTP).
Features
•P9412 CSP TRx WattShareTM Wireless power
Solution
•Delivers over 30W output power as a Receiver
•Delivers over 6W output power as Transmitter
•Integrated high-performance capacitor divider
•XY Position Sensing Technology
•I2C Connector
•Multiple-Time Programmable Memory (MTP)
•Fully assembled with test points and coil fixture
•6-layer PCB with 1oz. copper
Figure 1. P9412 CSP Demo Board v1.3
J3 pin I2C Access
for MTP / Registers
WPC TRx
Coil inputs
P9412
J8, J9 pins
for test points
CPOUT Output
to load
V1P8_AP
input
SMD Test Points
V5P0_AP
input
CPOUTS for
Kelvin sensing

P9412 Evaluation Board Manual
Rev.1.7
Jul.8.20
Page 2
Contents
1. Usage Guide................................................................................................................................................... 7
1.1 Quick-Start Guide for Rx and Tx Mode Operation ................................................................................ 7
1.2 Using the Windows GUI ........................................................................................................................ 8
1.2.1. Using the GUI to Program the P9412 ..................................................................................... 8
1.2.2. Using the GUI to Read / Write to Registers .......................................................................... 12
1.2.3. Using the GUI to Run in High Power Capacitor Divider Mode.............................................. 15
1.2.4. Using the GUI to Run in TX Mode ........................................................................................ 18
1.3 I2C Function......................................................................................................................................... 21
1.3.1. I2C Read back of MTP contents........................................................................................... 22
2. Registers....................................................................................................................................................... 23
2.1.1. Identification and Revision Registers.................................................................................... 23
2.1.1.1. Chip ID Register, Chip_ID_L (0x00), Chip_ID_H (0x01).................................................................. 23
2.1.1.2. Chip Revision and Font Register, Chip_Rev (0x02)........................................................................ 23
2.1.1.3. Customer ID Register, Customer ID (0x03)..................................................................................... 23
2.1.1.4. Firmware Major Rev. Registers, FW_Major_Rev_L (0x04), FW_Major_Rev_H (0x05)................... 23
2.1.1.5. Firmware Minor Rev. Registers, Minor_Rev_L (0x06), FW_Minor_Rev_H (0x07).......................... 23
2.1.1.6. Firmware Date/Time Registers, FW_Date_Code (0x 08~13), FW_Timer_Code (0x 14~1B).......... 23
2.1.1.7. Configuration Major Revision Registers, CFG_Major_Rev (0x1C).................................................. 24
2.1.1.8. Configuration Minor Revision Registers, CFG_Minor_Rev (0x1D).................................................. 24
2.1.1.9. Reference Design Version Register, RefDesignVer (0x4A)............................................................. 24
2.1.2. Status and Interrupt Registers .............................................................................................. 25
2.1.2.1. Status Registers, Status_L (0x34), Status_H (0x35)....................................................................... 25
2.1.2.2. Interrupt Registers, INT_L (0x36), INT_H (0x37)............................................................................. 25
2.1.2.3. Interrupt Enable Registers, INT_Enable_L (0x38), INT_Enable_H (0x39)...................................... 26
2.1.2.4. Interrupt Clear Registers, INT_Clear_L (0x3A), INT_Clear_H (0x3B)............................................. 27
2.1.2.5. TRX System Operating Mode Register, Sys_Op_Mode (0x4C)...................................................... 27
2.1.2.6. Over-Current Status Register, OC_Status (0xB5)........................................................................... 27
2.1.3. Battery Status and Power Transfer Registers....................................................................... 28
2.1.3.1. Charge Status Register, CHG_Status (0x3E).................................................................................. 28
2.1.3.2. End of Power Transfer Register, EPT_Code (0x3F) ....................................................................... 28
2.1.4. Operation Parameters Registers .......................................................................................... 28
2.1.4.1. Vout Set Register, Vout_Set_L (0x6C), Vout_Set_H (0x6D)........................................................... 28
2.1.4.2. TRX Vout Voltage Registers, Vout_L (0x42), Vout_H (0x43).......................................................... 29
2.1.4.3. Iout Limit Set Register (0x3D) ......................................................................................................... 29
2.1.4.4. TRX Iout / Iin Value Registers, Iout / Iiin_L (0x44), Iout / Iin_H (0x45) ............................................ 29
2.1.4.5. TRX Vrect Voltage Registers, Vrect_L (0x40), Vrect_H (0x41)....................................................... 29
2.1.4.6. TRX Die Temperature Registers, DieTemp_L (0x46), DieTemp_H (0x47)...................................... 29
2.1.4.7. TRX AC Frequency Registers, AC_Freq_L (0x48), AC_Freq_H (0x49).......................................... 29
2.1.5. Command and Communication Registers ............................................................................ 30
2.1.5.1. System Command Register, SYS_CMND_L (0x4E), SYS_CMND_H (0x4F).................................. 30
2.1.5.2. Config Table Command Register, Config_CMND (0xCA)............................................................... 30
2.1.5.3. TRX Header Register (PropPkt Send), TRX_Header_Out (0x50)................................................... 32
2.1.5.4. TRX Data Value1 Register (PropPkt Send), TRX_Data_VALUE1_Out (0x51)................................ 33
2.1.5.5. TRX Data Value 2~5 Reg. (PropPkt Send), TRX_Data_Value2_5_Out (0x52, 0x53, 0x54, 0x55).. 33
2.1.5.6. TRX Header Register (PropPkt Received), TRX_Header_In (0x58)............................................... 34

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2.1.5.7. TRX Data Value 1~2 Register (PropPkt Received), TRX_Data_Value1_2_In (0x59, 0x5A)........... 34
2.1.5.8. Com Channel Send Size Register, CC_Send_Size_L (0x140), CC_Send_Size_H (0x141)........... 34
2.1.5.9. Com Channel Send Index Register, CC_Send_Index_L (0x142), CC_Send_Index_H (0x143)...... 34
2.1.5.10. Com Channel Receive Size Register, CC_Recv_Size_L (0x144), CC_Recv_Size_H (0x145)..... 35
2.1.5.11. Com Channel Receive Index Reg., CC_Recv_Index_L (0x146), CC_Recv_Index_H (0x147)...... 35
2.1.5.12. Com Channel Status Register, CC_Status (0x148)....................................................................... 35
2.1.5.13. Pending Packets Register, Pend_Pkts (0x149)............................................................................. 35
2.1.5.14. ADT Packet Time Out Register, ADT_Timeout_PKT (0x150)....................................................... 35
2.1.5.15. ADT Stream Time Out Register, ADT_Timeout_STR (0x151) ...................................................... 35
2.1.5.16. ADT Error Code Register, ADT_Error_Code (0x14D)................................................................... 36
2.1.5.17. ADT Buffer Registers, (0x0800 ~ 0x0FFF).................................................................................... 36
2.1.5.18. Frequency Shift Keyed modulation (FSK) Transmitter to Receiver Communication ..................... 37
2.1.5.19. FSK Communication Protocol ....................................................................................................... 37
2.1.6. HW Control and Monitor Registers ....................................................................................... 37
2.1.6.1. Ping Frequency Register, PingFreq_L (0x6A), PingFreq_H (0x6B) ................................................ 37
2.1.6.2. HW Flag Register, HW_Flag (0x81)................................................................................................ 38
2.1.6.3. Over Voltage Protection Register, OV_Set (0xB3).......................................................................... 38
2.1.6.4. RX Mode Communication Modulation FET Register, CMFET_L (0xF4), CMFET_H (0xF5) ........... 38
2.1.6.5. RX Mode AFC Communication Modulation FET Register, AFC_CMFET (0xB2)............................ 38
2.1.6.6. RX Mode High Vout Communication Modulation FET Register, HiVout_CMFET (0x11B).............. 39
2.1.6.7. Align X Register, AlignX (0xB0)....................................................................................................... 39
2.1.6.8. Align Y Register, AlignY (0xB1)....................................................................................................... 39
2.1.6.9. Align adc Offset Registers, AlignAdcOffX (0x164), AlignAdcOffY (0x165)...................................... 40
2.1.6.10. Align Slope1 Registers, AlignSlope1X (0x166), AlignSlope1Y (0x167)......................................... 40
2.1.6.11. Align Slope2 Registers, AlignSlope2X (0x168), AlignSlope2Y (0x169)......................................... 40
2.1.6.12. Align Offset Registers, AlignOffX (0x16A), AlignOffY (0x16B)....................................................... 41
2.1.6.13. Align Threshold Registers, AlignThreshX (0x16C), AlignThreshY (0x16D)................................... 41
2.1.7. Vrect Control Registers......................................................................................................... 41
2.1.7.1. Target_Vrect Register, Vrect_Target_L(0x90), VrectTarget_H (0x91) ............................................ 41
2.1.7.2. Vrect Knee Register, PwrKnee (0x92)............................................................................................. 41
2.1.7.3. Vrect Correction Factor Register, VrCorrFactor (0x93) ................................................................... 42
2.1.7.4. Vrect Maximum Correction Register, VrMaxCorr_L (0x94), VrMaxCorr_H (0x95) .......................... 42
2.1.7.5. Vrect Minimum Correction Register, VrMinCorr_L (0x96), VrMinCorr_H (0x97) ............................. 42
2.1.7.6. Vrect Adjust Register, VRectAdj (0x5E) .......................................................................................... 42
2.1.8. Capacitor Divider Registers .................................................................................................. 42
2.1.8.1. Capacitor Divider Mode Status Register, CDModeSts (0x100)....................................................... 42
2.1.8.2. Capacitor Divider Mode Request Register, CDModeReq (0x101)................................................... 42
2.1.8.3. TRX CPout Voltage Registers, VCPout_L (0x10C), VCPout_H (0x10D)......................................... 43
2.1.8.4. Capacitor Divider Vout Threshold Reg., CD_Vout_Thd_L (0x10A), CD_Vout_Thd _H (0x10B)..... 43
2.1.8.5. Capacitor Divider Frequency Set Register, CD_Freq_L (0x108), CD_Freq _H (0x109).................. 43
2.1.9. Foreign Object Detection Registers...................................................................................... 43
2.1.9.1. RX FOD Adjustable Parameters Registers, (0x70 ~ 0x7F) ............................................................. 43
2.1.9.2. TX FOD Threshold Registers, TX_FOD_Thrsh_L (0xD4), TX_FOD_Thrsh_H (0xD5).................... 44
2.1.9.3. TX FOD Gain Register, TX_FOD_Gain (0xD1)............................................................................... 44
2.1.9.4. TX FOD Offset Registers, TX_FOD_Offset_L (0xD2), TX_FOD_Offset_H (0xD3) ......................... 44
2.1.9.5. TX FOD Offset Option Register, FOD_OffsetOpt (0XA3)................................................................ 44
2.1.10. WPC Basic and Extended Protocol Registers...................................................................... 45
2.1.10.1. EPP Q-Factor Register, EPP_Q_Factor (0x83)............................................................................. 45

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2.1.10.2. EPP Q-Factor A Register, EPP_Q_Fact_A (0x138)...................................................................... 46
2.1.10.3. EPP Q-Factor B Register, EPP_Q_Fact_B (0x139)...................................................................... 46
2.1.10.4. EPP TX Guaranteed Power Register, EPP_TXGuarPwr (0x84) ................................................... 46
2.1.10.5. EPP TX Potential Power Register, EPP_TXPotentPwr (0x85)...................................................... 46
2.1.10.6. EPP TX Capability Flag Register, EPP_TXCapaFlag (0x86) ........................................................ 46
2.1.10.7. EPP Renegotiation Status Register, EPP_RN_Sts (0x87)............................................................ 46
2.1.10.8. EPP Current RPP Header Register, MPCur_RPP (0x88) ............................................................. 47
2.1.10.9. EPP Current Negotiated Power Register, MPCur_NegPwr (0x89)................................................ 47
2.1.10.10. EPP Current Maximum Power Register, MPCur_MaxPwr (0x8A)............................................... 47
2.1.10.11. EPP Current FSK Modulation Register, MPCur_FSK (0x8B)...................................................... 47
2.1.10.12. EPP Request RPP Header Register, MPReq_RPP (0x8C)......................................................... 47
2.1.10.13. EPP Request Re-Negotiated Power Register, MPReq_NegPwr (0x8D)..................................... 47
2.1.10.14. EPP Request Maximum Power Register, MPReq_MaxPwr (0x8E)............................................. 47
2.1.10.15. EPP Request FSK Modulation Register, MPReq_FSK (0x8F).................................................... 48
2.1.10.16. WPC Spec Revision Register, WPC_SpecRev (0xB9)................................................................ 48
2.1.10.17. EPP Rx Manufacturer Code Reg., MpRxManufCode_L (0xBA), MpRxManufCode_H (0xBB).... 48
2.1.10.18. WPC Identification Register, WPC_ID (0xE0 ~ 0XE3) ................................................................ 48
2.1.10.19. Extended Identification Packet Register, WPC_ExtID (0xE4 ~ 0xEB)......................................... 49
2.1.10.20. Signal Strength Packet Register, SSPValue (0xB4).................................................................... 49
2.1.10.21. Control Error Packet Register, CEPValue (0x5F)........................................................................ 49
2.1.10.22. RX Power Register, Rx_Pwr_L (0xCE), Rx_Pwr_H (0xCF) ........................................................ 49
2.1.10.23. WPC Manufacturer ID Register, WPC_ManufID_L (0x15E), WPC_ManufID_H (0x15F)............ 50
2.1.11. Proprietary High-Power Protocol Registers.......................................................................... 50
2.1.11.1. Proprietary Tx Potential Power Register, PropTxPotenPwr (0xC4)............................................... 53
2.1.11.2. Proprietary Requested Power Register, PropReqPwr (0xC5)....................................................... 53
2.1.11.3. Proprietary Current Power Register, PropCurrPwr (0xC6)............................................................ 53
2.1.11.4. Proprietary Negotiated Power Step Size Register, PropModePwrStep (0xC7)............................. 53
2.1.11.5.Proprietary Mode Status Register, PropModeStatus (0xC8)......................................................... 53
2.1.11.6. Proprietary Mode Error Register, PropErrStatus (0xC9)................................................................ 53
2.1.12. TX Mode Registers ............................................................................................................... 54
2.1.12.1. TX Status Registers, Status_L (0x34), Status_H (0x35)................................................................ 54
2.1.12.2. TX Interrupt Registers, INT_L (0x36), INT_H (0x37)..................................................................... 54
2.1.12.3. TX Interrupt Enable Registers, INT_Enable_L (0x38), INT_Enable_H (0x39)............................... 55
2.1.12.4. TX Interrupt Clear Registers, INT_Clear_L (0x3A), INT_Clear_H (0x3B)...................................... 56
2.1.12.5. System TX Command Register, TX_CMND (0x4D)...................................................................... 56
2.1.12.6. TX Mode System Command Register, TxSysCmnd_L (0x4E), TxSysCmnd_H (0x4F)................. 57
2.1.12.7. TX Mode CEP Threshold Register, TxCepThrshVal (0xD6).......................................................... 57
2.1.12.8. TX Mode CEP Threshold Count Limit Register, TxCepThrshCntLmt (0xD7) ................................ 57
2.1.12.9. TX Mode API Current Limit Registers, I_API_Limit_L (0x56), I_API_Limit_H (0x57).................... 58
2.1.12.10. TX Mode API Current Hysteresis Register, I_API_Hys (0x82).................................................... 59
2.1.12.11. TX Mode API Current Limit Offset Registers, I_API_Offset_L (0xF6), I_API_Offset_H (0xF7) ... 59
2.1.12.12. TX Ping Frequency (Period) Register, PingFreqPer_L (0x90), PingFreqPer_H (0x91)............... 59
2.1.12.13. TX Ping Duty Cycle Register, PingDC (0x92).............................................................................. 59
2.1.12.14. TX Minimum Duty Cycle Register, MinDC (0x93)........................................................................ 59
2.1.12.15. TX Minimum Frequency (Period) Register, MinFreqPer_L (0x94), MinFreqPer_H (0x95) .......... 60
2.1.12.16. TX Maximum Frequency (Period) Register, MaxFreqPer_L (0x96), MaxFreqPer_H (0x97) ....... 60
2.1.12.17. TX Mode Operating Period Register, TxPeriod_L (0xA4), TxPeriod_H (0xA5) ........................... 60
2.1.12.18. TX Mode Operating Duty Cycle Register, TxDuty (0xA6)............................................................ 60

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2.1.12.19. TX Mode Over-Voltage Protection Register, Tx_OVP_L (0x9E), TX_OVP_H (0x9F).................. 60
2.1.12.20. TX Mode Over-Current Protection Register, TX_OCP_L (0xA0), TX_OCP_H (0xA1)................. 61
2.1.12.21. TX Conflict Threshold Register, TxConfThrsh (0x134)................................................................ 61
2.1.12.22. TX Conflict Count Register, TxConfCnt (0xAF)........................................................................... 61
2.1.12.23. TX Power Register, TX_Power_L (0xAC), TX_Power_H (0xAD) ................................................ 61
2.1.12.24. TX Dead Time Register, TX_DeadTime (0x9C).......................................................................... 61
2.1.12.25. TX Control Delay Register, TX_ControlDelay (0xAE).................................................................. 62
2.1.13. Commonly Used Registers ................................................................................................... 62
2.1.13.1. Monitoring, Status, Interrupt, and Operating Mode Registers........................................................ 62
2.1.13.2. Settings and Command Registers................................................................................................. 62
3. Schematic Diagram ..................................................................................................................................... 63
4. Bill of Materials ............................................................................................................................................ 64
5. Board Layout................................................................................................................................................ 66
5.1 FTDI Dongle ........................................................................................................................................ 72
6. Ordering Information................................................................................................................................... 74
7. Revision History .......................................................................................................................................... 74
Figures
Figure 1. P9412 CSP Demo Board v1.3...................................................................................................................1
Figure 2. Capacitor Divider Mode Transition Sequence...........................................................................................7
Figure 3. GUI Software.............................................................................................................................................8
Figure 4. FTDI USB-I2C Bridge Connected to I2C Terminal J3 of P9412 CSP TRx Demo Board..........................8
Figure 5. Initial Screen of P9412 GUI.......................................................................................................................9
Figure 6. USB-Bridge is Detected, P9412 is Not Connected...................................................................................9
Figure 7. P9412 MTP Programming using I2C Slave Device Address 0x3C .........................................................10
Figure 8. MTP Programming Successful................................................................................................................10
Figure 9. GUI Detects an Unprogrammed Part and Issues a Warning..................................................................11
Figure 10. Firmware Program Verification Success...............................................................................................11
Figure 11. Verify FW Revision and Date Code.......................................................................................................12
Figure 12. I2C Read / Write Registers....................................................................................................................13
Figure 13. Basic 1 Tab, after a “Read 1 time” Operation .......................................................................................13
Figure 14. VOUT Adjustments Can be made in Three Ways.................................................................................14
Figure 15. Check Cap Divider Mode ......................................................................................................................15
Figure 16. Enable Cap Divider Mode Operation.....................................................................................................16
Figure 17. P9412 Successfully Enters Cap Div. Mode and is Ready to Transition to High-Power Operation.......16
Figure 18. P9412 Transition to High Power Operation...........................................................................................17
Figure 19. Using the GUI to Manually Increase the RX Vout Voltage....................................................................17
Figure 20. Using the GUI to Manually Decrease the RX Vout Voltage..................................................................18
Figure 21. Basic Registers Initial Read Back; Before TX Mode Entry....................................................................19
Figure 22. Tx Mode Entry, Without an Rx Placed on the P9412 Coil; Vrect and Vout Voltage Read Back ~7V...19
Figure 23. Tx Mode, With an Rx Placed on the P9412 Coil; Use the GUI to Monitor the Status...........................20
Figure 24. Exit Tx Mode, With an Rx Placed on the P9412 Coil; Use the GUI to Send Exit Command................20
Figure 25. Verify Exit TX Mode; Use the GUI to Read Mode.................................................................................21
Figure 26. I2C Read Protocol using P9412............................................................................................................21

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Figure 27. I2C Write Protocol using P9412............................................................................................................22
Figure 28. Example of differential bi-phase encoding. ...........................................................................................37
Figure 29. Example of asynchronous serial byte format........................................................................................37
Figure 30. Proprietary High Power Protocol Flow Chart ........................................................................................52
Figure 31. P9412 DEMO Board v1.3 Schematic....................................................................................................63
Figure 32. Top and Top Silkscreen Layer ..............................................................................................................66
Figure 33. Inner1 GND Layer .................................................................................................................................67
Figure 34. Inner2 POWER/Signal/GND Layer........................................................................................................68
Figure 35. Inner3 POWER/ GND Layer..................................................................................................................69
Figure 36. Inner4 POWER/Signal/GND Layer........................................................................................................70
Figure 37. Bottom Layer.........................................................................................................................................71
Figure 38. FTDI Dongle for Programming the Firmware into P9412 MTP.............................................................72
Figure 39. FTDI Dongle Schematic for Programming the Firmware into P9412 MTP and Reading Registers .....73
Tables
Table 1. Bill of Materials .........................................................................................................................................64

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1. Usage Guide
The P9412 CSP TRx Demo board is designed to demonstrate the performance and functionality of the P9412
wireless transceiver in a lab bench test environment. For complex or electrically sensitive situations, it is
recommended to use the reference layout to integrate this design into the final system in order to eliminate
hardware limitations or signal degradation introduced by long leads.
With no computer interface, the demo board can function in its pre-programmed Rx mode of operation together
with a WPC compatible Tx transmitter such as the P9235A, P9236A, P9247 Tx EVKIT, or the P9260 Automotive
Tx.
1.1 Quick-Start Guide for Rx and Tx Mode Operation
The P9412, when used as a receiver (Rx), has three Capacitor Divider operating modes:
•Disable: Vout is on, but CPout is off
•Bypass: CPout = Vout
•Cap Divider: CPout = Vout/2
Any mode change between Bypass and Cap divider mode must go through Disable (see Figure 2). Note that the
firmware handles the transition through the Disable mode automatically and the information is being provided for
reference. CPout must not be loaded during mode transitions between Bypass and Cap Divider.
Bypass
Vout = Vout_set
CPout = Vout
Cap Divider
Vout = Vout_set
CPout = ½ Vout
Disable
Vout = Vout_set
CPout = 0V
Figure 2. Capacitor Divider Mode Transition Sequence
The default configuration for the EVK demo board is for LDO1P8 to be connected to the SCL and SDA I2C lines
only. To apply 1.8VDC from the target Application PCB, wire 1.8VDC to the V1P8_AP input test point and add a
GND reference wire (can be shared with VBAT GND wire). In order for the P9412 Demo PCB to properly
operate, the V1P8_AP pin should be powered by a 1.8VDC source at all times.
With no load applied to the VOUT or CPOUT pins, place the P9412 Rx coil with the windings facing down
(toward the Tx coil) centered above a valid Tx unit with a 1mm non-metallic spacer placed between the Tx
interface and the Rx coil. The charging pad can be a pre-powered WPC Tx, or can be powered after placing the
Rx coil into position.
Verify that power is available at the Rx output by measuring the voltage at the CPOUT1 test point to ground
(GND). The P9412 will start up in Bypass mode (i.e., Cap. Div. is not running and VOUT is transferred directly to
the CPOUT node) and can deliver up to 1.5A at 12V (if the Tx can support this much power transfer). A heavy
load (loads > 1A) should not be applied until the Cap Divider Bypass Mode has been verified (CPOUT = VOUT).
Additionally, startup into heavy loads can cause the TX to fail to connect due to FOD or OC. If higher output
power is desired, the integrated capacitor divider must be set into Cap Divider mode where up to 3A load can be

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connected between CPOUT1 and the GND terminals. For more information, see “Using the GUI to run in high
power Capacitor Divider mode”.
The I2C connector J3 can be used to program the P9412 or R/W to any valid Read/Write registers. The included
USB-I2C Bridge (FT4222 Dongle) and GUI for Windows PC allow reading, writing to registers, and programming
new firmware into MTP.
GUI software is shown in Figure 3. Use this revision or higher (latest revision available).
Figure 3. GUI Software
1.2 Using the Windows GUI
Connect the Bridge to PC via USB connector. Attach the Bridge to the I2C terminal J3 on the P9412 EVAL board
as shown on Figure 44. Line up the GND (black) of the Dongle with the pin 3 of J3 connector.
Figure 4. FTDI USB-I2C Bridge Connected to I2C Terminal J3 of P9412 CSP TRx Demo Board
1.2.1. Using the GUI to Program the P9412
To program the device, remove the P9412 demo board coil from the Tx, connect GND, SDA, SCL to the FTDI
USB-I2C Bridge and power CPOUT from an external Power Supply set to 5V to 8V (see Figure 4).
Note: Field MTP updates are possible using the host AP using a similar method and I2C. Contact the factory for
details.
J3-1 SCL
J3-2 SDA
J3-3 GND
CPOUT and
GND to
external P/S

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1. Open the GUI program – P9412_Demo_GUI_v0.10r007_.exe or higher. The initial screen of the GUI is
shown on Figure 5.
Figure 5. Initial Screen of P9412 GUI
Note: Make sure the external power supply is turned on and the USB-I2C Bridge is connected to the PC. Verify
that the Device selected is the P9412 at the top of screen. Check the “FTDI dongle detected” and “P9412
connected on FTDI dongle” messages are shown at the bottom of the screen. If you do not see these messages,
unplug the USB cable at the PC side, plug it in again and then check all connections.
If the message indicates that the “FTDI dongle detected” but the P9412 is not connected, see Figure 6 – it may
be necessary to select the P9412 again using the “Device” pull-down menu and clicking on “P9412 RX”.
Figure 6. USB-Bridge is Detected, P9412 is Not Connected

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2. To update the MTP program, select the “FW Pgm” tab. Then make sure the proper file type is selected,
either HEX or BIN box is checked and Press the “Load File” button, a pop-up window will appear. Navigate
to the current P9412 FW *.* file and Open the file. See Figure 7, which indicates the FW file was read
successfully.
Figure 7. P9412 MTP Programming using I2C Slave Device Address 0x3C
3. After loading the file, press the “Program” button, the MTP will be programmed and the GUI will indicate if
successful or if there were errors. See Figure 8, which indicates that the programming was successful. If
there are any errors during programming, attempt to program again.
Figure 8. MTP Programming Successful

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a. If an un-programmed part is detected, the GUI will issue a warning message (see Figure 9). Follow the
instructions: Turn off the external P/S and connect to Vrect or Vout, wait for 20 seconds, then turn on the
P/S and try to program again by “clicking” on the OK button. Failure to connect the external P/S to Vrect
or Vout when programming a blank IC can result in damage to the part.
Figure 9. GUI Detects an Unprogrammed Part and Issues a Warning
4. If the firmware was programmed successfully, power cycle the external P/S (turn P/S off then on). Then
press the “Verify” button. A total match should be indicated for successful programming (see Figure 10). If
there are any errors, attempt to program again.
Figure 10. Firmware Program Verification Success

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5. After programming and verification success.
a. Verify programming, it is recommended to select the “Basic 1” tab and press the “Read 1 time” button to
check that the firmware revision and date code are correct.
b. Turn off the external Power Supply and either set up the P9412 for TRx mode (see “Using the GUI to run
in TX mode” section), or remove the external power supply from CPOUT and place the P9412 on a
compatible Tx.
Figure 11. Verify FW Revision and Date Code
1.2.2. Using the GUI to Read / Write to Registers
Access to the P9412 status and control settings are done by reading and writing the I2C registers. The registers
are described in “Registers.” To read and write to the registers, use one of the following procedures:
1. Place the P9412 on a compatible Tx. The P9412 is configured as a BPP Rx and will connect and initially
start in Bypass mode, where the Capacitor Divider is not running and VOUT is transferred directly to the
CPOUT node. The voltage at CPOUT and VOUT should be 5V.

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2. To read and write specific registers, select the “Dev, I2C” tab and click the “I2C reg Rd/Wr” box. The I2C
Rd/Wr block will stay accessible when different tabs are selected (see Figure 12).
a. For example, to check the Rx mode CPout voltage, read the 16bit - code of I2C register 0x10C. First
enter 010C in the “Addr” field, select 2 “Bytes”, then press the “Read” button.
Figure 12. I2C Read / Write Registers
3. For bulk reading of common operating registers, select the Basic 1 tab and select one of the “Read 1 time”
buttons depending on what section the register of interest is in. The register values within the bracketed
section can be constantly monitored by selecting “Read loop”, and the monitoring can be stopped by
selecting “Stop”. Similarly, all the registers on this tab can be monitored continuously by selecting the “Read
loop” button at the bottom.
Figure 13. Basic 1 Tab, after a “Read 1 time” Operation
Read
registers in
Read or
Clear all

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4. Reciprocally, register 0x6C (valid for FW37 and above) is used to set the value of VOUT, as shown in Figure
14. Any register can be read (or written assuming it is a writeable register) from the I2C reg Rd/Wr tool at
any time. Address is the starting address and the number of bytes should be specified prior to clicking
“Read” for read, or “Write” for write operations.
Figure 14. VOUT Adjustments Can be made in Three Ways
•Vout_Set = Value in 0.01V entered into 0x6C: From the “Basic 2” tab, Vout Set field, enter or select the
voltage using the up/down arrows and then clicking Write, or
•Vout_Set = code_value (decimal value converted to hex) * 0.01 (V); 0x0230 corresponds to 5.6V and
clicking Write in “I2C Rd/Wr” block, or
•Click on one of the pre-set values. When clicking a pre-set button it is not necessary to click the Write
button.
Vout_Set in 40 mV step, 3.52 V ~ 20V range.
Note: The P9412 is configured as a BPP/EPP Rx and will connect and initially start in Bypass mode, CPOUT ≈
VOUT. In Bypass mode, the VOUT or CPOUT voltage is limited to a 12V maximum, and a standard BPP Tx is
normally limited to 5W (typically CPOUT = 5V, 1A load on the Rx). In order to attain higher output power, an EPP
TX or a proprietary TX, and running the P9412 in Cap Divider mode is required. For instructions on entering Cap
Divider mode, see “Using the GUI to run in high power Capacitor Divider mode”.
Pre-set Vout
voltages

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1.2.3. Using the GUI to Run in High Power Capacitor Divider Mode
When preparing to deliver higher power or to use the integrated Capacitor Divider (CD), the following steps
should be taken to allow the Cap Divider the opportunity to soft-start safely without causing wireless connection
interruptions or cause excessive current to flow during start-up:
1. Reduce the load on CPOUT to 0A.
2. Set the Cap Divider mode to “Cap Div”.
3. Monitor the CD mode Status register for Cap Div Operation.
a. Or, check the INT register for the CD_MODECHANGE_INT (used to notify the AP).
4. Increase the CPOUT voltage and proprietary Tx input voltage as required (during Cap Div mode, CPOUT ≈
VOUT / 2).
Note:VOUT is only allowed to be set above 12V in Cap Div mode. Also, VOUT must be below 12V when exiting
Cap Div mode. CPout must not be loaded during any Cap Divider mode transitions. When in Cap Div mode,
change the CPOUT voltage by changing Vout_set to 2x the CPOUT target voltage.
To transition from low power to high power operation, follow the procedure outlined. Low power operation is with
the Capacitor Divider in Bypass mode. Check the Cap Divider mode by using the “Basic 3” tab, and reading the
Cap Div mode (see Figure 15).
Figure 15. Check Cap Divider Mode
Check the VOUT voltage by measuring the VOUT test point or by using the GUI (“Basic 2” tab, Monitoring: Vout,
and Vout_set). Once it is determined that the P9412 is in Bypass mode and the VOUT voltage is set to less than
12V, reduce the output load to 0mA.
Referring to Figure 16: select the QC tab, click the CD box, and then press the “Set Mode” button [step 1]. This
is in preparation to set the P9247 QC TX to a higher input voltage and higher power transfer operation. By
clicking the “Set Mode” button, the GUI is requesting a transition from Bypass mode to Cap Divider mode
operation (see Figure 2). Verify Cap Divider operation by checking the voltage at VOUT and at CPOUT. The
voltage at CPOUT should be half of the voltage at VOUT. Note that the Iout check field is indicating “Add load”
[step 2], this is normal and prevents the transition to high power operation (or the increase of RX Vout and TX
Vin voltages) without first adding a 200mA load to CPOUT. The 200mA load is recommended to make the output

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voltage transition smoother and to reduce the coupled spikes that occur when the TX input power supply is being
adjusted.
Figure 16. Enable Cap Divider Mode Operation
Add a 200mA load and click the “Continue” button [step 3]. By clicking the “Continue” button while the P9412 is
placed on the P9247 QC TX, a “Load OK” message should be displayed as shown in Figure 17. This indicates
that the GUI is now able to change the P9412’s VOUT voltage and send a command to the P9247 to change the
TX input voltage after the time interval given. Note that if the RX Vout voltages indicate a maximum of 12V, it is
necessary to press the “Default” button. The sequence the GUI follows for increasing the RX Vout and TX VIN
voltages is: 1. Increase Vout_set to the level indicated; 2. Wait for the designated interval for the RX Vout to
stabilize (Note: the wait period should not be less than 100ms for best results); 3. Increase the TX Vin voltage to
increase the power transferred.
Figure 17. P9412 Successfully Enters Cap Div. Mode and is Ready to Transition to High-Power Operation
[1
[2
[3
[1
[2
[3

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To increase the RX VOUT voltage and TX input voltage make sure all the Up and Down step boxes are
checked. Then press the “Incr” button. The arrow direction indicates the sequence of the steps from Up1 to
Up6. The step-up sequence may take several seconds to complete. Similarly, the system can be set back to
9Vout operation by clicking the “Decr” button.
Figure 18. P9412 Transition to High Power Operation
In addition to using the Incrand Decrbuttons it is possible to manually control the sequence using the “Single
step incr” buttons. For example, to increase the RX Vout from 9V to 12V, press the “2” button. The sequence
the GUI follows for increasing the RX Vout voltage is: 1. Increase Vout_set to the 12V; 2. Wait for the 2 second
interval for RX Vout to stabilize; 3. Increase the TX Vin voltage to 12V to increase the power transferred.
Figure 19. Using the GUI to Manually Increase the RX Vout Voltage
[1
[2
[3

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Similarly, the RX VOUT voltage can be manually decreased by using the “Single step decr” buttons. For
example, to decrease the RX Vout from 18V to 16V, press the “4” button. The sequence the GUI follows for
decreasing the RX Vout voltage is: 1. Decrease TX Vin voltage from17V to 16V to lower the power transferred;
2. Wait for the 2 second interval for TX Vin and RX Vout to stabilize; 3. Decrease the RX Vout voltage to 16V.
Figure 20. Using the GUI to Manually Decrease the RX Vout Voltage
1.2.4. Using the GUI to Run in TX Mode
Use the following procedure to enter TX mode operation:
1. Remove the P9412 from the TX pad. Remove load from the CPOUT pin.
2. Connect an external 7V Power supply to CPOUT and GND.
3. Turn on the external power supply.
[3
[2
[1

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4. Select the “Basic 1” Tab and check that the GUI is connected to the P9412 demo board by pressing the
“Clear all” and then the “Read 1 time” button on the “Basic 1” tab. Check that the firmware revision and date
code are reading correctly and that the Vrect, Vout, and VCPout voltages are all ~0V and that Iout ~0mA.
Figure 21. Basic Registers Initial Read Back; Before TX Mode Entry
If the registers look correct then change to the TX mode tab and press the “TX mode” button. Then press the
“RD all” button. The Vrect, Vout, and VCPout voltages should be near the external power supply voltage applied
to CPOUT as shown. The Iout current should be low since the RX is not placed on the P9412 coil. Verify “TX
mode” has been entered.
Figure 22. Tx Mode Entry, Without an Rx Placed on the P9412 Coil; Vrect and Vout Voltage Read Back ~7V
Hover over register
value to access
tool tip
Button switches
between enable /
disable TX mode

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5. Place the Rx on the P9412’s coil and check the output voltage of the Rx. If a connection is established, there
should be ~5V present on the Rx output. Continue to monitor the P9412 Vrect, Vout, Iout, and RX freq
registers.
Figure 23. Tx Mode, With an Rx Placed on the P9412 Coil; Use the GUI to Monitor the Status
To exit TX mode operation, either use the “TX mode cmd” register to write a 0x02 to register 0x4F or the “Dis TX
mode” button. Verify by reading the OP mode register 0x4C – it should read 0x00 or AC missing (see Figures 24
and 25).
Figure 24. Exit Tx Mode, With an Rx Placed on the P9412 Coil; Use the GUI to Send Exit Command