Renesas RC22312A User manual

Evalua
tion Board Manual
RC22312A/RC32312A
Evaluation Board
R31UH0022EU0100 Rev.1.00
Mar 28, 2023
Page 1
© 2023 Renesas Electronics
The RC22312A/RC32312A Evaluation Board (EVB)
is designed to support users evaluating high
performance synthesizer and jitter attenuator
applications. This document describes the following:
■Basic hardware and GUI setup using Renesas IC
Toolbox (RICBox™) software
■Board power-up instructions
■Instructions to get active output signals using a
provided configuration file
■Hardware modifications required for different
conditions
Board Contents
■RC22312A/RC32312A evaluation board
■EVB manual
■Configuration software (installable plugin for
RICBox)
■Configuration example file for four built-in device
settings
■Board schematic and BOM
Features
■Four differential clock inputs
■Twelve differential clock outputs
■On-board EEPROM stores startup-configuration
data
■XIN terminal can use laboratory signal generator
or OCXO/TCXO/XO components and board
■Laboratory power supply connectors
■USB-C power supply
■Serial port for configuration and register read out
Computer Requirements
■USB 2.0 or USB 3.0 interface
■Processor: minimum 1GHz
■Memory: minimum 512MB; recommended 1GB
■Available disk space: minimum 600MB (1.5GB 64-
bit); recommended 1GB (2GB 64-bit)
Figure 1. RC32312A Block Diagram

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Contents
1. Functional Description.................................................................................................................................4
1.1 Operational Characteristics ..................................................................................................................4
1.2 Hardware Setup and Configuration ......................................................................................................4
1.2.1. Power and USB-C Connections to Computer Host................................................................8
1.2.2. Overdrive the XIN with an External Signal .............................................................................9
1.2.3. On-board Crystal Mount.......................................................................................................10
1.2.4. On-board XO Mount.............................................................................................................11
1.2.5. Clock Inputs..........................................................................................................................13
1.2.6. Clock Outputs.......................................................................................................................14
1.2.7. Serial Connection.................................................................................................................15
1.2.8. On-board EEPROM..............................................................................................................15
1.2.9. GPIO DIP Switch Selectors..................................................................................................17
1.3 Software Setup and Configuration......................................................................................................17
1.3.1. Prepare the Software ...........................................................................................................17
1.3.2. Launch the GUI....................................................................................................................18
1.3.3. Configure the Evaluation Board............................................................................................20
2. Board Design..............................................................................................................................................21
2.1 Bill of Materials (BOM)........................................................................................................................23
3. Typical Performance Graphs.....................................................................................................................26
4. Ordering Information..................................................................................................................................27
5. Revision History .........................................................................................................................................27
Figures
Figure 1. RC32312A Block Diagram.......................................................................................................................1
Figure 2. Evaluation Board.....................................................................................................................................5
Figure 3. USB Power Jumpers...............................................................................................................................8
Figure 4. External 5V Board Input..........................................................................................................................9
Figure 5. External 5V Schematic............................................................................................................................9
Figure 6. J90 Board Input.......................................................................................................................................9
Figure 7. VDD Jumper Bypass Schematic .............................................................................................................9
Figure 8. XIN Pin Overdrive Schematic................................................................................................................10
Figure 9. Crystal Mount Schematic.......................................................................................................................10
Figure 10. EVB XO Pads......................................................................................................................................11
Figure 11. XO Path Connection Schematic..........................................................................................................11
Figure 12. XO Schematic .....................................................................................................................................12
Figure 13. XO OE Pin Header Schematic............................................................................................................12
Figure 14. Input Clock Termination Schematic.....................................................................................................13
Figure 15. Input Clock Pull-up/down Schematic...................................................................................................13
Figure 16. Output Type Options...........................................................................................................................14
Figure 17. LVDS Input Clock Termination............................................................................................................14
Figure 18. HCSL Input Clock Termination............................................................................................................14
Figure 19. Communication Setup for I2C Mode ....................................................................................................15

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Figure 20. EEPROM in Socket.............................................................................................................................15
Figure 21. EEPROM Pin Description....................................................................................................................15
Figure 22. EEPROM Schematic...........................................................................................................................16
Figure 23. EEPROM Connection Resistors..........................................................................................................16
Figure 24. FTDI to I2C Communication Jumpers..................................................................................................16
Figure 25. GPIO Schematic and EVB DIP Switches............................................................................................17
Figure 26. Create New Project in RICBox............................................................................................................18
Figure 27. Selecting RC32312A Device GUI in RICBox.......................................................................................18
Figure 28. RICBox Wizard Navigation..................................................................................................................19
Figure 29. RICBox GUI Menu Buttons..................................................................................................................19
Figure 30. Connect to the Device in RICBox........................................................................................................20
Figure 31. Connected Button................................................................................................................................20
Figure 32. Program Button...................................................................................................................................20
Figure 33. RC22312A/RC32312A Evaluation Board (Top)...................................................................................21
Figure 34. RC22312A/RC32312A Evaluation Board (Bottom) .............................................................................22
Figure 35. Phase Noise 312.5MHz Output Synthesizer Mode .............................................................................26
Figure 36. Phase Noise 312.5MHz Output Jitter Attenuation Mode.....................................................................26

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1. Functional Description
The evaluation kit is used to demonstrate the RC22312A/RC32312A, a fully integrated clock
synthesizer/generator and clock jitter attenuator. The kit can be used to evaluate major parameters including
phase noise, spurious attenuation, clock frequency, output skew, phase alignment, device timing, and the signal
waveform. The device on the board accepts any input frequency from 1kHz to 1GHz.
The RC22312A/RC32312A consists of a single APLL and DPLL design that allows for two separate frequency
domains. The APLL can be used independently of the DPLL to generate synthesized clocks at the outputs that
track the frequency of the input at the XIN pin. The DPLL can be used for jitter attenuation, clock filtering, and
frequency translation while tracking clocks from the CLKIN pins. The DPLLs provide a programmable bandwidth
and a DCO function for real-time frequency/phase adjustment.
1.1 Operational Characteristics
The board is equipped with on-board LDOs that require a 5V supply. If connecting to a high-speed USB
interface, the evaluation board may be powered directly from the USB connection. The board is designed to
operate over the industrial temperature range from -40°C to +85°C, ambient temperature.
It is recommended to use proper grounding during board operations to avoid ESD damage to the EVB.
1.2 Hardware Setup and Configuration
The following sections describe the crystal, input clock, serial, GPIO, and output and power functions used for
setting up device testing.

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Figure 2. Evaluation Board
Refer to Table 1 and Figure 2 for the RC22312A/RC32312A evaluation board pin descriptions and functions.
Table 1. RC22312A/RC32312A Evaluation Board Pin Descriptions
Item No. Name
On-Board
Connector Label Function
1
R22312A/RC32312A
U4
Evaluation device, 64-VFQFPN.
2
I2C for FTDI or Aardvark
Connector J119 6-pin header of I2C connector for SCL and SDA pins.
3 USB Interface U16
USB type jack for connection with the computer and
interaction with RICBox software.
4
XIN SMA Connector
J2
External clock input signal to XIN pin.

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Item No. Name
On-Board
Connector Label Function
5
CLKIN0/nCLKIN0 –
CLKIN3/nCLKIN3
J15, J24, J27, J37,
J39, J50, J59, J73
External clock input connectors for jitter attenuation
functionality.
6 OUT[3:0]
J13, J16, J18, J22,
J23, J27, J28, J33 SMA output test points.
7 OUT[7:4]
J35, J38, J40, J43,
J47, J51, J54, J58 SMA output test points.
8 OUT[11:8]
J60, J67, J70, J75,
J77, J79, J80, J83 SMA output test points.
9
DIP Switches
SW1
GPIO pull-up/down control.
10
VDD 5V Input Connector
J123
5V input supply to voltage regulators.
11
GND Connector
J125
Board ground for external supply.
12
Direct Supply Connector
J90
Voltage supply connector for direct pin supply.
13
I2C/SPI Pin Control Pull-up/down
Resistors
J244, J245, J246,
J247, J248
SDA_SDIO, SCL_SCLK, SDO_A1, NCS_A0, LOCK pin 10kΩ
to GND or VDDD33_SERIAL.
14
VDDXO_DCD, VDD_VCO,
VDDO0, VDDO1_FOD0, VDDO2,
VDDO3 Voltage Selection
J98, J100, J111,
J109, J107, J105 1.8V regulator jumper selection.
15
VDD_GPIO, VDDO4, VDDO5,
VDDO6, VDDO7, VDDO8_FOD1
Voltage Selection
J92, J103, J101,
J99, J97, J94 1.8V regulator jumper selection.
16
VDDO9, VDDO10_FOD2,
VDDO11, VDD_CLK,
VDDD33_DIA, VDDD33_SERIAL
Voltage Selection
J110, J108, J106,
J104, J102, J100 1.8/3.3V regulator jumper selection.
17 EEPROM Address Selection J74
EEPROM pins A1 and A2 pull-up/down to GND or
VDDD33_SERIAL.
18
EEPROM Socket
U5
8-pin dip EEPROM socket.
19
EEPROM WP
J71
Pull-up/down EEPROM write-protect pin.
20 FTDI I2C/SPI Controller U17
I2C/SPI control interface between PC and
RC22312A/RC32312A.
21
I2C/SPI Path Connection
J120
Combine or fanout SDI/SDO lines from the FTDI chip.
22
Level Translator Enable
J243
Enable/Disable I2C level translators.
23 I2C Pull-ups and Path Connectors J61, J62, J65, J66
Connect level translators SDA/SCLK to
RC22312A/RC32312A pins and pull-up to VDDD33_SERIAL.
24
Voltage Regulators
U13, U14, U15
Receive 5V input and supply 1.8/3.3V to EVB power domains.
25 FTDI Voltage Selection J259
Control FTDI voltage source between USB input and 5V board
supply.
26
I2C Pull-up Resistors
J117, J118
Pull-up to FTDI 3.3V
27 LDO Voltage Input Selection J124
Select EVB LDO input voltage source between bench or USB
supply.

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For proper functionality out of the box, the jumpers on board should be placed to allow the correct voltages at
each LDO and domain. The jumpers should be arranged as described in Table 2.
Table 2. Default Jumper Configurations
Label/Function
Jumper
Default Orientation
Connect nCS_LS to IC from FTDI
J45
OFF
Connect MISO_LS to IC from FTDI
J46
OFF
Connect SCL_SCLK_LS to IC from FTDI
J61
ON
Connect SDA_SDIO_LS to IC from FTDI
J62
ON
I2C Pull-up to VDDD33_SERIAL
J65
ON
I2C Pull-up to VDDD33_SERIAL
J66
ON
EEPROM Write Protect
J71
OFF
EEPROM Address Select
J74
OFF
VDD_GPIO
J92
Either 1P8V_0 or 1P8V_1
VDDO8_FOD1
J94
Either 1P8V_0 or 1P8V_1
VDD_VCO
J96
Either 1P8V_0 or 1P8V_1
VDDO7
J97
Either 1P8V_0 or 1P8V_1
VDD_XO_DCD
J98
Either 1P8V_0 or 1P8V_1
VDDO6
J99
Either 1P8V_0 or 1P8V_1
VDDD33_SERIAL
J100
3P3V
VDDO5
J101
Either 1P8V_0 or 1P8V_1
VDDD33_DIA
J102
Either 1P8V_0 or 1P8V_1
VDDO4
J103
Either 1P8V_0 or 1P8V_1
VDD_CLK
J104
Either 1P8V_0 or 1P8V_1
VDDO3
J105
Either 1P8V_0 or 1P8V_1
VDDO11
J106
Either 1P8V_0 or 1P8V_1
VDDO2
J107
Either 1P8V_0 or 1P8V_1
VDDO10_FOD2
J108
Either 1P8V_0 or 1P8V_1
VDDO1_FOD0
J109
Either 1P8V_0 or 1P8V_1
VDDO9
J110
Either 1P8V_0 or 1P8V_1
VDDO0
J111
Either 1P8V_0 or 1P8V_1
I2C Pull-up
J117
ON
I2C Pull-up
J118
ON
Bus Communication Selection J119
Between FTDI_SDO and AVK_SDA and between FTDI_SCL
and AVK_SCL
SDO and SDI Connection for I2C
J120
Between FTDI_SDO_J and FTDI_SDI_J

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Label/Function
Jumper
Default Orientation
GND
J121
OFF
Enable I2C Pull-ups
J243
Between FTDI_3P3V and Center
SDA_SDIO
J244
OFF
SCL_SCLK
J245
OFF
SDO_A1
J246
OFF
NCS_A0
J247
Between center and HI
LOCK_C
J248
OFF
Note: 1P8V_0 and 1P8V_1 refer to separate LDO supply on the board. They can be used to isolate pin supplies
from each other for performance optimization.
1.2.1. Power and USB-C Connections to Computer Host
The EVB is connected to a computer host via the USB3.0 to USB-C cable. It is recommended that the cable is
connected to a USB3.0 port. However, a USB2.0 port acceptable due to the RC22312A/RC32312A for I2C/SPI
communications only. The USB-C provides +5V as power source to the on-board regulators. The on-board
regulators support 3.3V and 1.8V voltages to the entire EVB. These voltages can be set by various jumpers
found around the RC22312A/RC32312A.
The RC22312A/RC32312A voltage source can be derived from the on-board voltage regulators for 3.3V, 1.8V,
or directly from the J90 banana connector with an external supply. The J90 connection can be used to measure
total supply current into pins as reference. When jumpers are used to select power from J90 connector, the USB
connection will still be required to connect RICBox.
■Power connection
●Set the power supply voltage to 5V and the current limit to 2A
●+5V (J123) = +5V
●GND (J125) = GND
■Expected current draw: ~ 0.7A
●After programming the device ~0.6A to 1A during normal operation depending on the device configuration
1.2.1.1. Power the Device with USB Connection
■Set jumper on J124 between pins 1 and 2
■Set jumper on J259 between pins 1 and 2
■Ensure that the EVB connects to a USB 3.0 port or newer
Figure 3. USB Power Jumpers

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1.2.1.2. Power the Device with External Power Supply Connection and On-board Voltage Regulators
■Set jumper on J124 between pins 2 and 3
■Set jumper on J259 between pins 2 and 3
■Ensure 5V at banana jack J123 and GND connection
Figure 4. External 5V Board Input
Figure 5. External 5V Schematic
Note: Allow for up to 2A of current with direct power supply. The device current will be increased during register
write and calibration.
1.2.1.3. Power the Device Pins with External Power Supply Connection J90
■Ensure 1.8V or 3.3V at banana jack J90 and GND connection depending on the power pin
■Change the corresponding domain jumper selection to VDD
Figure 6. J90 Board Input
Figure 7. VDD Jumper Bypass Schematic
Note: J90 can supply voltage for the entire device. If all voltage pin jumper settings are configured for VDD and
the input voltage is 1.8V.
Note: All individual voltage domains run at 1.8V. Only VDDD33_SERIAL and VDDD33_DIA are compatible with
3.3V. Supplying 3.3V to any other domain may cause damage to the RC22312A/RC32312A device.
1.2.2. Overdrive the XIN with an External Signal
The RC22312A/RC32312A device can support between 25MHz–80MHz on the XIN (crystal oscillator input) pin.
There are four options for providing an input signal to the device XIN pin:
■An external signal (J2 SMA connector) typically from a signal generator; see section 1.2.1). This option is
configured by default.
■An on-board crystal mount (U3); see section 1.2.2
■Two on-board XO mounts (U27, U29); see section 1.2.3
To overdrive XIN with an external signal (see Figure 8):
1. Populate C1 with 0.1µF capacitor to ensure that J2 has a connected path to the RC32312A device.

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2. Depopulate C2, C3, R398, and R424 to ensure that excess trace is not used.
3. Populate R4 with 50Ωfor input termination (ensure signal is >~1.3V amplitude).
4. Place input clock signal at J2 and ensure that the signal is within specification for the XIN pin.
Figure 8. XIN Pin Overdrive Schematic
1.2.3. On-board Crystal Mount
The crystal mounting position can only be used if there is no other signal present on the XIN path (see Figure 9).
In order to setup the evaluation board for crystal input:
1. Depopulate C1, R398, R423, and R424 to ensure there is no excess trace in the XIN pin.
2. Populate C2 and C3 to externally tune the input crystal frequency.
Note: The EVB stray capacitance has been measured to be ~8.24pF.
3. Mount crystal to U3. Remove R400 or R402 if the crystal only has 3 pads.
Figure 9. Crystal Mount Schematic

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1.2.4. On-board XO Mount
There are two options on the evaluation board to allow for an XO to be mounted. PositionsU27 and U29 are
connected in parallel and should only be used one at a time. For an XO to work properly at U27 and U29, the
following must be setup (see Figure 10, Figure 11, Figure 12 and Figure 13):
Figure 10. EVB XO Pads
1. Populate R398 with 0 Ohms.
2. Depopulate C1, U3, R423, R424, C1, and C2.
Figure 11. XO Path Connection Schematic
3. Populate R428 if pin 5 of the XO is being used as output.
4. Ensure that the XO output is below ~1.3V amplitude signal in order to support proper XIN pin characteristics.
a. R416 can be populated with a low value resistor (33Ω) to reduce the XO output amplitude. Otherwise,
R416 can be populated with 0 Ohms.

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5. R405 and R406 can be populated to adjust the common mode voltage of the XO output.
Figure 12. XO Schematic
6. Use jumper on J253 – J256 to pull the XO output enable pin high or low depending on the XO datasheet.
Figure 13. XO OE Pin Header Schematic

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1.2.5. Clock Inputs
The RC32312A can accept four differential clock inputs to be used as a jitter attenuator source. To enable
proper connection, make sure the input termination resistor setup corresponds to the input signal that is
connected. The evaluation board default termination setup has 50Ωto GND at each leg.
Figure 14. Input Clock Termination Schematic
The RC32312A contains internal AC-coupling for LVDS, HCSL, LVCMOS signals. Supported frequency ranges
of the clock inputs are 1kHz to 1GHz in differential mode, and 1kHz to 250MHz in single-ended mode.
Pull-up and pull-down resistors apart of the CLKIN path can be used for common mode voltage adjustments.
Figure 15. Input Clock Pull-up/down Schematic
Note: Clock inputs are only used with RC32312A devices.

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1.2.6. Clock Outputs
Each of the 12 differential output pairs can be programmed to LVDS, HCSL or CMOS logic type.
■The HCSL mode supports HCSL by default and can be modified to support other modes by changing the
amplitude and enabling/disabling the internal termination.
■For CMOS output type, output phase of each pin can be programmed to be 180 degrees out-of-phase, in-
phase, or single pin output.
■LVDS outputs can be configured to 350mV or 400mV swing up to 1V common mode voltage.
■Each output can also be tri-stated when not being used.
Output terminations on the evaluation board can be populated to support the different output types.
Figure 16. Output Type Options
Place 50Ωacross each leg, for a total 100Ωacross, to terminate for LVDS.
Figure 17. LVDS Input Clock Termination
Place 50Ωto GND at each leg for HCSL terminations.
Figure 18. HCSL Input Clock Termination

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1.2.7. Serial Connection
The EVB can be connected to a computer via a USB3.0 to USB-C connector. The on-board USB-to-MPSSE
Bridge (FTDI FT232HQ) can handle the data communication. The +5V from the USB-C powers the on-board
regulators (see section 1.2.1.1).
The Bus Source connector J119 is used to select the source of the communication bus. The bus will be I2C for
most communication but can also be SPI for specific tests. Pins 1 and 2 in J119 are SDA and SCL from the FTDI
chip. Pins 3 and 4 pass the SDA and SCL to the I2C level shifter. To use the on-board FTDI chip, install jumpers
on pins 1–3 and 2–4. The board will be shipped with these jumpers installed. Theoretically, any I2C adapter can
be connected to pins 3 and 4 for SDA and SCL. Pin 6 can be used as the ground connection for the I2C
connection. Pins 3, 4, 5 and 6 are arranged such that a Total Phase I2C Host Adapter (part number: TP240141)
can be plugged onto pins 3, 4, 5 and 6 only (see Figure 19).
For default I2C operation, jumpers are installed on pins 1–3 and 2–4 (see jumper J119 in Table 2).
Figure 19. Communication Setup for I2C Mode
Note: For SPI operation instructions, contact Renesas support.
1.2.8. On-board EEPROM
The EVB also supports an external EEPROM IC for loading of an RC22312A/RC32312A configuration
programmed into the EEPROM as an option. To load the configurations from EEPROM, the EEPROM load
enable bit must be set in device OTP. If the enable bit is not set, the EEPROM load will be skipped.
The EVB provides a socket of 8-lead DIP8 SOIC-8 socket (Figure 20) so other EEPROM devices of different
memory size can be tested.
Figure 20. EEPROM in Socket
Figure 21. EEPROM Pin Description
RC22312A/
RC32312A
I2C
Level
Shifter
1 2
1 2
2 64
1 53
= Jumper
J62
SDA
3.3V / 1.8V
3.3V / 1.8V
SCL
GND
SCL_3.3V
SDA_3.3V
J119
SDA
SCL
FTDI
Chip
USB
Type-C
Port
J61

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Figure 22. EEPROM Schematic
The A1 and A2 pins are the EEPROM address inputs that can be pull either high or low using jumpers at J74 to
define the device address. By default, jumpers can be removed so that A1 and A2 are left floating as they are
internally pulled down to GND in most EEPROM devices.
The WP pin is the write-protect input. When the WP pin is pulled down to GND (Low), the EEPROM can have
normal write operations. When it is pulled up directly to VCC (High), all write operations are inhibited. The WP pin
can be controlled with a jumper at J71.
To establish a connection to the EEPROM, the SDA and SCL traces must be connected to the FTDI
communication path. Populate R122 and R124 with 0 Ohms to make the connection. This will allow software
features like RICBox to communicate with the EEPROM device.
Figure 23. EEPROM Connection Resistors
When the device attempts to load an EEPROM configuration during start-up, the FTDI I2C controller can cause
interference. The FTDI device can be removed from the I2C trace path by removing jumpers J61 and J62. This
will also disconnect RICBox from communicating with the RC22312A/RC32312A device.
Figure 24. FTDI to I2C Communication Jumpers

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1.2.9. GPIO DIP Switch Selectors
The EVB has one DIP switch set (SW1) to support GPIO pins on RC22312A/RC32312A device. GPIOs 0–6 can
support a two-level input (low/high). The middle position of the DIP switches leaves the pin open so GPIOs can
be controlled with internal pull-up and pull-down resistors. Move to the ‘+’ side to pull the pin high and move to
the ‘-‘ side to pull the pin low. LEDs correspond to each GPIO to show the pin state.
Figure 25. GPIO Schematic and EVB DIP Switches
1.3 Software Setup and Configuration
1.3.1. Prepare the Software
For software installation instructions, see the Renesas IC Toolbox Software Manual, sections 1 and 11.

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1.3.2. Launch the GUI
After successfully installing the Renesas IC Toolbox software, launch the software from the Windows <start>
menu at the bottom-left corner of the screen.
1. Click Start > RICBox to open the initial RICBox window.
2. Click Create new project.
Figure 26. Create New Project in RICBox
3. Select FemtoClock3 from the “Select a Product Family” list.
4. Select the product variant to evaluate, then click OK. In this example, the RC32312A is selected.
Figure 27. Selecting RC32312A Device GUI in RICBox

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5. Follow the on-screen wizard (see Figure 28) to configure the device for general evaluation starting from
“Inputs”, then “DPLL”, and finally ”Outputs”.
Figure 28. RICBox Wizard Navigation
6. Click on the Finish button after the settings are decided and to review the control panel page.
7. Use the side panel menu buttons (see Figure 29) to navigate through the GUI for all five separate pages.
Figure 29. RICBox GUI Menu Buttons

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1.3.3. Configure the Evaluation Board
1. To establish communication between the EVB and the GUI, click the Not Connected button in the lower right
corner, then click Connect.
Figure 30. Connect to the Device in RICBox
2. Once the RICBox connection is established to the EVB, the “Not Connected” button will change to
“Connected”.
Figure 31. Connected Button
3. Click the Program button to write all the changed registers from the GUI to the on-board device. Any register
changes made after clicking the “Program” button will occur in real-time and the device will update.
Figure 32. Program Button