Renesas RTK00V2XRC7746SFS User manual

All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp.
RTK00V2XRC7746SFS
User’s Manual: Hardware
Rev.1.3 September. 2017
ASD-B-16-0247

Hardware Design Specification
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CONTENTS
1OVERVIEW ..........................................................................................................................................9
1.1 FEATURES............................................................................................................................................ 10
1.1.1 Features of the Tethys Board ..................................................................................................... 10
1.1.2 Functions of the Tethys Board ....................................................................................................11
1.2 USAGE NOTES...................................................................................................................................... 12
1.2.1 Specifications of the Tethys Board ............................................................................................. 12
1.3 BOARD CONFIGURATION ....................................................................................................................... 13
1.3.1 Block Diagram of the Tethys Board ........................................................................................... 13
2OPERATING CONDITION AND ANTENNA CHARACTERISTIC .......................................................14
2.1 OPERATING CONDITION ......................................................................................................................... 14
3SPECIFICATIONS OF INTERFACE MODULES ON THE TETHYS BOARD.......................................15
3.1 MODE SETTING .................................................................................................................................... 15
3.1.1 Specifications ............................................................................................................................. 15
3.1.2 MD0 Pin -Selection of Free-Running Mode or Step-Up Mode .................................................. 15
3.1.3 MD [3:1] Pins-Selection of Boot Device ..................................................................................... 15
3.1.4 MD4 Pin-Selection of CS0 Space Size ...................................................................................... 15
3.1.5 MD5 Pin-Reserved ..................................................................................................................... 15
3.1.6 MD [7:6] Pins-Selection of Master Boot Processor ................................................................... 15
3.1.7 MD8 Pin-Selection of Area 0 Space Data Bus Width ................................................................ 16
3.1.8 MD9 Pin-Selection of Crystal Resonator or Crystal Oscillator ................................................... 16
3.1.9 MD21, MD20, MD11, MD10, and MDT [1:0] Pins-Switching of JTAG, SDHI1, and SDHI2 ....... 16
3.1.10 MD [14:13] Pins-Frequency Mode Setting ................................................................................. 17
3.1.11 Initial Values of Mode Setting Pins on Tethys Board ................................................................. 17
3.2 DDR3-SDRAM INTERFACE (DBSC)...................................................................................................... 17
3.2.1 Specifications ............................................................................................................................. 17
3.2.2 Signal Connections between R-Car W2H and DDR3-SDRAMs ................................................ 18
3.2.3 Block Diagram ............................................................................................................................ 19
3.3 SPI-FLASH INTERFACE (QSPI)............................................................................................................... 20
3.3.1 Specifications ............................................................................................................................. 20
3.3.2 Block Diagram ............................................................................................................................ 20
3.4 AUDIO CODEC INTERFACES (SSI0, SSI1) ................................................................................................ 21
3.4.1 Specifications ............................................................................................................................. 21
3.4.2 Block Diagram ............................................................................................................................ 21
3.5 EMMC MEMORY INTERFACE (EMMC) ................................................................................................... 22
3.5.1 Specifications ............................................................................................................................. 22

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3.5.2 Block Diagram ............................................................................................................................ 22
3.6 SD CARD HOST INTERFACE (SDHI2)...................................................................................................... 23
3.6.1 Specifications ............................................................................................................................. 23
3.6.2 Block Diagram ............................................................................................................................ 23
3.7 MINI PCI EXPRESS INTERFACE............................................................................................................... 24
3.7.1 Specifications ............................................................................................................................. 24
3.7.2 The Mini PCIE connector signal configuration are shown as below: ......................................... 24
3.7.3 Block Diagram ............................................................................................................................ 28
3.8 USB TO UART..................................................................................................................................... 29
3.8.1 Specifications ............................................................................................................................. 29
3.8.2 Block Diagram ............................................................................................................................ 29
3.9 USB2.0 INTERFACE .............................................................................................................................. 30
3.9.1 Specifications ............................................................................................................................. 30
3.9.2 Block Diagram ............................................................................................................................ 31
3.10 DEBUG INTERFACE ............................................................................................................................... 32
3.10.1 CPU debug ................................................................................................................................. 32
3.10.2 CPU JTAG2 debug ..................................................................................................................... 33
3.10.3 MCU debug ................................................................................................................................ 34
3.11 GYRO/G-SENSOR.............................................................................................................................. 35
3.11.1 Specifications ............................................................................................................................. 35
3.11.2 Block Diagram ............................................................................................................................ 35
3.12 I2C INTERFACES................................................................................................................................... 36
3.12.1 Specifications ............................................................................................................................. 36
3.12.2 List of Slave Addresses .............................................................................................................. 37
3.12.3 Block Diagram ............................................................................................................................ 37
3.13 GPS MODULE ...................................................................................................................................... 38
3.13.1 Specifications ............................................................................................................................. 38
3.13.2 Block Diagram ............................................................................................................................ 38
3.14 CANAND FLEXRAY INTERFACE ............................................................................................................. 39
3.14.1 Specifications ............................................................................................................................. 39
3.14.2 Block Diagram ............................................................................................................................ 39
3.15 LEDS AND SWITCHES ........................................................................................................................... 41
3.15.1 Specifications ............................................................................................................................. 41
3.16 CONNECTION BETWEEN CPUAND MCU................................................................................................. 44
3.16.1 Specifications ............................................................................................................................. 44
3.16.2 Block Diagram ............................................................................................................................ 44
3.17 CLOCK SYSTEM .................................................................................................................................... 45
3.17.1 Clock Signals Supplied to the R-Car W2H ................................................................................ 45
3.17.2 Differential Clock Signals Supplied to the R-Car W2H .............................................................. 45

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3.17.3 Clock Signals Supplied to Devices Other than R-Car W2H ...................................................... 45
3.17.4 Block Diagram ............................................................................................................................ 46
3.18 EXTERNAL INTERRUPTS ........................................................................................................................ 47
3.18.1 Specifications ............................................................................................................................. 47
3.18.2 Block Diagram ............................................................................................................................ 47
3.19 RESET SYSTEM..................................................................................................................................... 48
3.19.1 Specifications ............................................................................................................................. 48
3.19.2 Block Diagram ............................................................................................................................ 48
3.19.3 Reset Sequence ........................................................................................................................ 49
3.20 POWER SYSTEM.................................................................................................................................... 50
3.20.1 Specifications ............................................................................................................................. 50
3.20.2 Block Diagram ............................................................................................................................ 51
3.20.3 Power Sequence ........................................................................................................................ 52
4MEMORY MAP...................................................................................................................................53
4.1 SPECIFICATIONS ................................................................................................................................... 53
4.2 FUNCTION ........................................................................................................................................... 57
4.2.1 Control the power of the Tethys Custom Board. ........................................................................ 57
4.2.2 Realize the UART with the baud rate of 115200 ........................................................................ 58
4.2.3 Realize an asynchronous serial with baud rate of 1M between RH850 and CPU. ................... 59
4.2.4 Make CAN0 and CAN1 working with baud rate of 1M ............................................................... 59
5OUTLINE DIAGRAMS OF THE TETHYS BOARD..............................................................................60
5.1 TETHYS BOARD DIMENSION................................................................................................................... 60
5.2 THE WEIGHT OF THE TETHYS BOARD ...................................................................................................... 60
5.3 TETHYS ID DIMENSION ......................................................................................................................... 61
5.4 TETHYS ASSEMBLY ............................................................................................................................... 63
6BOARD CONNECTORS......................................................................................................................67
6.1 TOPSIDE CONNECTORS......................................................................................................................... 67
6.2 BOTTOM SIDE CONNECTORS................................................................................................................... 68
6.3 THE DETAILS OF CONNECTORS ............................................................................................................... 69
7APPENDIX..........................................................................................................................................71
7.1 USB DEBUG CABLE .............................................................................................................................. 71
7.2 ACADAPTER ....................................................................................................................................... 72
7.2.1 Specifications ............................................................................................................................. 72
7.2.2 Mechanic Size and Picture ........................................................................................................ 73
7.3 GPSANTENNA ..................................................................................................................................... 75
7.3.1 Specification ............................................................................................................................... 75

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7.4 V2XANTENNA1WITH 2M CABLE ........................................................................................................... 77
7.4.1 Specification ............................................................................................................................... 77
7.5 V2XANTENNA(ROD TYPE).................................................................................................................. 84
7.5.1 Specification ............................................................................................................................... 84
7.6 RF CABLE ........................................................................................................................................... 91
7.6.1 Specification ............................................................................................................................... 91
7.7 JTAG DEBUG BOARD WITH FPC CABLE ................................................................................................. 92
7.7.1 Specifications ............................................................................................................................. 92
7.7.2 Block Structure ........................................................................................................................... 92
7.7.3 Block Diagram ............................................................................................................................ 93
7.8 V2X CONNECTION BOARD..................................................................................................................... 94
7.8.1 Board Structure .......................................................................................................................... 94
7.8.2 Block Diagram ............................................................................................................................ 95
7.8.3 Block dimension ........................................................................................................................... 95
7.9 SUB BOARD TORTUGAWIRELESS MODULE BOARD DIMENSION ................................................................... 96
7.9.1 RF characteristic ........................................................................................................................ 96
7.9.2 Board Dimension ....................................................................................................................... 98
7.10 SIDE COVER OPTION OF CASE ............................................................................................................... 100
7.11 ACRONYMS AND ABBREVIATIONS ........................................................................................................ 101
8REGULATORY WARNING STATEMENTS ........................................................................................102
9EU DECLARATION OF CONFORMITY (DOC).................................................................................104
10 MANUFACTURER INFORMATION..................................................................................................105
WEBSITE AND SUPPORT.......................................................................................................................106
NOTICE...................................................................................................................................................108

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Tables
Table 1 Features of the Tethys Board.......................................................................................................... 10
Table 2 List of Tethys Board Functions .......................................................................................................11
Table 3 Operating Condition...................................................................................................................... 14
Table 4 DDR3-SDRAM Interface Specifications......................................................................................... 18
Table 5 Signal Connections between R-Car W2H and DDR3-SDRAMs........................................................ 18
Table 6 SPI-Flash Interface Specifications.................................................................................................. 20
Table 7 SSI Codec Specifications............................................................................................................... 21
Table 8 eMMC Memory Interface (eMMC) Specifications........................................................................... 22
Table 9 Specifications of SD Card Host Interface (SDHI2) .......................................................................... 23
Table 10 USB to UART Specifications....................................................................................................... 29
Table 11 USB2.0 Interface ........................................................................................................................ 30
Table 12 CPU debug Specifications ........................................................................................................... 32
Table 13 CPU JTAG2 debug ..................................................................................................................... 33
Table 14 MCU debug Specification............................................................................................................ 34
Table 15 GYRO/G-SENSOR Specifications ............................................................................................... 35
Table 16 List of I2C Devices ..................................................................................................................... 36
Table 17 List of I2C Slave Addresses ......................................................................................................... 37
Table 18 CAN and Flexray Interface Specifications..................................................................................... 39
Table 19 DIP Switches default setting is as below table ............................................................................... 41
Table 20 Slide Switches default setting is as below table:............................................................................. 43
Table 21 List of Clock Signals and Crystals for the R-Car W2H................................................................... 45
Table 22 List of Differential Clock Signals Supplied to the R-Car W2H........................................................ 45
Table 23 List of Clocks and Crystals other than for R-Car W2H................................................................... 45
Table 24 External Interrupts Specifications................................................................................................. 47
Table 25 Reset System Specifications......................................................................................................... 48
Table 26 List of the Switching Controllers and Regulators on the Tethys Board ............................................. 50
Table 27 Antenna Specification for GPS module......................................................................................... 75
Table 28 Antenna Specification for V2X (2m cable).................................................................................... 77
Table 29 Antenna Specification for V2X (Rod Type)................................................................................... 84
Table 30 RF Cable Specification for GPS module & RF Board..................................................................... 91

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Figures
Figure 1 Block Diagram of the Tethys Board .............................................................................................. 13
Figure 2 Block Diagram of the DDR3-SDRAM Interface ............................................................................ 19
Figure 3 Block Diagram of the SPI-Flash Interface ..................................................................................... 20
Figure 4 Block Diagram of the Audio Codec Interface................................................................................. 21
Figure 5 Block Diagram of the eMMC Memory Interface............................................................................ 22
Figure 6 Block Diagram of the SDHI2 Interface ......................................................................................... 23
Figure 7 Block Diagram of Mini PCI Express Interface ............................................................................... 28
Figure 8 Block Diagram of the USB to UART ............................................................................................ 29
Figure 9 Block Diagram of the USB2.0 Interface ........................................................................................ 31
Figure 10 Block Diagram of the CPU debug............................................................................................... 32
Figure 11 Block Diagram of the CPU JTAG2 (SH-4AL) debug.................................................................... 33
Figure 12 Block Diagram of the MCU debug.............................................................................................. 34
Figure 13 Block Diagram of the GYRO/G-SENSOR................................................................................... 35
Figure 14 Block Diagram of the I2C Interfaces ........................................................................................... 37
Figure 15 Block Diagram of the GPS module ............................................................................................. 38
Figure 16 Block Diagram of the CAN and Flexray Interface ........................................................................ 39
Figure 17 Block Diagram of the Connection between CPU and MCU........................................................... 44
Figure 18 Block Diagram of the Clock system............................................................................................ 46
Figure 19 Block Diagram of the External Interrupts .................................................................................... 47
Figure 20 Block Diagram of the Reset System............................................................................................ 48
Figure 21 The Reset Sequence................................................................................................................... 49
Figure 22 Block Diagram of the Power System........................................................................................... 51
Figure 23 The Power Sequence.................................................................................................................. 52
Figure 24 The Tethys board dimension....................................................................................................... 60
Figure 25 TOP Side Connectors................................................................................................................. 67
Figure 26 Bottom side connectors.............................................................................................................. 68
Figure 27 Image of USB debug cable......................................................................................................... 71
Figure 28 Power Adapter ID LOG specification.......................................................................................... 74
Figure 29 Image of Power Adapter............................................................................................................. 74
Figure 30 Image of GPS Antenna from Bottom view................................................................................... 76
Figure 31 Image of GPS Antenna from Top view ........................................................................................ 76
Figure 32 V2X Antenna Test Chamber description ...................................................................................... 78
Figure 33 V2X Antennal test axis definition description .............................................................................. 79
Figure 34 V2X Antennal VSWR test character............................................................................................ 80
Figure 35 V2X Antennal 2D radiation pattern............................................................................................. 81
Figure 36 V2X Antennal 3D radiation pattern............................................................................................. 82
Figure 37 Image of V2X Antenna1 from Bottom view................................................................................. 83
Figure 38 Image of V2X Antenna1 from Top view ...................................................................................... 83

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Figure 39 V2X Antenna2 Test Chamber description .................................................................................... 85
Figure 40 V2X Antenna2 test axis definition description.............................................................................. 86
Figure 41 V2X Antenna2 VSWR test character........................................................................................... 87
Figure 42 V2X Antenna2 2D radiation pattern ............................................................................................ 88
Figure 43 V2X Antenna2 3D radiation pattern ............................................................................................ 89
Figure 44 Image of V2X Antenna2 (SMA rotate 90 degree) ......................................................................... 90
Figure 45 Image of V2X Antenna2 (SMA rotate 0 degree) ........................................................................... 90
Figure 46 RF Cable .................................................................................................................................. 91
Figure 47 JTAG Debug Board with FPC Cable for R-CAR W2H & RH850 MCU ......................................... 92
Figure 48 JTAG Debug Board block structure............................................................................................. 92
Figure 49 Block Diagram of the JTAG Debug Board................................................................................... 93
Figure 50 Top side view of V2X Connection board ..................................................................................... 94
Figure 51 Bottom side view of V2X Connection board................................................................................ 94
Figure 52 Block structure of V2X Connection board ................................................................................... 94
Figure 53 Block Diagram of the V2X Connection board.............................................................................. 95
Figure 54 Side cover option of case ......................................................................................................... 100
Appendix
Appendix 1 Acronyms and Abbreviations................................................................................................. 101

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1 Overview
The Tethys board is R-Car W2H-specific evaluation board that can be used to evaluate systems using the R-Car
W2H and to develop operating systems, device drivers, and applications. Using the Tethys board allows developers to
efficiently conduct required tasks such as evaluating the performance of R-Car W2H-based systems, thus greatly
reducing turn-around times in product development.
SD Card CN2
GPS Antenna CN7
HSM CN14
CAN&Flexray
CN6
Ethernet CN3
Audio jack
J1
USB CN1
DEBUG CN4
POWER Switch
SW18
POWER IN JACK
CN17 and CN18
Micro USB : CN16、CN10、CN5
ETNB CN13
D12 (GPS_LED)、D4、D6、D8、D10
CN9、CN8、CN12、CN11
SW1、SW2
SW11、SW10、SW9、SW8
SW16、SW15、SW14、SW13、SW4 (MCU reset)
D9、D7、D5、D3、D11 (GPS_LED)
SW5、SW6、SW7

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1.1 Features
1.1.1 Features of the Tethys Board
Table 1 Features of the Tethys Board
Item
Description
CPU
·U1:R-Car W2H
( Operating clock: ARM 1.0GHz(Max), SH-4AL 260MHz)
MCU
·U32:RH850F1H/F1L
( Operating clock: RH850F1H 120MHz, RH850F1L 60MHz)
Audio Interfaces
·J1:
(1) L/R Audio output for SSI0
(2) Microphone input for SSI1
Connectors
·CN6:CAN & Flexray Connector(Flexray’s software not support)
·CN7:GPS ANT Connector
·CN14:HSM Connector(Software not support)
·CN13:ETNB Connector (Software not support)
PCIE Connectors
·CN9:Mini PCIE Connector for V2X Sub Board
·CN8: Mini PCIE Connector for Ethernet AVB Sub Board (Software not support)
·CN12:Mini PCIE Connector for V2X Sub Board
·CN11:Standard Mini PCIE
Debugger Interfaces
·CN4:26 pin FPC connector for CPU and MCU.
·CN10:UART-USB for Debug
·CN5:UART-USB for CPU Debug
·CN16:UART-USB for MCU Debug
Network Interfaces
·CN3:10M/100M Ethernet connector for Ethernet MAC
Storage Interfaces
·CN1:USB2.0 type A receptacle x 2
·CN2:SD card slots for SDHI2
·eMMC memory for MMC
Power Supply
·CN17 or CN18: DC 12V input

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1.1.2 Functions of the Tethys Board
Table 2 List of Tethys Board Functions
Board Function
Tethys
RAM
DDR3 I/F: DDR3-SDRAM 1600MHz 1 GB x2
USB 2.0
USB2.0 CH0 : USB2.0 type A
USB2.0 CH1 : USB2.0 type A
SDHI
SDHI0 : Mini PCIE Connector for V2X Sub Board
SDHI2 : SD card slots , Mini PCIE Connector for V2X Sub Board
SCIF
SCIF0_D/HSCIF0_B : (1) Mini PCIE Connector for V2X Sub Board ,
(2) UART-USB
SCIF3_B/HSCIF2 : Mini PCIE Connector for V2X Sub Board
SCIF2_B(Debug serial) : UART-USB for CPU Debug
SCIF5_C : GPS Module
ROM(QSPI)
QSPI0 : SPI Flash 64MB
QSPI1 : SPI Flash 4MB
Ethernet MAC / Ethernet AVB
Ethernet MAC: RJ45 Connector
Ethernet AVB: Mini PCIE Connector for Ethernet AVB Sub Board (Ethernet AVB’s software
not support)
HSCIF
HSCIF1_A: Mini PCIE Connector for Ethernet AVB Sub Board (Ethernet AVB’s software
not support)
SCIF0_D/HSCIF0_B : (1) Mini PCIE Connector for V2X Sub Board ,
(2) UART-USB
SCIF3_B/HSCIF2 : Mini PCIE Connector for V2X Sub Board
I2C
I2C1_A/SPI : HSM Connector (Software not support)
I2C1_A : G-Sensor , Gyro , MCU
SSI
SSI0,1,2,9 : Audio CODEC
MSIOF
MSIOF1_B : MCU [Flexray (Software not support)、Ethernet AVB’s software not support]
MMC
MMC : eMMC(8GB)
PCI Express
Mini PCIE Connector
CAN
R-CAR W2H CAN channel support, RH850 CAN0/1 support, Flexray Software not support
Debug I/F
DBG : TO Sub Connector
VCC
Power Block
.

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1.2 Usage Notes
1.2.1 Specifications of the Tethys Board
When the AC adapter is connected to the outlet, the 12V DC power is supplied to the Tethys board and some of the circuitry start
operating. Setting the ACC switch (SW18) to the ON side after that leads to the generation of various power supply levels including
5V DC and 3.3V DC from the 12V DC power.
Take particular care to ensure the correct configurations of the jumpers and switches mounted on the Tethys board. Incorrect
configurations may damage on-board devices.
For power supply to the Tethys, be sure to use the power supply that comes with it. Applying a voltage greater than 12 V may
damage devices on the Tethys board.
There are sequences for turning on and off the power supply to the Tethys board. Be sure to obey the notes below when using
the Tethys board.
(1) When turning on the power
Be sure to confirm that the ACC switch (SW18) is off before plugging the AC adapter into the power source.
It is prohibited to plug the AC adapter into a power source while the ACC switch (SW18) is on.
(2) When turning off the power
Be sure to turn off the ACC switch (SW18) before unplugging the AC adapter from the power source.
It is prohibited to unplug the AC adapter from the power source while the ACC switch (SW18) is on.
The AC adapter that comes with the Tethys board can supply current up to 3A at 12V. If you intend sub board to PCIe connect
on Tethys board, ensure that this does not lead to supply current exceeding 3A.
If the system configuration is such that the current supply does exceed 3A, prepare a separate stabilized DC power supply that
can supply more current at 12V.
Regarding the dedicated socket for the R-Car W2H, neither disconnect it from nor connect it to the Tethys board; also,
regarding the R-Car W2H, neither remove it from nor insert it in the dedicated socket. Both actions lead to malfunctions of
R-Car W2H operation on the board due to loosening of contacts between the socket and the board and between the socket and
the R-Car W2H.

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1.3 Board Configuration
The Tethys board is composed of a single board whose size is 185 mm ×110 mm
1.3.1 Block Diagram of the Tethys Board
Figure 1 shows a block diagram of the Tethys board
DDR3 I/F
DDR3 4G*32 bit
2 devices
DDR3 4Gbit
2 devices
MT41K256M16HA-125
Micron QSPI
RJ45 CN
HY911105AE
Hanrun
EtherMAC/
EtherAVB
USB 2.0-H
Type-A CN 2 in1
1775468-1
Samtec
USB 2.0 CH1
USB 2.0 CH0
HSCIF1_A
GPIO
SCIF0_D/HSCIF0_B
USB micro-B CN
47346-0001
Molex
Tact SW 4bit
SKRKAEE010
ALPS
Emmc(8GB)
SDIN8DE1-8G-XA
Sandisk
SDHI0
SDHI2
Mini PCI
Express CN
1759546-1
TE
USB to UART
CP2102
Silicon
SD Card Slot CN
503182-1852
Molex
MMC
GPIO Power Block
VCC
CAN CN
TSW-104-08-F-D
Samtec
GPIO
CAN0_C
1PPS
HSCIF2
DBG
USB to UART
CP2102
Silicon
SCIF2_B
(debug serial)
Tethy Board
1PPS
LED 4bit
SML-D13FW
ROHM
MCU
RH850F1H
Renesas
I2C1_A
RESET
To sub Connector
FH12-20S-0.5SV
Irios
GPS Module
NEO-7M
U-blox
GPS ANT
U.FL-R-SMT
Murata
CAN CN
TSW-104-08-F-D
Samtec
RMII PHY
KSZ8041RNLI
Micrel
SPI Flash(4MB)
S25FL132K0XMFI011
Spansion
SPI Flash(64MB)
S25FL512SAGMFIG11
Spansion
GPIO
GPIO
CPU
R-CarW2H
Renesas
BU12V
CAN transceiver
TJA1050
NXP
CAN
transceiver
TJA1050
NXP
Mini PCI
Express CN
1759546-1
TE
Mini PCI
Express CN
1759546-1
TE
USB micro-B CN
47346-0001
Molex
USB to UART
CP2102
Silicon
USB micro-B CN
47346-0001
Molex
GPIO
SCIF3_B/HSCIF2
CAN CN
TSW-104-08-F-D
Samtec
CAN
transceiver
TJA1050
NXP
1PPS
G-Sensor
AIS328DQ
ST
Gyro
A3G4250D
ST
I2C1_A
USB2.0 CH1-2
USB 2.0 CH1-4
USB 2.0 CH1-3 SCIF5_C
USB HUB
GL852GT-MNGXX
GENESYS
USB 2.0 CH1-2,3,4
USB CH1 -1
CPU JTAG CN
HTST-110-01-S-DV
Samtec
MCU JTAG CN
1-1634688-4
Samtec
Connector
FH12-20S-0.5SV
Irios
Debug Board
GPIO
FPC
MSIOF1_B
PCI Express
Mini PCI
Express CN
1759546-1
TE
I2C1_A/SPI
Mini Jack Line OUT Audio DAC/ADC
AK4642
AKM SSI0,1,2,9
HSM CN
FlexrayDriver FlexrayCN
EtherAVB CN
CPU SH4A JTAG CN
1-1634688-4
Samtec
Figure 1 Block Diagram of the Tethys Board
Notice:
White text means not support the function
(HSM CN, Flexray_CN, Ethernet AVB CN)

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2 Operating condition and antenna characteristic
2.1 Operating condition
Table 3 shows the operating condition. To use the Tethys board system, please keep the condition.
Table 3 Operating Condition
Item
Min
Typ
Max
Units
Input Voltage
7
12
25
V
Consumption Current
200
450
3000(*1)
mA
Operating Temperature
-25
25
+85
Degree C
V2X antenna Frequency range
5860
5920
MHz
V2X antenna VSWR
2.0
V2X antenna Gain
2M Cable Type:
(1)3.0(without cable loss)
(2) -1.0(with cable loss)
Rod Type:
(1)5.0
dBi
V2X antenna Cable Loss
4.0 (L=2m)
dB
GPS antenna Center Frequency
1575 ±3
MHz
GPS antenna VSWR
2.0
GPS antenna Bandwidth
20
MHz
GPS antenna Gain
30
dB
Storage Temperature
-25
85
Degree C
Operating Humidity
25
85(*2)
%
Notice:
(*1): 3000mA is the maximum current of AC adapter. If user need more current for Tethys board, user need
prepare stable big current AC adapter.
(*2): Humidity: No condensation.

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3 Specifications of Interface Modules on the Tethys Board
This section describes the main function of the Tethys board, which includes the following sections:
3.1 Mode Setting
3.1.1 Specifications
The operating mode of the R-Car W2HR-Car W2H is set by a power-on reset. For details on the operating mode, see the
documents related to the R-Car W2HR-Car W2H operating mode specifications.
3.1.2 MD0 Pin -Selection of Free-Running Mode or Step-Up Mode
Do not change the initial setting at shipment (MD0=0).
3.1.3 MD [3:1] Pins-Selection of Boot Device
These pins select the boot device.
MD3
MD2
MD1
Selection of Boot Device
0
0
0
External ROM boot (area 0)
0
0
1
eMMC boot via SDHI1
0
1
0
Serial flash ROM boot via QSPI; 16Kbytes transferred at 48.75 MHz
0
1
1
Reserved
1
0
0
Serial flash ROM boot via QSPI; 16Kbytes transferred at 39 MHz
1
0
1
Reserved
1
1
0
Serial flash ROM boot via QSPI; 4 Kbytes transferred at 39 MHz
1
1
1
Reserved
3.1.4 MD4 Pin-Selection of CS0 Space Size
This pin selects whether the area 0 space (CS0) is used as a normal space (64 Mbytes) or an expanded space (128 Mbytes).
MD4
Area Division
0
Area 0: 64 Mbytes
1
Area 0: 128 Mbytes
3.1.5 MD5 Pin-Reserved
Do not change the initial setting at shipment (MD5=1).
3.1.6 MD [7:6] Pins-Selection of Master Boot Processor
These pins select the master boot processor.

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MD7
MD6
Selection of Master Boot Processor
0
0
Setting prohibited
0
1
Booted through CPU0 in CA7.
1
0
Booted through SH-4AL in 32-bit mode
1
1
Setting prohibited
3.1.7 MD8 Pin-Selection of Area 0 Space Data Bus Width
This pin sets the data bus width of the area 0 space (CS0) to 8 bits or 16 bits. Select the data bus width of the boot device
connected to the LBSC.
MD8
EXBUS Area 0 Data Bus Width
0
8-bit bus
1
16-bit bus
3.1.8 MD9 Pin-Selection of Crystal Resonator or Crystal Oscillator
This pin selects either a crystal resonator or a crystal oscillator to be connected to the EXTAL/XTAL pins. A crystal oscillator
(Y2: 20 MHz) is mounted on the Tethys board by default.
MD9
EXTAL/XTAL Pin Setting
0
An external clock is input to the EXTAL pin.
1
A crystal resonator is connected to the EXTAL and XTAL pins.
3.1.9 MD21, MD20, MD11, MD10, and MDT [1:0] Pins-Switching of JTAG, SDHI1, and SDHI2
These pins select the debugging function through the JTAG connector (CN4) or the SD card slot for the SDHI1. The debugging
through the SDHI1 or SDHI2 is possible by the combination of MD pin settings in the R-Car W2H specifications.
MD10
MD[21:20]
MD11
MDT[1:0]
JTAG
MMC
SDHI2
0
00
-
--
Boundary scan
Normal function
Normal function
0
01
-
--
Reserved
Reserved
Reserved
0
10
0
--
Coresight (*1)
Normal function
Normal function
0
10
1
00
Coresight (*1)
Reserved
Reserved
0
10
1
01
Coresight (*1)
SH-4AL
Normal function
0
10
1
10
Coresight (*1)
Reserved
Reserved
0
10
1
11
Coresight (*1)
Normal function
SH-4AL
0
11
0
--
SH-4AL
Normal function
Normal function
0
11
1
00
SH-4AL
Coresight (*1)
Normal function
1
00
-
--
Reserved
Reserved
Reserved
1
01
0
--
Reserved
Reserved
Reserved
1
01
1
01
Reserved
Reserved
Reserved
1
10
-
--
Reserved
Reserved
Reserved
1
11
-
--
Reserved
Reserved
Reserved

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(*1) “Coresight” is an abbreviation of “Coresight debug port”.
3.1.10 MD [14:13] Pins-Frequency Mode Setting
These pins select the frequency mode. A crystal oscillator (Y2: 20 MHz) is mounted on the Tethys board. Do not change the
initial setting at shipment (MD14 = 0, MD13 = 0).
MD14
MD13
EXTAL
Frequency
EXTAL
Divider
PLL0 Multiplication
Ratio
PLL1 Multiplication
Ratio
PLL3 Multiplication Ratio
0
0
20 MHz
×1
×80
VCO = 1600 MHz
×78
VCO = 1560 MHz
×50
VCO = 1000 MHz
0
1
26 MHz
×1
×60
VCO = 1560 MHz
×60
VCO = 1560 MHz
×56
VCO = 1456 MHz
1
0
Prohibited
setting
1
1
30 MHz
×1
×52
VCO = 1560 MHz
×52
VCO = 1560 MHz
×50
VCO = 1500 MHz
3.1.11 Initial Values of Mode Setting Pins on Tethys Board
The following table shows the Initial Values of Mode Setting Pins on the Board, and how the individual mode pins are set:
MD Pins
Initial
Value
Initial Function
Setting Method
MD0
0
-
Set by a dip switch
MD[3:1]
010
Boot from the QSPI(48.75 MHz/16-Kbyte
transfer)
Set by a dip switch
MD4
0
CS0 space size (64 Mbytes)
Set by a dip switch
MD5
1
-
Set by a dip switch
MD[7:6]
01
Cortex-A7 boot
Set by a dip switch
MD8
1
CS0 space data bus width (16 bits)
Set by a dip switch
MD9
1
Crystal resonator is used.
Set by a dip switch
MD10, MD[21:20], MD11,
MDT[1:0]
0,10,0,00
JTAG = Coresight
SDHI1 and SDHI2 = Normal function
Set by a dip switch
MD[14:13]
00
Input frequency = 20 MHz
Set by a dip switch
3.2 DDR3-SDRAM Interface (DBSC)
3.2.1 Specifications
The Tethys board incorporates two 4-Gbit DDR3-SDRAMs (16-bit bus width) and operates at a maximum speed of

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DDR3-1000. The Tethys board can support memory size up to 2GB (8-Gbit memory x 2) and the data bus width is 32 bits x1. The
DDR3-SDRAMs are allocated to the address space from H'01_0000 0000 to H'01_FFFF FFFF in the R-Car W2H. The address
ranges from H'00_40000000 to H'00_BFFF FFFF can be accessed by default as a mirror area of H'01_0000 0000 to H'01_7FFF
FFFF.
Table 4 DDR3-SDRAM Interface Specifications
Controller
On-chip external bus controller for DDR3-SDRAM (DBSC) in the R-Car W2H
Product name
MT41K256M16HA-125 AAT:E from Micron
DDR3-1600 (x 16 bits, 4 Gbits) x 2 pcs
Power supply voltage
1.50 V
Capacity
H'01_0000 0000 to H'01_FFFF FFFF
Bus width
32-bit data bus
Memory bus frequency(R-Car W2H Spec.)
DDR3-1000
3.2.2 Signal Connections between R-Car W2H and DDR3-SDRAMs
Table 5 Signal Connections between R-Car W2H and DDR3-SDRAMs
R-Car W2H
DDR3-SDRAM (U3)
DDR3-SDRAM (U4)
D[31:16]
D[15:0]
M0DQ[31:16]
DQ[15:0]
--
M0DQ[15:0]
--
DQ[15:0]
M0A[15:0]
A[15:0]
←
M0BA[2:0]
BA[2:0]
←
M0CK1、M0CK1#
CK、CK#
--
M0CK0、M0CK0#
--
CK、CK#
MCKE1
CKE
--
MCKE0
--
CKE
M0CS1#
CS#
--
M0CS0#
--
CS#
M0WE#
WE#
←
M0RAS#
RAS#A
←
M0CAS#
CAS#
←
M0DQS3、M0DQS3#
UDQS、UDQS#
--
M0DQS2、M0DQS2#
LDQS、LDQS#
--
M0DQS1、M0DQS1#
--
UDQS、UDQS#
M0DQS0、M0DQS0#
--
LDQS、LDQS#
M0DM3、M0DM2
UDM、LDM
--
M0DM1、M0DM0
--
UDM、LDM

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M0ODT1
ODT
--
M0ODT0
--
ODT
M0RESET#
RESET#
←
3.2.3 Block Diagram
R-CarW2H
M0DQ[31:0]
M0A[15:0]
M0BA[2:0]
M0RAS#
M0CAS#
M0WE#
M0RESET#
M0CS0#
M0CKE0
M0ODT0
M0CK0
M0CK0#
M0DQS[1:0]
M0DQS[1:0]#
M0DM[1:0]
M0CKE1
M0ODT1
M0CK1
M0CK1#
M0DQS[3:2]
M0DQS[3:2]#
M0DM[3:2]
M0BKPRST#
M0VREFDQ1
M0VREFDQ0
M0VREFCA
M0ZQ
A[15:0]
BA[2:0]
RAS#
CAS#
WE#
RESET#
CS#
CKE
ODT
CK
CK#
DQS
DQS#
DM
DQS
DQS#
DM
DQL[7:0]
DQU[7:0]
VREFCA
VREFDQ
DQL[7:0]
DQU[7:0]
0.1uF 0.1uF
0.1uF
20K20K
DDR3
0.1uF 0.1uF
0.1uF
20K20K
M0BKPRST D1.5V D1.5V
120
MT41K256M16H
A-125 AAT:E
0.1uF 0.1uF
20K20K
22
22
22
22
22
M0CS1# CS#
22
22
CKE
22
22
22
100
M0ZQ
240
ODT
CK
CK#
D1.5V
0.1uF
51
51
0
0.1uF
Figure 2 Block Diagram of the DDR3-SDRAM Interface

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3.3 SPI-Flash Interface (QSPI)
3.3.1 Specifications
The Tethys board incorporates 512-Mbit and 32-Mbit SPI flash memory devices manufactured by Spansion. These flash memory
devices are connected to the QSPI of the R-Car W2H’s pin of (GP1_21/QSPI0_SSL/WE1#). And the connection is controlled by
SW9 When the 512-Mbit SPI flash memory is to be assessed, set SW9 pin 3 and 6 short, and when the 32-Mbit SPI flash memory is
to be accessed, set SW9 pin 4 and 8 short. Do not short them at the same time.
Table 6 SPI-Flash Interface Specifications
Flash memory interfaces
QSPI0 and QSPI1 in the R-Car W2H
Operating voltage
D3.3 V_FLASH = 3.3V
Capacity
512-Mbit and 32-Mbit
Mapping area (512-Mbit)
0x0000000~0x3ffffff
Mapping area (32-Mbit)
0x0000000~0x3fffff
3.3.2 Block Diagram
R-Car W2H
SPI FLASH
S25FL132K0XMFI011
32Mbit
U6
GP1_21/QSPI0_SSL/WE1#
GP1_20/QSPI0_IO3/RD#
GP1_19/QSPI0_IO2/CS0#
GP1_18/QSPI0_MISO/QSPI0_IO1/RD/WR#
GP1_17/QSPI0_MOSI/QSPI0_IO0/BS#
GP1_16/QSPI0_SPCLK/WE0#
CS#
QSPI_IO3
QSPI_IO2
QSPI_SO/IO1
QSPI_SI/IO0
QSPI_CLK
HOLD#/IO3
W#/ACC/IO2
SI/IO0
SI/IO1
CLK
QSPI
D3.3V_FLASH
SPI FLASH
S25FL512SAGMFIG11
512Mbit
U5
CS#
DQ3
DQ2
DQ0
DQ1
CLK
D3.3V_FLASH
5
6
4
3
SW9
Figure 3 Block Diagram of the SPI-Flash Interface
QSPI0 devices
U5:S25FL512SAGMFIG11 (512 Mbits, 8-/16-bit data width) from Spansion ×1 pcs
U6:S25FL132K0XMFI011(32Mbits, 8-/16-bit data width) from Spansion ×1 pcs