RF Technology Eclipse Series User manual

Eclipse Series
RF Technology
[e-mail]
November, 2001
T50 Transmitter
Operation and Maintenance Manual
This manual is produced by RF Technology Pty Ltd
10/8 Leighton Place, Hornsby NSW 2077 Australia
Copyright © 2001 RF Technology

Page 2 RF Technology T50
CONTENTS CONTENTS
Contents
1 Operating Instructions 5
1.1 Front Panel Controls and Indicators 5
1.1.1 PTT 5
1.1.2 Line 5
1.1.3 POWER LED 6
1.1.4 TX LED 6
1.1.5 ALARM LED 6
2Transmitter Internal Jumper Options 7
2.1 Serial I/O Parameters 7
2.2 Line Terminators 7
2.3 Exciter Low Battery Level 7
2.4 External PA Parameters 7
2.5 LOOP Volts Select 7
2.6 Direct Audio (TONE) Select 8
2.7 Direct Audio (TONE) High Pass Filter Select 8
2.8 Transmit Time 8
2.9 Channel Selectable Parameters 8
3 Transmitter I/O Connections 8
3.1 25 Pin Connector 8
3.2 9 Pin Front Panel Connector 9
4 Channel and Tone Frequency Programming 10
4.1 Setting Options 10
4.2 Setting Channel Parameters 11
5 Circuit Description 13
5.1 T50 Master Schematic (Sheet 1) 13
5.2 Microprocessor (Sheet 2) 13
5.3 Audio Processing Section (Sheet 3) 13
5.4 Line Input Processing Section (Sheet 4) 13
5.5 Tone Generation Section (Sheet 5) 20
5.6 Frequency Synthesiser (Sheet 6) 21
5.6.1 The Modulation PLL 21
5.6.2 The Channel PLL 22
5.6.3 The External Reference Divider 23
5.6.4 The DAC 23
5.6.5 The VCOs and the RF Output 24
5.7 Voltage Controlled Oscillators (Sheet 7) 24
5.8 1W Broadband HF Power Amplifier (Sheet 8) 26
5.9 Power Generation Section (Sheet 9) 26
6 Field Alignment Procedure 27
6.1 Standard Test Equipment 27
6.2 Invoking the Calibration Procedure 28
6.3 The “Miscellaneous” Calibration Procedure 28
6.4 The “Reference” Calibration Procedure 29

RF Technology T50 Page 3
CONTENTS CONTENTS
6.5 The “Deviation” Calibration Procedure 31
6.6 The “Tone Deviation” Calibration Procedure 32
6.7 The “Line” Calibration Procedure 33
6.8 The “Power” Calibration Procedure 34
7 Specifications 36
7.1 Overall Description 36
7.1.1 Channel Capacity 36
7.1.2 CTCSS 37
7.1.3 Channel Programming 37
7.1.4 Channel Selection 37
7.1.5 Microprocessor 38
7.2 Physical Configuration 38
7.3 Front Panel Controls, Indicators and Test Points 38
7.3.1 Controls 38
7.3.2 Indicators 38
7.3.3 Test Points 38
7.4 Electrical Specifications 38
7.4.1 Power Requirements 38
7.4.2 Frequency Range and Channel Spacing 39
7.4.3 Frequency Synthesizer Step Size 39
7.4.4 Frequency Stability 39
7.4.5 Number of Channels 39
7.4.6 Antenna Impedance 39
7.4.7 Output Power 39
7.4.8 Transmit Duty Cycle 39
7.4.9 Spurious and Harmonics 39
7.4.10 Carrier and Modulation Attack Time 40
7.4.11 Modulation 40
7.4.12 Distortion 40
7.4.13 Residual Modulation and Noise 40
7.4.14 600ΩLine Input Sensitivity 40
7.4.15 Test Microphone Input 40
7.4.16 External Tone Input 40
7.4.17 T/R Relay Driver 40
7.4.18 Channel Select Input / Output 41
7.4.19 DC Remote Keying 41
7.4.20 PTT in 41
7.4.21 Programmable No-Tone Period 41
7.4.22 Firmware Timers 41
7.4.23 CTCSS 42
7.5 Connectors 42
7.5.1 RF Output Connector 42
7.5.2 Power and I/O Connector 42
7.5.3 External Reference Connector (optional) 42

Page 4 RF Technology T50
1. CONTENTS CONTENTS
A Engineering Diagrams 43
A.1 Block Diagram 43
A.2 Circuit Diagrams 43
A.3 Component Overlay Diagrams 43
B Parts List 44
C EIA CTCSS Tones 60

RF Technology T50 Page 5
1 OPERATING INSTRUCTIONS
1 Operating Instructions
1.1 Front Panel Controls and Indicators
1.1.1 PTT
A front-panel push-to-talk (PTT) button is provided to facilitate bench and field tests
and adjustments. The button is a momentary action type. When keyed, audio from the
line input is disabled so that a carrier with subtone is transmitted. The front-panel
microphone input is not enabled in this mode, but it is enabled when the PTT line on
that socket is pulled to ground.
The PTT button has another function when transmission is keyed up, and the TX LED
light is showing. If there is a “forward power low” alarm (the ALARM LED flashes
three times, then pauses), pressing this will cause the ALARM LED to flash 6, 7, 8, or 9
times before the pause (see Table 2). This will indicate what has caused the low power
alarm.
1.1.2 Line
The LINE trimpot is accessible by means of a small screwdriver from the front panel of
the module. It is used to set the correct sensitivity of either line input or the direct
audio input. It is factory preset to give 60% of rated deviation with an input of 0dBm
(1mW on 600Ωequivalent to 775mV RMS or about 2.2V peak-to-peak) at 1kHz. The
nominal 60% deviation level may be adjusted by measuring between pins 6 and 1 on the
test socket, and adjusting the pot. By this means an input sensitivity from approximately
-12dBm to +12dBm may be established.
An internal, software selectable, option, provides an extra gain step of 20dB. This,
effectively changes the input sensitivity to –32 to –8dBm.
WARNING
Changes or modifications not expressly approved by
RF Technology could void your authority to operate this
equipment. Specifications may vary from those given in
this document in accordance with requirements of local
authorities. RF Technology equipment is subject to
continual improvement and RF Technology reserves the
right to change performance and specification without
further notice.

Page 6 RF Technology T50
1.1.3 Power Led 1 OPERATING INSTRUCTIONS
LED Flash Cadence Fault Condition
9 flashes, pause External PA failure
8 flashes, pause Low dc supply on External PA
7 flashes, pause External PA Over Current Condition
6 flashes, pause External PA Over Temperature
5 flashes, pause Synthesizer unlocked
3 flashes, pause Unable to communicate with External PA
2 flashes, pause The current channel is not programmed or the frequency
is out of range.
1 flash, pause Low dc supply voltage
LED ON continuously Transmitter timed out
Table 1: Interpretations ofLED flash cadence (TXLED Off)
LED Flash Cadence Fault Condition
9 flashes, pause External PA failure (if PTT is pressed)
8 flashes, pause Low dc supply on External PA (if PTT is pressed)
7 flashes, pause External PA Over Current Condition(if PTT is pressed)
6 flashes, pause External PA Over Temperature(if PTT is pressed)
4 flashes, pause Either PLL is near operational limit
3 flashes, pause Forward Power Out of Range(if PTT is not pressed)
2 flashes, pause Reverse Power ratio exceeded.
1 flash, pause Low dc supply voltage
LED ON continuously Transmitter timed out
Table 2: Interpretations ofLED flash cadence (TXLED On)
1.1.3 POWER LED
The PWR LED shows that the dc supply is connected to the receiver and that the
microprocessor is not being held in a RESET state.
1.1.4 TX LED
The TX LED illuminates when the transmitter is keyed. It will not illuminate (and an
ALARM cadence will be shown) if the synthesizer becomes unlocked, or the output
amplifier supply is interrupted by the microprocessor.
1.1.5 ALARM LED
The Alarm LED can indicate several fault conditions if they are detected by the self test
program. The alarm indicator shows the highest priority fault present. See Tables 1
and 2.

RF Technology T50 Page 7
2 TRANSMITTER INTERNAL JUMPER OPTIONS
2Transmitter Options
There are NO internal jumpers in the T50.
There are many software selectable options. Some options are selected on a per channel
basis, and some are defined globally (i.e. the parameter is fixed irrespective of which
channel is selected). Below is a description of these global parameters
2.1 Serial I/O Parameters
There are two serial ports. There is the main serial port which is brought out to the front
panel connector. This is referred to as PORT0. There is another serial port which is for
factory use only. It is referred to as PORT1.
The baud rate, parity, and whether hardware flow control is enabled can be defined for
PORT0. PORT0 is set by default to 57.6Kbps, with No parity, and No Hardware Flow
Control.
2.2 LINE Terminators
There are two main audio inputs, plus a direct audio (TONE) input. The direct audio
input is a High Impedance Balanced DC input, but the two audio inputs are AC coupled
(> 10Hz) inputs which can be High Impedance(HiZ), or 600 ohm inputs. Each input
can be software selected to be HiZ, or 600 ohms.
2.3 Exciter Low Battery Level
This is factory set to 24.0V, and defines the level of the DC supply that will cause an
Exciter dc supply low alarm.
2.4 External PA Parameters
There are several user definable parameters associated with the external PA provided
with each exciter.
These are the PA low battery alarm level (default is 26V), the PA Set Forward Power
Level (defaults to 100W), the Forward Power Low Alarm Level (defaults to 90%), and
the Reverse Power Alarm Level (defaults to 25% - corresponding to a VSWR of 3:1).
2.5 LOOP Volts Select
Normally the transmitter will key up if dc current is sensed flowing in either direction
between Line1+ and Line1- (>=1mA). If this option is selected, then a 12Vdc supply is

Page 8 RF Technology T50
2.6 Direct Audio (TONE) Select 2 TRANSMITTER INTERNAL JUMPER OPTIONS
applied to the pair through 660 ohms of source impedance. (It would be expected,
normally, that if this option is selected, then the option to remove the 600 terminator
from Line1, would also be selected). If dc current flows from having applied this
potential, then the transmitter will key up.
2.6 Direct Audio (TONE) Select
Normally any signal applied to the TONE+/TONE- pair is ignored. If this option is
selected then a Direct Audio input will be mixed with any audio received on either of
the other two lines.
2.7 Direct Audio (TONE) High Pass Filter Select
Normally the Direct Audio, and the CTCSS outputs are passed through a 250Hz, low
pass filter. This filter can be bypassed by selecting this option.
2.8 Transmit Time
This parameter defines a maximum time limit for continuous transmission. It is
expressed in seconds and can be arbitrarily large (months in fact). If it is set to zero
seconds, then the transmitter can stay keyed up permanently.
2.9 Channel Selectable Parameters
Each channel defines two complete set of parameters. One set of parameters is used
when a transmitter keys up from the PTT-in input, and the other set is used when the
transmitter keys up from the LOOP-in, the PTT switch, or the microphone PTT input.
Each set defines what frequency to use, what CTCSS sub-tone (if any) to use, what
maximum line deviation to use, what tone deviation to use, what transmit delay (a delay
applied from PTT-in or LOOP-in to transmission), what transmit tail (delay from PTT-
in, or LOOP-in, to transmission being stopped, and No-TONE period (a period of extra
transmission in which No Tone is applied after PTT-in or LOOP-in has been released.
As well as these parameters, which Line (or Lines) can be selected, and whether the
Lines should have Flat frequency response or have Pre-emphasis applied. Also, it can
Enable or disable the extra 20dB gain pad.
Note that both Line1 and Line 2 can be selected (each with or without pre-emphasis),
and if so, then the two signals will be mixed, and the Line potentiometer will adjust the
level of them both.
3 Transmitter I/O Connections
3.1 25 Pin Connector
The female D-shell, 25 pin, connector is the main interface to the transmitter. The pin
connections are described in table 3.

RF Technology T50 Page 9
3 TRANSMITTER I/O CONNECTIONS 3.2 9 Pin Front Panel Connector
Function Signal Pins Specification
dc power +28Vdc(in)
0 Vdc
+5Vdc(out)
+12Vdc(out)
13, 25
1, 14
17
15
+24 to 32 Vdc
Common Voltage
Output for external Logic(100mA)
Output for an external relay(120mA)
Serial
Communications SCLK MOSI
CH_EN
PA_CS
SPARE_SEL
12
6
18
24
5
Serial Clock
Bi-directional Data Pin
Enables Channel Select Shift Register
Enables PA A/D chip
Spare Select (for future use)
600Ω/HiZ Line Line1+
Line1- 8 19 Transformer Isolated Balanced 0dBm Input
600Ω/HiZ Line Line2+
Line2- 10 22 Transformer Isolated Balanced 0dBm Input
Direct PTT input 11 Ground to key PTT
T/R Relay driver
output 23 Open collector, 250mA /12V
Sub-Audible Tone
Input Tone+ Tone- 9 21 >10kΩ, dc coupled
Table 3: Pin connections and explanations for the main 25-pin, D connector.
3.2 9 Pin Front Panel Connector
The female D-shell, 9 pin, front panel connector is an RS232 interface for serial
communications to a terminal, a terminal emulator, or to a computer. The pin
connections are described in table 4.
Function Pins Specification Pin name on IBM PC
TXD 2 Transmit Data (Output) RxD
RXD 3 Receive Data (Input) TxD
RTS 8 Request To Send (Output) CTS
CTS 7 Clear To Send (Input) RTS
DTR 6 Data Terminal Ready(Output) DSR
DSR 1 Data Set Ready (Input) DCD
GND 5 GND GND
Table 4: Pin connections for the front panel 9 pin D connector.
The pinout for the connector has been chosen so that a straight-through BD9 male to
DB9 female cable can connect the transmitter to any male DB9 serial port on an IBM
PC compatible computer.
Note that for connection to a modem, a cross-over cable will be required.

Page 10 RF Technology T50
4 CHANNEL PROGRAMMING AND OPTION SELECTION
4 Channel Programming and Option Selection
Channel and tone frequency programming is most easily accomplished with RF
Technology Eclipse50 software. This software can be run on an IBM compatible PC
and can be used to calibrate a T50, R50, and PA50 as well as program channel
information. See the Eclipse 50 users manual for further information.
But the T50 also has its own stand-alone high level interface, which can be accessed
from a VT100 compatible terminal, or terminal emulator (such as HyperTerm which is
available as a standard accessory with Windows).
The pertinent aspects of this High Level Interface are described below.
4.1 Setting Options
Note that any text in italics, represents data output by the T50 firmware, rather than
command line data sent to the T50 firmware.
The T50, after powering up, will issue a command prompt of the form:
T50>
Via a terminal, or a terminal emulator, a user can type various commands in. The basic
command to read parameters is:
T50> read par parameter_name
Where “parameter_name” is one of the following:
Parameter Name Parameter Function Default Value Parameter
Range
LOOP_GEN Generate a LOOP potential
(see 2.5) Off Text: Off or On
PA_SET_FWD_PWR Output Power of the PA (see
2.4) 100.0 (Watts) Floating point number
20.0 – 150.0
PA_LOW_BAT Low Battery Alarm Level (see
2.4) 26.0 (Volts) Floating Point
Number
< 32.0
REV_PWR_ALARM Sets the maximum level of
reverse power. At this level of
reverse power, forward power
is automatically decreased so
that this reverse power level is
never exceeded. It also sets
the ratio of forward power,
which if exceeded causes the
reverse power alarm condition
to be asserted
25.0 (% of
PA_SET_FWD_PWR)
25.0 (% of current
forward power)
Floating
Point
Number
0.0 – 99.9

RF Technology T50 Page 11
4 CHANNEL PROGRAMMING AND OPTION SELECTION
Parameter Name Parameter Function Default Value Parameter
Range
LOW_PWR_ALARM Level of Output Power when
the low power alarm condition
occurs (see 2.4)
90.0 (% of
PA_SET_FWD_PWR) Floating Point
Number
0.0 – 99.9
TRANSMIT_TIME Maximum Time that the
transmitter can stay keyed up 0 (Seconds: Note that zero seconds implies
no transmit time limit)
Decimal
number:
0 - 9999999
BAUD_RATE0 Port 0 Baud Rate 57600 (BPS) Decimal
number:
300 - 115200
PARITY0 Port 0 Parity None Text: None,
Even, or Odd
FLOW_CONTROL Port 0 Flow Control Off (“On” not yet
available) Text: Off
Table 5: Some User Defined Parameters.
Note that the parameter names have been shown in upper case, but they can be typed in
upper or lower case.
A parameter can be changed, or added, by typing
T50> set par parameter_name=parameter_value
As for parameter names, the parameter value can be Upper or Lower case if it is a text
value, as against a numeric value.
4.2 Setting Channel Parameters
One can read the data from an existing channel by enteringthe command:
T50> read chan chan_number
Where chan_number is a number from 0 to 99.
Entering new channel values, or modifying existing ones is possible from the command
line interface, but it is not recommended. It can be done by typing the following at a
command prompt:
T50> set chan chan_number parameter_list
Where chan_number is a number from 0 to 99.
The format of the parameter_list is quite complex. It has 14 fields. Each field can be
separated by a colon(:), comma(,), space, or tab.
For example set chan 0 25.0,35.0,100.0,120.0,0,5,2,0,5,2,10,11,0,3

Page 12 RF Technology T50
4 CHANNEL PROGRAMMING AND OPTION SELECTION
Field1: Transmit Frequency (in MHz) if PTT-in is asserted. This is 25.0 MHz in the
example.
Field2: Transmit Frequency (in MHz) if the exciter is keyed up by anything but PTT-in
being asserted. This is 35.0 MHz in the example.
Field3: CTCSS Tone (in Hz) if PTT-in is asserted. This is 100Hz in the example.
Field4: CTCSS Tone (in Hz) if the exciter is keyed up by anything but PTT-in being
asserted. This is 120Hz in the example.
Fields 5,6,7: These define the start-up delay (in hundredths of a second), the transmit
tail (in seconds), and the no tone period (in tenths of a second) if the exciter
keys up from PTT-in being asserted.
Fields 8,9,10: These define the start-up delay (in hundredths of a second), the transmit
tail (in seconds), and the no tone period (in tenths of a second), if the exciter
keys up from anything other than PTT-in being asserted.
Field 11: Selects the line parameter if PTT-in being asserted caused the exciter to key
up. In the example it has disabled the 20dB gain pad, and enabled pre-
emphasis on Line 2 (Line 1 is disabled).
Field 12: Selects the line parameter if anything other than PTT-in being asserted caused
the exciter to key up. In the example it has disabled the 20dB gain pad, and it
would enable pre-emphasis on Line 1 and Line2 (i.e. audio on each input is
mixed).
Field 13: Selects the Tone deviation and the Maximum Line deviation if the exciter
keys up from PTT-in being asserted In the example, it has selected the default
maximum line deviation (5kHz), and the default tone deviation of 750Hz. (See
Tables 7 and 8)
Field 14: Selects the Tone deviation and the Maximum Line deviation if the exciter
keys up from anything other than PTT-in being asserted. In the example, it
has selected a maximum deviation of 2.5kHz, and a maximum tone deviation
of 375Hz. (See Tables 7 and 8)
Least Significant BCD digit of Fields 13 or 14 Maximum Deviation
0 5.0kHz
1 4.0kHz
2 3.0kHz
3 2.5kHz
4 2.0kHz
5 1.5kHz
6 User Specified(default: 4.5kHz)
Table 7: Maximum Deviations

RF Technology T50 Page 13
4 CHANNEL PROGRAMMING AND OPTION SELECTION
Most Significant BCD digit of Fields 13 or 14 Nominal Tone Deviation
0 750Hz
1 500Hz
2 375Hz
3 250Hz
4 150Hz
5 User Specified (default: 600Hz)
Table 8: Maximum Tone Deviations (when Max Dev is 5kHz)
Note that the actual maximum tone deviations depend on the maximum deviations. If a
maximum deviation of 4kHz was chosen, and a nominal tone deviation of 250 Hz, the
actual maximum tone deviation would be 250*4.0/5.0 = 200Hz.
If the Eclipse50 Software is not used to program the exciter, it is recommended that the
programming information is prepared using a spreadsheet and/or a text editor, and the
resulting file is then downloaded, as a text file, to the firmware using, for example,
HyperTerm.
Note that if using HyperTerm to download the text file, at 57600 bits per second or
higher speeds, the connection properties may need to be changed to add a 10
millisecond delay after each line of text is sent.
5 Circuit Description
The following descriptions should be read as an aid to understanding the block and
schematic diagrams given in the appendix of this manual.
There are 9 sheets in the schematic in all.
5.1 T50 Master Schematic (Sheet 1)
Sheet 1, referred to as the “T50 Master Schematic”, is a top level sheet, showing five
circuit blocks, and their interconnection with each other, as well as the interconnection
with all connectors and external switches.
JP12 is the connector, on the printed circuit board, for the microphone input.
P3 represents the rear female DB25 connector.
J1 is the nominal 1W RF output (BNC) connector, which is used to connect to the
External Power Amplifier.
J4 is an optional BNC connector for an external reference clock. If an external
reference clock, with power level from +5 to +26dBm is attached here, the firmware
will automatically track the channel VCO to the reference.

Page 14 RF Technology T50
5 CIRCUIT DESCRIPTION
Note that the external reference frequency is limited to:
500kHz, or any multiple
any multiple of 128KHz greater than or equal to 4
any multiple of 160KHz greater than or equal to 3
P1 is the front panel DB9 RS-232 connector for attachment to a terminal, a terminal
emulator, or to an IBM PC running the Eclipse50 software.
JP2 is for the attachment of an LCD display module. This has been included for later
development.
JP3 is a specialised connector for test and factory configuration use only.
RV100 represents the front panel LINE potentiometer.
SW1 represents the PTT test pin.
D102, D103, and D104 represent the three front panel LEDs.
5.2 Microprocessor (Sheet 2)
Sheet 2 describes the basic microprocessor circuitry.
The core CPU is the Motorola XC68HC12A0. It is configured in 8 bit data width
mode.
The CPU is clocked by a 14.7456MHz crystal oscillator circuit (top left) comprising the
JFET Q202, and two switching transistors Q203 and Q204.
The CPU contains an 8 channel A/D converter whose inputs are identified as AN0,
AN1, …, AN7.
AN7 and AN6 are used as LOCK detect inputs from the two Phase Locked Loop (PLL)
circuits (see 5.6)
AN5 is used to sense whether or not the dc supply is within spec or not.
AN4 is multiplexed between the LINE control potentiometer and the Channel reference
crystal’s temperature sense. Which analogue input drives this analogue input, is defined
by the state of TEMP_LEVEL_IN which is a CPU output signal.
AN3 and AN1 are inputs from the PLL circuits that sense the bias voltage on the VCO
control varactor for each VCO.
AN2 is used to sense the average peak voltage of the audio input.
AN0 is used to sense the average peak voltage of the RF output.

RF Technology T50 Page 15
5 CIRCUIT DESCRIPTION
FRDY is an output from the flash. It goes low when the Flash starts to write a byte of
data, or erase a block, or erase the whole chip, and it returns to its default high state
when the action requested has completed.
FPSW1 is the switch input from the PTT Test pin.
FPSW2, and FPSW3 are two pins that have been reserved for future use as switch
inputs.
LOOP/VOLTS_SEL is a CPU output that when high applies 12V of dc feed to the
audio output.
TONE_DEV_U/D and TONE_DEV_INC are CPU outputs that are used to control the
digital potentiometer that sets the TONE deviation level. (see 5.5)
EXT_TONE_SEL is a CPU output that when low enables differential analogue input
from the TONE+/TONE- pair. (see 5.5)
LINEINP_ADSEL is a serial bus select pin. It selects the quad Digital to Analogue
converter (DAC) that sets the levels for the two Line input Voltage Controlled
Amplifiers, the output RF power amplifier bias voltage, and the LCD bias circuit. (see
5.4)
LINEINP_DSEL is also a serial bus select pin. It is used to select the shift register that
is used to control most of the analogue switches in the audio Line input circuitry, as
well as the digital POT used to set the maximum deviation level. (See 5.4)
PWR_CNTRL_HIGH is a CPU output that can be low, tri-state, or high. This adjusts,
slightly, the range of the power amplifier bias circuitry allowing finer control of the
output power level. (see 5.4 and 5.8)
CTCSS_SEL is a serial bus select pin. It is used to select the FX805 chip(U500), which
is used to generate CTCSS tones. (see 5.5)
CHAN_PLL_SEL is a serial bus select pin. It is used to select the PLL chip in the
Channel PLL circuit (U604). (See 5.6)
SIGGEN_ADSEL is a serial bus select pin. It is used to select the quad DAC in the RF
area. This DAC controls the reference oscillator bias voltages, and the BALANCE
voltage controlled amplifier. (See 5.6)
CHAN_VCO_EN is a CPU output that enables (when high) the Channel VCO. (See 5.6
and 5.7)
EXT_REF_DIV is a CPU timer input. It is the output of the external reference clock
divided by 3200. The software can measure what the reference frequency is, and then
use this input to calculate the frequency error of the channel PLL reference oscillator. It
can then adjust the channel reference oscillator to reduce this error to less than 0.3ppm.
(See 5.6)

Page 16 RF Technology T50
5 CIRCUIT DESCRIPTION
SPARE_SEL is a serial bus select. It has been reserved for future use, and has been
brought out to the rear DB25 connector. (see 5.1)
CH_EN is a serial bus select. It is brought out to the rear panel and is used to interface
to the channel encoder on the rear daughter-board. (See 5.1)
Any GPS pulses are isolated from the on-board electronics by the opto-isolator U212.
The output of that opto-isolator is then connected to the GPS timer input of the CPU.
The software assumes that any GPS pulses are 1 second apart and can use this input to
measure the frequency error of the channel PLL reference oscillator. . It can then adjust
the channel reference oscillator to reduce this error to less than 0.3ppm. (See 5.1)
TERM_EN2 and TERM_EN1 are used to enable (when low) 600 ohm termination of
Line2, and Line1 respectively. (See 5.3)
Fo_MOD_2, and Fo_CHAN_2 are the Fo outputs from the Modulation PLL and the
Channel PLL divided by two. They should be 200Hz square waves, except for brief
periods when frequencies are being changed. (See 5.6)
LCD_DB7 is an input used to sense if the LCD display module is busy processing the
last command sent to it.
ECLK is a pin that at start-up only, should have the CPU system clock of 7.3728MHz
on it.
TX_LED, ALARM_LED, are CPU outputs that drive (when low) the TX LED, and the
ALARM LED on.
T/R_RELAY_H, when high, drives the T/R RELAY output low, and also enables the
RF power amplifier. The T/R RELAY output can activate at least one conventional
12V relay. (See 5.1)
SCLK, and MOSI are used as the core of a serial bus. SCLK is a clock pin, and MOSI
is a bi-directional data pin.
PA_CS is a serial select pin. It is passed, via the rear DB25 connector to the External
Power Amplifier (PA). (See 5.1)
DBGTX_TTL, DBGRX_TTL are RS232 transmit and receive (TTL) data pins which
are connected to the debug port after conversion to/from RS232 compatible voltage
levels by U202 and U201.
TXD_TTL, RXD_TTL, RTS_TTL, CTS_TTL, DTR_TTL, DSR_TTL, are RS232 data
pins which are connected to the main front panel serial port after conversion to/from
RS232 compatible voltage levels by U202 and U201.
PTT_uPHONE is a CPU input and it reflects the state of the PTT pin on the microphone
handset.
TONE_INT is a CPU input that comes from the FX805 (U500). This pin is used to
indicate when a Tone has been decoded, or there is some other need to service the
FX805. As yet this pin is not used in the T50. (See 5.5)

RF Technology T50 Page 17
5 CIRCUIT DESCRIPTION
LOOP_DET is a CPU pin that is asserted low if there is dc loop current detected
through the centre tap input of Line2. (See 5.3)
FILTER_OFF is a CPU output that is used to by-pass, when low, the low pass filter in
the Tone Input Circuitry. (See 5.5)
PTT-in is an input from the rear DB25 connector that causes the INT pin of the CPU to
be asserted (low) when 1mA of current is drawn via that pin. If PTT-in is pulled to
ground, through a resistance of at most 3.9kohms, it will cause INT to be asserted. If it
is pulled low via a 2K2 resistor, and as many as three diodes in series, it will still cause
the INT pin to be asserted. This latter example shows that quite complex diode logic
can be used on this pin.
BKGD is a bi-directional I/O pin used to communicate with the core of the CPU. It is
connected to the debug port and is utilised by specialised hardware to control the CPU
externally, even without any firmware being present in the Flash.
DEV_H_L is a CPU output that can be used to generate a test signal in the audio path.
It is currently not used. (See 5.4)
The RESET pin is both a low active input and a low active output to the CPU. If
generated externally to the CPU, it forces the CPU into reset, and if the CPU executes a
RESET instruction this pin will be driven low by the CPU.
Whenever there is insufficient volts (< 4.65V) on pin 2 of the MC33064D (U203), it
will keep its RES output low. After the voltage has met the right level it will assert its
output low for another 200 milliseconds. Thus the CPU will be held in reset until VCC
is at the correct level. Thus the PWR_OK LED will only light when VCC is within
specification, and RESET has been released.
S200 is a momentary push-button switch that, when pressed, will cause the CPU to be
reset.
MOD_PLL_SEL is a serial bus select pin. It is used to select the Modulation PLL chip
(U602). (See 5.6)
LCD_RS, LCD_R/W, and LCD_E are reserved for interfacing to an LCD display
module. Note that this feature has not been implemented.
U205 is used to select whether the Flash or RAM is to be read or written.
U207 is a single supply, 5V, TSOP40 Flash chip of size 8, 16, or 32 Megabits, and is
used to store the firmware.
U208 is a 1, or 4, Megabit Static RAM in an SOP-32 package, and is used for both code
and data. The code in the RAM is copied from the Flash, at start-up.

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5 CIRCUIT DESCRIPTION
5.3 Audio Processing Section (Sheet 3)
Sheet 3 is a schematic, which itself refers to two other sheets.
Sheet 3 shows how the two Line inputs go to audio transformers T300 and T301, are
then optionally terminated by analogue switches U301B, and U301C, before being
passed to the audio input stages described by Sheet 4.
It also shows how the Direct Audio (TONE) signal is passed to the Tone circuitry (sheet
5).
It also shows how dc current in Line1 will cause the opto-isolator (U300) to generate
the CPU input LOOP_DET.
Relay RL300 is used to drive current back through an externally generated dc loop,
when the CPU output LOOP/VOLTS_SEL is high.
The output of the Tone circuitry and the Audio circuitry is mixed (summed) and
amplified by U302. It is then passed through a high order low pass filter (3.1kHz),
before being attenuated by digital POT U303.
The Digital POT (U303) sets the Maximum deviation.
U302C then adds 6dB of gain before sending the audio to the modulator.
R317, D307, and C304, act as an average peak detector. This enables the CPU to
determine the size of signals being handled by the audio section.
Note that the Line inputs, and the TONE input, are protected by transils and fuses
against accidental connection to damaging voltages. The fuses (F300, F301, and F302)
are not user replaceable. They are surface mount devices and must be replaced by
authorised service personnel.
5.4 Line Input Processing Section (Sheet 4)
The two audio inputs are passed, after transformer coupling, to sheet 4.
In Sheet 4, the two Line Inputs are input to a transconductance amplifier (U402A, and
U402B). A transconductance amplifier is a current controlled, current amplifier, i.e. it
amplifies input current, but its level of amplification is controlled by the level of current
that is injected into pin1 or pin16. By converting a DAC output into a current, and
converting the input voltage into an input current, U402A and U402B are converted into
Voltage Controlled voltage Amplifiers(VCAs).
Two of the DAC outputs are converted to currents by U400B, U400C, Q401, and Q400,
and these currents are used to control the gain of the transconductance amplifiers.
The input voltages are converted to current by the input load resistors R402, and R403.
The output currents are converted to voltages by resistors R420 and R424.

RF Technology T50 Page 19
5 CIRCUIT DESCRIPTION
The outputs of the transconductance amplifiers are buffered by the darlington buffers
provided with the amplifiers (U402C, and U402D).
The output of each VCA is then amplified by U405B and U405C respectively.
The level of amplification of each VCA is adjusted in software in accordance with any
adjustments made to the LINE POT. The software converts the linear range of the
LINE POT into a logarithmic scale, such that if the LINE POT is wound down to zero,
the amplification of each VCA is reduced by 12db relative to its centre position.
Similarly if the POT is wound to its maximum position, both amplifiers increase their
gain by 12dB.
The outputs of these amplification stages are then attenuated. Analogue switches
U404A and U404Bare used to select which attenuation circuit is used for Line 2, and
U404D and U404C are used to select which attenuation circuit is used for Line 1.
If the resistive divider formed by R425, R426, and R439 is selected then the Line 2
audio signal frequency response is unaffected (it is Flat). If the reactive divider defined
by C402, R431, and R439 is selected, then higher frequencies of the Line 2 audio signal
are attenuated less than lower frequencies, i.e. Pre-emphasis is applied to the audio
signal.
Line 1 has an identical circuit.
The outputs of these pre-emphasis/flat frequency response attenuators are then buffered
by U405A, and U405D respectively.
The microphone input is amplified by U400D, after being limited by D400. It is passed
through a pre-emphasis network (defined by C404, R433, and R436), and is enabled, or
disabled by switch U403D.
The outputs of the Line 1 conditioning circuit, the Line 2 conditioning circuit, and the
microphone input amplifier, are then mixed (summed) and amplified by U407A. Its
output is, in turn, amplified by U407B, but the gain of U407B is either 2.7 or 27
depending on the state of analogue switch U403B.
The CPU is capable of injecting a clipped (saturated) signal into the audio path. This
can be achieved via the two digital outputs DEV_H_L and TEST_DEV. This is
currently not used.
The output of U407B is passed (signal LINE_INP) to the Line Level Sense circuitry
(sheet 3) so that the CPU can determine the input line level.
U407B’s output is also passed to the limiter defined by D402, and D401. Resistors
R442, and R444 are used to “soften” the clipping, i.e. to “round off” the edges as the
voltage hits the clipping levels. This reduces the level of the lower order harmonics
produced.
U407C then buffers the output for mixing with the tone output circuitry.

Page 20 RF Technology T50
5 CIRCUIT DESCRIPTION
The PWR_CNTRL_RAW DAC output is used to control the bias to the on-board RF
amplifier (see Sheet 8). The CPU output pin PWR_CNTRL_HIGH is effectively
summed with the DAC output to define three control ranges:
State of PWR_CNTRL_HIGH PWRCNTRL Voltage Range
TriState 2.98 – 5.86
Low (0V) 0.6 – 3.0
High (5V) 3.55 - 5.96
Table 9: Power Control Ranges.
Note that in practice only the last two power ranges are used. The last is used when the
External Power Amplifier is the 38-50MHz model, and the middle is used otherwise.
U401 is an octal shift register and octal latch combined. When there is a rising edge on
LINEINP_DEN, the 8 shift register outputs are latched into the octal latch. The outputs
of the octal latch are the outputs Q0 to Q7. Thus the last 8 data bits clocked onto MOSI,
by SCLK, before LINEINP_DEN is clocked high, will appear on Q0 to Q7. This,
therefore, forms an inexpensive means for the CPU to increase its number of outputs.
U406 is a quad 8 bit DAC. The CPU communicates with the DAC via SCLK, MOSI,
and the select signal LINEINP_ADSEL, which is low when the DAC is selected.
U302B is used to convert the DAC output into a bias level for the LCD. The bias level,
would be adjusted for temperature, and as per a calibration procedure. Note that, at this
stage, the LCD display option is not developed.
5.5 Tone Generation Section (Sheet 5)
U500 is a CTCSS tone encoder and decoder. The integrated circuit is also capable of
generating and receiving DCSsignals, but at this stage this has not been implemented.
The CPU accesses U500 via the serial bus using MOSI, SCLK, and the low active
Select signal CTCSS_SEL.
The output of the tone generator is mixed (summed) with any signals that are allowed
through analogue switch U301D.
U502 is set up as a balanced differential amplifier. The resistors R530, R531, R508,
R509, R510, R532, R533, and R511, are precision resistors to improve the CMRR of
the differential amplifier.
U502A amplifies, as well as mixes, the two audio inputs, and its output is either passed
through a low pass filter (at 250Hz), or not, depending on the state of analogue switch
U301A.
The output of U502C is then attenuated by a digital POT, before being buffered by
U502D.