Rohm LAPIS SEMICONDUCTOR ML620Q503 User manual

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ML620Q503/Q504
User’s Manual
Issue Date: Apr.16, 2015
FEUL620Q504-01

ML620Q503/Q504 User’s Manual
FEUL620Q504 1
Notes
1) The information contained herein is subject to change without notice.
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http://www.lapis-semi.com/en/

ML620Q503/Q504 User’s Manual
FEUL620Q504 2
Preface
This manual describes the operation of the hardware of the 16-bit microcontroller
ML620Q503/Q504.
The following manuals are also available. Read them as necessary.
nX-U16/100 Core Instruction Manual
Description on the basic architecture and the each instruction of the nX-U16/100 Core.
MACU8 Assembler Package User’s Manual
Description on the method of operating the relocatable assembler, the linker, the
librarian, and the object converter and also on the specifications of the assembler
language.
CCU8 User’s Manual
Description on the method of operating the compiler.
CCU8 Programming Guide
Description on the method of programming.
CCU8 Language Reference
Description on the language specifications.
DTU8 Debugger User’s Manual
Description on the method of operating the debugger DTU8.
IDEU8 User’s Manual
Description on the integrated development environment IDEU8.
uEASE User’s Manual
Description on the on-chip debug tool uEASE.
uEASE connection Manual
Description about the connection between uEASE and ML620Q503/Q504.
FWuEASE Flash Writer Host Program User’s Manual
Description on the Flash Writer host program.

ML620Q503/Q504 User’s Manual
FEUL620Q504 3
Notation
Classification Notation Description
♦Numeric value xxh, xxH Indicates a hexadecimal number. x: Any value in the range of 0 to F
xxb Indicates a binary number; “b” may be omitted. x: A value 0 or 1
♦Unit word, W 1 word = 16 bits
byte, B 1 byte = 8 bits
nibble, N 1 nibble = 4 bits
maga-, M 106
kilo-, K 210 = 1024
kilo-, k 103= 1000
milli-, m 10-3
micro-, µ 10-6
nano-, n 10-9
second, s (lower case) second
♦Terminology “H” level, “1” level Indicates high voltage signal levels VIH and VOH as specified by the
electrical characteristics.
“L” level, “0” level Indicates low voltage signal levels VIL and VOL as specified by the
electrical characteristics.
♦Register description
R/W: Indicates that Read/Write attribute. “R” indicates that data can be read and “W” indicates that data can be
written. “R/W” indicates that data can be read or written.
MSB
LSB
FCON0 OUTC1 OUTC0 OSCM1 OSCM0 SYSC1 SYSC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
1
1
0
0
1
1
Bit name
Register name
Initial value after reset
Invalid bit: Write in an initial value when you write access

ML620Q503/Q504 User’s Manual
Contents
FEUL620Q504 contents–1
Table of Contents
Chapter 1
1. Overview...........................................................................................................................................1-1
1.1 Features....................................................................................................................................... 1-1
1.2 Configuration of Functional Blocks ............................................................................................ 1-5
1.2.1 Block Diagram of ML620Q503/504 ............................................................................1-5
1.3 Pins.........................................................................................................................................1-6
1.3.1 Pin Layout...................................................................................................................1-6
1.3.1.1 Pin Layout of ML620Q503/Q504 TQFP Package............................................1-6
1.3.2 List of Pins ..................................................................................................................1-7
1.3.2.1 List of Pins of ML620Q503/Q504 TQFP Package ...........................................1-7
1.3.3 Description of Pins....................................................................................................1-10
1.3.4 Termination of Unused Pins.....................................................................................1-13
Chapter 2
2. CPU and Memory Space..................................................................................................................2-1
2.1 General Description....................................................................................................................2-1
2.1.1 Features......................................................................................................................2-1
2.1.2 Notes When Executing SB/RB Instruction..................................................................2-1
2.2 Program Memory Space.............................................................................................................2-2
2.3 Data Memory Space ...................................................................................................................2-3
2.4 Instruction Length........................................................................................................................2-5
2.5 Data Type...............................................................................................................................2-5
2.6 Description of Registers .............................................................................................................2-5
2.6.1 List of Registers ..........................................................................................................2-5
2.6.2 Data Segment Register (DSR) ...................................................................................2-5
2.7 Multiplication/Division Coprocessor........................................................................................... 2-6
2.7.1General Description....................................................................................................2-6
2.7.2List of Registers ..........................................................................................................2-6
2.7.2.1 Registers A, B, C, and D (CR0 to CR7)............................................................ 2-7
2.7.2.2 Operation Mode Register (CR8)....................................................................... 2-8
2.7.2.3 Operation Status Register (CR9)...................................................................... 2-9
2.7.2.4 Coprocessor ID Register (CR15).................................................................... 2-10
2.7.3Description of Operation...........................................................................................2-11
Chapter 3
3. Reset Function..................................................................................................................................3-1
3.1 Overview......................................................................................................................................3-1
3.1.1 Features......................................................................................................................3-1
3.1.2 Configuration...............................................................................................................3-1
3.1.3 List of Pin ....................................................................................................................3-1
3.2 Description of Registers .............................................................................................................3-2
3.2.1 List of Registers ..........................................................................................................3-2
3.2.2 Reset Status Register (RSTAT)..................................................................................3-3
3.3 Description of Operation............................................................................................................. 3-4
3.3.1 Cause of Reset...........................................................................................................3-4
3.3.2 Operation of System Reset Mode...............................................................................3-4

ML620Q503/Q504 User’s Manual
Contents
FEUL620Q504 contents–2
Chapter 4
4. Power Management..........................................................................................................................4-1
4.1 General Description.....................................................................................................................4-1
4.1.1 Features......................................................................................................................4-1
4.1.2 Configuration...............................................................................................................4-1
4.2 Description of Registers ................................................................................................................ 4-2
4.2.1 Register Configuration List.........................................................................................4-2
4.2.2 Stop Code Acceptor (STPACP)..................................................................................4-3
4.2.3 Standby Control Register (SBYCON).........................................................................4-4
4.2.4 Block Control Register 01 (BLKCON01) ....................................................................4-5
4.2.5 Block Control Register 23 (BLKCON23) ....................................................................4-7
4.2.6 Block Control Register 45 (BLKCON45) ....................................................................4-9
4.3 Description of Operation.............................................................................................................4-11
4.3.1 HALT Mode...............................................................................................................4-11
4.3.1.1 HALT Mode..........................................................................................................4-11
4.3.1.2 DEEP-HALT Mode............................................................................................. 4-12
4.3.1.3 HALT-H Mode..................................................................................................... 4-13
4.3.2 STOP Mode..............................................................................................................4-14
4.3.2.1 Oscillation Stop and Restart Timing of Low-Speed Clock ................................... 4-14
4.3.2.2 Oscillation Stop and Restart Timing of High-Speed Clock................................... 4-15
4.3.2.3 Note on Return Operation from STOP/HALT/DEEP-HALT/HALT-H Mode.......... 4-17
4.3.3 Operation of Functions in STOP/HALT/DEEP-HALT/HALT-H Mode ......................4-18
4.3.4 Block Control Function..............................................................................................4-19
Chapter 5
5. Interrupts...........................................................................................................................................5-1
5.1 General Description.................................................................................................................... 5-1
5.1.1 Features.........................................................................................................................5-1
5.1.2 Configuration.................................................................................................................5-2
5.2 Description of Registers ............................................................................................................. 5-3
5.2.1 List of Registers..........................................................................................................5-3
5.2.2 Interrupt Enable Register 01 (IE01)............................................................................5-5
5.2.3 Interrupt Enable Register 23 (IE23)............................................................................5-7
5.2.4 Interrupt Enable Register 45 (IE45)............................................................................5-9
5.2.5 Interrupt Enable Register 67 (IE67)..........................................................................5-11
5.2.6 Interrupt Request Register 01 (IRQ01) ....................................................................5-13
5.2.7 Interrupt Request Register 23 (IRQ23) ....................................................................5-16
5.2.8 Interrupt Request Register 45 (IRQ45) ....................................................................5-19
5.2.9 Interrupt Request Register 67 (IRQ67) ....................................................................5-22
5.2.10 Interrupt Level Control Enable Register (ILEN)......................................................5-24
5.2.11 Current Interrupt Request Level Register (CIL)......................................................5-25
5.2.12 Interrupt Level Control Register 1 (ILC1) ...............................................................5-27
5.2.13 Interrupt Level Control Register 2 (ILC2) ...............................................................5-29
5.2.14 Interrupt Level Control Register 3 (ILC3) ...............................................................5-31
5.2.15 Interrupt Level Control Register 4 (ILC4) ...............................................................5-33
5.2.16 Interrupt Level Control Register 5 (ILC5) ...............................................................5-35
5.2.17 Interrupt Level Control Register 6 (ILC6) ...............................................................5-37
5.2.18 Interrupt Level Control Register 7 (ILC7) ...............................................................5-39
5.2.19 External Interrupt Control Registers 01 (EXICON01).............................................5-41
5.2.20 External Interrupt Control Registers 23 (EXICON23).............................................5-42
5.2.21 External Interrupt 0/1 Selection Register (EXI01SEL) ...........................................5-43
5.2.22 External Interrupt 2/3 Selection Register (EXI23SEL) ...........................................5-45
5.2.23 External Interrupt 4/5 Selection Register (EXI45SEL)...........................................5-47
5.2.24 External Interrupt 6/7 Selection Register (EXI67SEL) ...........................................5-49

ML620Q503/Q504 User’s Manual
Contents
FEUL620Q504 contents–3
5.3 Description of Operation........................................................................................................... 5-51
5.3.1 Interrupt Source........................................................................................................5-51
5.3.2 Maskable Interrupt Processing.................................................................................5-53
5.3.3 Non-Maskable Interrupt Processing.........................................................................5-53
5.3.4 Software Interrupt Processing..................................................................................5-53
5.3.5 Notes on Interrupt Routine........................................................................................5-54
5.3.6 Interrupt Processing When Interrupt Level Control Enabled....................................5-58
5.3.7 Flow Chart (When Interrupt Level Control Enabled)................................................5-59
5.3.8 Interrupt Disable State..............................................................................................5-61
5.3.9 External Interrupt......................................................................................................5-62
Chapter 6
6. Clock Generation Circuit...................................................................................................................6-1
6.1 General Description.................................................................................................................... 6-1
6.1.1 Features......................................................................................................................6-1
6.1.2 Configuration...............................................................................................................6-1
6.1.3 List of Pins ..................................................................................................................6-3
6.1.4 Clock Configuration Diagram......................................................................................6-4
6.2 Description of Registers ............................................................................................................. 6-5
6.2.1 List of Registers..........................................................................................................6-5
6.2.2 Frequency Control Register 01 (FCON01).................................................................6-6
6.2.3 Frequency Control Register 23 (FCON23).................................................................6-9
6.2.4 Frequency Status Register (FSTAT)........................................................................6-11
6.3 Description of Operation........................................................................................................... 6-12
6.3.1 Low-Speed Clock......................................................................................................6-12
6.3.1.1 Low-Speed Built-in RC Oscillation Mode........................................................... 6-12
6.3.1.2 Low-Speed Crystal Oscillation Mode.................................................................. 6-12
6.3.1.3 Low-Speed External Clock Input Mode.............................................................. 6-13
6.3.1.4 Low-Speed Built-In RC Oscillation Mode Operation......................................... 6-14
6.3.1.5 Low-Speed Crystal Oscillation Mode Operation................................................ 6-15
6.3.1.6 Low-Speed External Clock Mode Operation...................................................... 6-16
6.3.2High-Speed Clock.....................................................................................................6-17
6.3.2.1 High-Speed Built-in RC Oscillation Mode.......................................................... 6-17
6.3.2.2 High-Speed Crystal/Ceramic Oscillation Mode.................................................. 6-17
6.3.2.3 High-Speed External Clock Input Mode............................................................. 6-18
6.3.2.4 High-Speed Built-In RC Oscillation Mode Operation ........................................ 6-19
6.3.2.5 High-Speed Crystal/Ceramic Oscillation Mode Operation................................ 6-20
6.3.2.6 High-Speed External Clock Mode Operation..................................................... 6-23
6.3.3 Switching of System Clock .......................................................................................6-25
6.3.4Low-speed oscillation clock switch interrupt.............................................................6-26
Chapter 7
7. Time Base Counter...........................................................................................................................7-1
7.1 Overview...................................................................................................................................... 7-1
7.1.1 Features......................................................................................................................7-1
7.1.2 Configuration...............................................................................................................7-1
7.2 Description of Registers ............................................................................................................. 7-2
7.2.1 List of Registers..........................................................................................................7-2
7.2.2 Low-Speed Time Base Counter (LTBR).....................................................................7-3
7.2.3 Low-Speed Time Base Counter Frequency Adjustment Registers (LTBADJ)...........7-4
7.2.4 Low-Speed Time Base Counter Interrupt select Registers (LTBINT)........................7-6
7.3 Description of Operation............................................................................................................. 7-7
7.3.1 Low-Speed Time Base Counter .................................................................................7-7

ML620Q503/Q504 User’s Manual
Contents
FEUL620Q504 contents–4
Chapter 8
8. Timers...............................................................................................................................................8-1
8.1 Overview...................................................................................................................................... 8-1
8.1.1 Features......................................................................................................................8-1
8.1.2 Configuration...............................................................................................................8-1
8.2 Description of Registers ............................................................................................................. 8-3
8.2.1 List of Registers..........................................................................................................8-3
8.2.2 Timer n Data Register (TMnmD : {n,m}={0,1}, {2,3}, {4,5}, {6,7}) ..............................8-4
8.2.3 Timer n Counter Register (TMnmC : {n,m}={0,1}, {2,3}, {4,5}, {6,7}).........................8-5
8.2.4 Timer n Control Register (TMnmCON : {n,m}={0,1}, {2,3}, {4,5}, {6,7})..................... 8-6
8.2.5 Timer Start Register 0 (TMSTR0)...............................................................................8-8
8.2.6 Timer Stop Register 0 (TMSTP0)...............................................................................8-9
8.2.7 Timer Status Register 0 (TMSTAT0)........................................................................8-10
8.3 Description of operation............................................................................................................ 8-11
8.3.1 Normal timer mode operation...................................................................................8-11
8.3.2 One shot timer mode operation................................................................................8-12
8.3.3 16bit timer mode ........................................................................................................8-12
Chapter 9
9. Function Timer (FTM).......................................................................................................................9-1
9.1 General Description.................................................................................................................... 9-1
9.1.1 Features......................................................................................................................9-1
9.1.2 Configuration...............................................................................................................9-2
9.1.3 List of Pins ..................................................................................................................9-3
9.2 Description of Registers ............................................................................................................. 9-4
9.2.1 List of Registers..........................................................................................................9-4
9.2.2 FTMn Period Register (FTnP : n=0,1,2,3)..................................................................9-7
9.2.3 FTMn Event Register A (FTnEA : n=0,1,2,3).............................................................9-8
9.2.4 FTMn Event Register B (FTnEB : n=0,1,2,3).............................................................9-9
9.2.5 FTMn DeadTime Register (FTnDT : n=0,1,2,3).......................................................9-10
9.2.6 FTMn Counter Register (FTnC : n=0,1,2,3).............................................................9-11
9.2.7 FTMn Control Register 0 (FTnCON0 : n=0,1,2,3)....................................................9-12
9.2.8 FTMn Control Register 1 (FTnCON1 : n=0,1,2,3)....................................................9-13
9.2.9 FTMn Mode Register (FTnMOD : n=0,1,2,3)...........................................................9-15
9.2.10 FTMn Clock Register (FTnCLK : n=0,1,2,3)...........................................................9-17
9.2.11 FTMn Trigger Register 0 (FTnTRG0 : n=0,1,2,3)...................................................9-19
9.2.12 FTMn Trigger Register 1 (FTnTRG1 : n=0,1,2,3)...................................................9-21
9.2.13 FTMn Interrupt Enable Register (FTnINTE: n = 0,1,2,3)........................................9-22
9.2.14 FTMn Interrupt Status Register (FTnINTS : n=0,1,2,3)..........................................9-24
9.2.15 FTMn Interrupt Clear Register (FTnINTC : n=0,1,2,3)...........................................9-26
9.2.16 FTM Output nm Select Register (FTOnmSL : n = 0,2,4,6,8,A,C,E, m=n+1) .........9-27
9.3 Description of Operation........................................................................................................... 9-29
9.3.1 Common Sequence..................................................................................................9-29
9.3.2 Counter Operation....................................................................................................9-31
9.3.2.1 Starting/Stopping Counting by Software.......................................................... 9-31
9.3.2.2 Starting/Stopping Counting by TriggerEvent................................................... 9-31
9.3.3 TIMER Mode Operation............................................................................................9-32
9.3.3.1 Output Waveform in TIMER Mode................................................................... 9-32
9.3.4 PWM1 Mode Operation............................................................................................9-35
9.3.4.1 Output Waveform in PWM1 Mode ................................................................... 9-35
9.3.5 PWM2 Mode Operation............................................................................................9-37
9.3.5.1 OutputWaveform in PWM2 Mode..................................................................... 9-37
9.3.6 CAPTURE Mode Operation......................................................................................9-40
9.3.6.1 Measurement Example in the CAPTUREMode.............................................. 9-40

ML620Q503/Q504 User’s Manual
Contents
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9.3.7 Event/Emergency Stop Trigger Control....................................................................9-42
9.3.7.1 Trigger Signal..................................................................................................... 9-42
9.3.7.2 Start/Stop Operations by EventTrigger............................................................ 9-43
9.3.7.3Emergency StopOperation ............................................................................... 9-43
9.3.8 Output at Counter Stop.............................................................................................9-45
9.3.9 Changing Period, Event A/B, and Dead Time during Operation..............................9-46
9.3.10 Interrupt Source......................................................................................................9-47
Chapter 10
10. Watchdog Timer ...........................................................................................................................10-1
10.1 Overview.................................................................................................................................. 10-1
10.1.1 Features..................................................................................................................10-1
10.1.2 Configuration...........................................................................................................10-1
10.2 Description of Registers.......................................................................................................... 10-2
10.2.1 List of Registers......................................................................................................10-2
10.2.2 Watchdog Timer Control Register (WDTCON)......................................................10-3
10.2.3 Watchdog Timer Mode Register (WDTMOD).........................................................10-4
10.3 Description of Operation......................................................................................................... 10-5
10.3.1 The process example when not using Watchdog Timer........................................10-7
Chapter 11
11. Synchronous Serial Port...............................................................................................................11-1
11.1 Overview .................................................................................................................................. 11-1
11.1.1 Features..................................................................................................................11-1
11.1.2 Configuration...........................................................................................................11-1
11.1.3 List of Pins ..............................................................................................................11-1
11.2 Description of Registers.......................................................................................................... 11-2
11.2.1 List of Registers......................................................................................................11-2
11.2.2 Serial Port 0 Transmit/Receive Buffers (SIO0BUF)...............................................11-3
11.2.3 Serial Port Control Register (SIO0CON)................................................................11-4
11.2.4 Serial Port Mode Register (SIO0MOD)................................................................11-5
11.3 Description of Operation......................................................................................................... 11-7
11.3.1 Transmit Operation.................................................................................................11-7
11.3.2 Receive Operation..................................................................................................11-9
11.3.3 Transmit/Receive Operation.................................................................................11-11
11.3.4 Pin Settings...........................................................................................................11-11
Chapter 12
12. Synchronous Serial Port with FIFO (SSIOF)................................................................................12-1
12.1 General Description ................................................................................................................12-1
12.1.1 Features..................................................................................................................12-1
12.1.2 Configuration...........................................................................................................12-2
12.1.3 List of Pins ..............................................................................................................12-2
12.2 Description of Registers..........................................................................................................12-3
12.2.1 List of Registers......................................................................................................12-3
12.2.2 SIOF0 Control Register (SF0CTRL).......................................................................12-4
12.2.3 SIOF0 Interrupt Control Register (SF0INTC).........................................................12-6
12.2.4 SIOF0 Transfer Interval Control Register (SF0TRAC)...........................................12-8
12.2.5 SIOF0 Baud Rate Register (SF0BRR)...................................................................12-9
12.2.6 SIOF0 Status Register (SF0SRR)........................................................................12-11
12.2.7 SIOF0 Status Clear Register (SF0SRC)..............................................................12-14
12.2.8 SIOF0 FIFO Status Register (SF0FSR)...............................................................12-16
12.2.9 SIOF0 Write Data Register (SF0DWR)................................................................12-17
12.2.10 SIOF0 Read Data Register (SF0DRR)...............................................................12-18