Rohm LAPIS SEMICONDUCTOR ML620Q503 User manual

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ML620Q503/Q504
User’s Manual
Issue Date: Apr.16, 2015
FEUL620Q504-01

ML620Q503/Q504 User’s Manual
FEUL620Q504 1
Notes
1) The information contained herein is subject to change without notice.
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http://www.lapis-semi.com/en/

ML620Q503/Q504 User’s Manual
FEUL620Q504 2
Preface
This manual describes the operation of the hardware of the 16-bit microcontroller
ML620Q503/Q504.
The following manuals are also available. Read them as necessary.
nX-U16/100 Core Instruction Manual
Description on the basic architecture and the each instruction of the nX-U16/100 Core.
MACU8 Assembler Package User’s Manual
Description on the method of operating the relocatable assembler, the linker, the
librarian, and the object converter and also on the specifications of the assembler
language.
CCU8 User’s Manual
Description on the method of operating the compiler.
CCU8 Programming Guide
Description on the method of programming.
CCU8 Language Reference
Description on the language specifications.
DTU8 Debugger User’s Manual
Description on the method of operating the debugger DTU8.
IDEU8 User’s Manual
Description on the integrated development environment IDEU8.
uEASE User’s Manual
Description on the on-chip debug tool uEASE.
uEASE connection Manual
Description about the connection between uEASE and ML620Q503/Q504.
FWuEASE Flash Writer Host Program User’s Manual
Description on the Flash Writer host program.

ML620Q503/Q504 User’s Manual
FEUL620Q504 3
Notation
Classification Notation Description
♦Numeric value xxh, xxH Indicates a hexadecimal number. x: Any value in the range of 0 to F
xxb Indicates a binary number; “b” may be omitted. x: A value 0 or 1
♦Unit word, W 1 word = 16 bits
byte, B 1 byte = 8 bits
nibble, N 1 nibble = 4 bits
maga-, M 106
kilo-, K 210 = 1024
kilo-, k 103= 1000
milli-, m 10-3
micro-, µ 10-6
nano-, n 10-9
second, s (lower case) second
♦Terminology “H” level, “1” level Indicates high voltage signal levels VIH and VOH as specified by the
electrical characteristics.
“L” level, “0” level Indicates low voltage signal levels VIL and VOL as specified by the
electrical characteristics.
♦Register description
R/W: Indicates that Read/Write attribute. “R” indicates that data can be read and “W” indicates that data can be
written. “R/W” indicates that data can be read or written.
MSB
LSB
FCON0 OUTC1 OUTC0 OSCM1 OSCM0 SYSC1 SYSC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
1
1
0
0
1
1
Bit name
Register name
Initial value after reset
Invalid bit: Write in an initial value when you write access

ML620Q503/Q504 User’s Manual
Contents
FEUL620Q504 contents–1
Table of Contents
Chapter 1
1. Overview...........................................................................................................................................1-1
1.1 Features....................................................................................................................................... 1-1
1.2 Configuration of Functional Blocks ............................................................................................ 1-5
1.2.1 Block Diagram of ML620Q503/504 ............................................................................1-5
1.3 Pins.........................................................................................................................................1-6
1.3.1 Pin Layout...................................................................................................................1-6
1.3.1.1 Pin Layout of ML620Q503/Q504 TQFP Package............................................1-6
1.3.2 List of Pins ..................................................................................................................1-7
1.3.2.1 List of Pins of ML620Q503/Q504 TQFP Package ...........................................1-7
1.3.3 Description of Pins....................................................................................................1-10
1.3.4 Termination of Unused Pins.....................................................................................1-13
Chapter 2
2. CPU and Memory Space..................................................................................................................2-1
2.1 General Description....................................................................................................................2-1
2.1.1 Features......................................................................................................................2-1
2.1.2 Notes When Executing SB/RB Instruction..................................................................2-1
2.2 Program Memory Space.............................................................................................................2-2
2.3 Data Memory Space ...................................................................................................................2-3
2.4 Instruction Length........................................................................................................................2-5
2.5 Data Type...............................................................................................................................2-5
2.6 Description of Registers .............................................................................................................2-5
2.6.1 List of Registers ..........................................................................................................2-5
2.6.2 Data Segment Register (DSR) ...................................................................................2-5
2.7 Multiplication/Division Coprocessor........................................................................................... 2-6
2.7.1General Description....................................................................................................2-6
2.7.2List of Registers ..........................................................................................................2-6
2.7.2.1 Registers A, B, C, and D (CR0 to CR7)............................................................ 2-7
2.7.2.2 Operation Mode Register (CR8)....................................................................... 2-8
2.7.2.3 Operation Status Register (CR9)...................................................................... 2-9
2.7.2.4 Coprocessor ID Register (CR15).................................................................... 2-10
2.7.3Description of Operation...........................................................................................2-11
Chapter 3
3. Reset Function..................................................................................................................................3-1
3.1 Overview......................................................................................................................................3-1
3.1.1 Features......................................................................................................................3-1
3.1.2 Configuration...............................................................................................................3-1
3.1.3 List of Pin ....................................................................................................................3-1
3.2 Description of Registers .............................................................................................................3-2
3.2.1 List of Registers ..........................................................................................................3-2
3.2.2 Reset Status Register (RSTAT)..................................................................................3-3
3.3 Description of Operation............................................................................................................. 3-4
3.3.1 Cause of Reset...........................................................................................................3-4
3.3.2 Operation of System Reset Mode...............................................................................3-4

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Contents
FEUL620Q504 contents–2
Chapter 4
4. Power Management..........................................................................................................................4-1
4.1 General Description.....................................................................................................................4-1
4.1.1 Features......................................................................................................................4-1
4.1.2 Configuration...............................................................................................................4-1
4.2 Description of Registers ................................................................................................................ 4-2
4.2.1 Register Configuration List.........................................................................................4-2
4.2.2 Stop Code Acceptor (STPACP)..................................................................................4-3
4.2.3 Standby Control Register (SBYCON).........................................................................4-4
4.2.4 Block Control Register 01 (BLKCON01) ....................................................................4-5
4.2.5 Block Control Register 23 (BLKCON23) ....................................................................4-7
4.2.6 Block Control Register 45 (BLKCON45) ....................................................................4-9
4.3 Description of Operation.............................................................................................................4-11
4.3.1 HALT Mode...............................................................................................................4-11
4.3.1.1 HALT Mode..........................................................................................................4-11
4.3.1.2 DEEP-HALT Mode............................................................................................. 4-12
4.3.1.3 HALT-H Mode..................................................................................................... 4-13
4.3.2 STOP Mode..............................................................................................................4-14
4.3.2.1 Oscillation Stop and Restart Timing of Low-Speed Clock ................................... 4-14
4.3.2.2 Oscillation Stop and Restart Timing of High-Speed Clock................................... 4-15
4.3.2.3 Note on Return Operation from STOP/HALT/DEEP-HALT/HALT-H Mode.......... 4-17
4.3.3 Operation of Functions in STOP/HALT/DEEP-HALT/HALT-H Mode ......................4-18
4.3.4 Block Control Function..............................................................................................4-19
Chapter 5
5. Interrupts...........................................................................................................................................5-1
5.1 General Description.................................................................................................................... 5-1
5.1.1 Features.........................................................................................................................5-1
5.1.2 Configuration.................................................................................................................5-2
5.2 Description of Registers ............................................................................................................. 5-3
5.2.1 List of Registers..........................................................................................................5-3
5.2.2 Interrupt Enable Register 01 (IE01)............................................................................5-5
5.2.3 Interrupt Enable Register 23 (IE23)............................................................................5-7
5.2.4 Interrupt Enable Register 45 (IE45)............................................................................5-9
5.2.5 Interrupt Enable Register 67 (IE67)..........................................................................5-11
5.2.6 Interrupt Request Register 01 (IRQ01) ....................................................................5-13
5.2.7 Interrupt Request Register 23 (IRQ23) ....................................................................5-16
5.2.8 Interrupt Request Register 45 (IRQ45) ....................................................................5-19
5.2.9 Interrupt Request Register 67 (IRQ67) ....................................................................5-22
5.2.10 Interrupt Level Control Enable Register (ILEN)......................................................5-24
5.2.11 Current Interrupt Request Level Register (CIL)......................................................5-25
5.2.12 Interrupt Level Control Register 1 (ILC1) ...............................................................5-27
5.2.13 Interrupt Level Control Register 2 (ILC2) ...............................................................5-29
5.2.14 Interrupt Level Control Register 3 (ILC3) ...............................................................5-31
5.2.15 Interrupt Level Control Register 4 (ILC4) ...............................................................5-33
5.2.16 Interrupt Level Control Register 5 (ILC5) ...............................................................5-35
5.2.17 Interrupt Level Control Register 6 (ILC6) ...............................................................5-37
5.2.18 Interrupt Level Control Register 7 (ILC7) ...............................................................5-39
5.2.19 External Interrupt Control Registers 01 (EXICON01).............................................5-41
5.2.20 External Interrupt Control Registers 23 (EXICON23).............................................5-42
5.2.21 External Interrupt 0/1 Selection Register (EXI01SEL) ...........................................5-43
5.2.22 External Interrupt 2/3 Selection Register (EXI23SEL) ...........................................5-45
5.2.23 External Interrupt 4/5 Selection Register (EXI45SEL)...........................................5-47
5.2.24 External Interrupt 6/7 Selection Register (EXI67SEL) ...........................................5-49

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Contents
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5.3 Description of Operation........................................................................................................... 5-51
5.3.1 Interrupt Source........................................................................................................5-51
5.3.2 Maskable Interrupt Processing.................................................................................5-53
5.3.3 Non-Maskable Interrupt Processing.........................................................................5-53
5.3.4 Software Interrupt Processing..................................................................................5-53
5.3.5 Notes on Interrupt Routine........................................................................................5-54
5.3.6 Interrupt Processing When Interrupt Level Control Enabled....................................5-58
5.3.7 Flow Chart (When Interrupt Level Control Enabled)................................................5-59
5.3.8 Interrupt Disable State..............................................................................................5-61
5.3.9 External Interrupt......................................................................................................5-62
Chapter 6
6. Clock Generation Circuit...................................................................................................................6-1
6.1 General Description.................................................................................................................... 6-1
6.1.1 Features......................................................................................................................6-1
6.1.2 Configuration...............................................................................................................6-1
6.1.3 List of Pins ..................................................................................................................6-3
6.1.4 Clock Configuration Diagram......................................................................................6-4
6.2 Description of Registers ............................................................................................................. 6-5
6.2.1 List of Registers..........................................................................................................6-5
6.2.2 Frequency Control Register 01 (FCON01).................................................................6-6
6.2.3 Frequency Control Register 23 (FCON23).................................................................6-9
6.2.4 Frequency Status Register (FSTAT)........................................................................6-11
6.3 Description of Operation........................................................................................................... 6-12
6.3.1 Low-Speed Clock......................................................................................................6-12
6.3.1.1 Low-Speed Built-in RC Oscillation Mode........................................................... 6-12
6.3.1.2 Low-Speed Crystal Oscillation Mode.................................................................. 6-12
6.3.1.3 Low-Speed External Clock Input Mode.............................................................. 6-13
6.3.1.4 Low-Speed Built-In RC Oscillation Mode Operation......................................... 6-14
6.3.1.5 Low-Speed Crystal Oscillation Mode Operation................................................ 6-15
6.3.1.6 Low-Speed External Clock Mode Operation...................................................... 6-16
6.3.2High-Speed Clock.....................................................................................................6-17
6.3.2.1 High-Speed Built-in RC Oscillation Mode.......................................................... 6-17
6.3.2.2 High-Speed Crystal/Ceramic Oscillation Mode.................................................. 6-17
6.3.2.3 High-Speed External Clock Input Mode............................................................. 6-18
6.3.2.4 High-Speed Built-In RC Oscillation Mode Operation ........................................ 6-19
6.3.2.5 High-Speed Crystal/Ceramic Oscillation Mode Operation................................ 6-20
6.3.2.6 High-Speed External Clock Mode Operation..................................................... 6-23
6.3.3 Switching of System Clock .......................................................................................6-25
6.3.4Low-speed oscillation clock switch interrupt.............................................................6-26
Chapter 7
7. Time Base Counter...........................................................................................................................7-1
7.1 Overview...................................................................................................................................... 7-1
7.1.1 Features......................................................................................................................7-1
7.1.2 Configuration...............................................................................................................7-1
7.2 Description of Registers ............................................................................................................. 7-2
7.2.1 List of Registers..........................................................................................................7-2
7.2.2 Low-Speed Time Base Counter (LTBR).....................................................................7-3
7.2.3 Low-Speed Time Base Counter Frequency Adjustment Registers (LTBADJ)...........7-4
7.2.4 Low-Speed Time Base Counter Interrupt select Registers (LTBINT)........................7-6
7.3 Description of Operation............................................................................................................. 7-7
7.3.1 Low-Speed Time Base Counter .................................................................................7-7

ML620Q503/Q504 User’s Manual
Contents
FEUL620Q504 contents–4
Chapter 8
8. Timers...............................................................................................................................................8-1
8.1 Overview...................................................................................................................................... 8-1
8.1.1 Features......................................................................................................................8-1
8.1.2 Configuration...............................................................................................................8-1
8.2 Description of Registers ............................................................................................................. 8-3
8.2.1 List of Registers..........................................................................................................8-3
8.2.2 Timer n Data Register (TMnmD : {n,m}={0,1}, {2,3}, {4,5}, {6,7}) ..............................8-4
8.2.3 Timer n Counter Register (TMnmC : {n,m}={0,1}, {2,3}, {4,5}, {6,7}).........................8-5
8.2.4 Timer n Control Register (TMnmCON : {n,m}={0,1}, {2,3}, {4,5}, {6,7})..................... 8-6
8.2.5 Timer Start Register 0 (TMSTR0)...............................................................................8-8
8.2.6 Timer Stop Register 0 (TMSTP0)...............................................................................8-9
8.2.7 Timer Status Register 0 (TMSTAT0)........................................................................8-10
8.3 Description of operation............................................................................................................ 8-11
8.3.1 Normal timer mode operation...................................................................................8-11
8.3.2 One shot timer mode operation................................................................................8-12
8.3.3 16bit timer mode ........................................................................................................8-12
Chapter 9
9. Function Timer (FTM).......................................................................................................................9-1
9.1 General Description.................................................................................................................... 9-1
9.1.1 Features......................................................................................................................9-1
9.1.2 Configuration...............................................................................................................9-2
9.1.3 List of Pins ..................................................................................................................9-3
9.2 Description of Registers ............................................................................................................. 9-4
9.2.1 List of Registers..........................................................................................................9-4
9.2.2 FTMn Period Register (FTnP : n=0,1,2,3)..................................................................9-7
9.2.3 FTMn Event Register A (FTnEA : n=0,1,2,3).............................................................9-8
9.2.4 FTMn Event Register B (FTnEB : n=0,1,2,3).............................................................9-9
9.2.5 FTMn DeadTime Register (FTnDT : n=0,1,2,3).......................................................9-10
9.2.6 FTMn Counter Register (FTnC : n=0,1,2,3).............................................................9-11
9.2.7 FTMn Control Register 0 (FTnCON0 : n=0,1,2,3)....................................................9-12
9.2.8 FTMn Control Register 1 (FTnCON1 : n=0,1,2,3)....................................................9-13
9.2.9 FTMn Mode Register (FTnMOD : n=0,1,2,3)...........................................................9-15
9.2.10 FTMn Clock Register (FTnCLK : n=0,1,2,3)...........................................................9-17
9.2.11 FTMn Trigger Register 0 (FTnTRG0 : n=0,1,2,3)...................................................9-19
9.2.12 FTMn Trigger Register 1 (FTnTRG1 : n=0,1,2,3)...................................................9-21
9.2.13 FTMn Interrupt Enable Register (FTnINTE: n = 0,1,2,3)........................................9-22
9.2.14 FTMn Interrupt Status Register (FTnINTS : n=0,1,2,3)..........................................9-24
9.2.15 FTMn Interrupt Clear Register (FTnINTC : n=0,1,2,3)...........................................9-26
9.2.16 FTM Output nm Select Register (FTOnmSL : n = 0,2,4,6,8,A,C,E, m=n+1) .........9-27
9.3 Description of Operation........................................................................................................... 9-29
9.3.1 Common Sequence..................................................................................................9-29
9.3.2 Counter Operation....................................................................................................9-31
9.3.2.1 Starting/Stopping Counting by Software.......................................................... 9-31
9.3.2.2 Starting/Stopping Counting by TriggerEvent................................................... 9-31
9.3.3 TIMER Mode Operation............................................................................................9-32
9.3.3.1 Output Waveform in TIMER Mode................................................................... 9-32
9.3.4 PWM1 Mode Operation............................................................................................9-35
9.3.4.1 Output Waveform in PWM1 Mode ................................................................... 9-35
9.3.5 PWM2 Mode Operation............................................................................................9-37
9.3.5.1 OutputWaveform in PWM2 Mode..................................................................... 9-37
9.3.6 CAPTURE Mode Operation......................................................................................9-40
9.3.6.1 Measurement Example in the CAPTUREMode.............................................. 9-40

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9.3.7 Event/Emergency Stop Trigger Control....................................................................9-42
9.3.7.1 Trigger Signal..................................................................................................... 9-42
9.3.7.2 Start/Stop Operations by EventTrigger............................................................ 9-43
9.3.7.3Emergency StopOperation ............................................................................... 9-43
9.3.8 Output at Counter Stop.............................................................................................9-45
9.3.9 Changing Period, Event A/B, and Dead Time during Operation..............................9-46
9.3.10 Interrupt Source......................................................................................................9-47
Chapter 10
10. Watchdog Timer ...........................................................................................................................10-1
10.1 Overview.................................................................................................................................. 10-1
10.1.1 Features..................................................................................................................10-1
10.1.2 Configuration...........................................................................................................10-1
10.2 Description of Registers.......................................................................................................... 10-2
10.2.1 List of Registers......................................................................................................10-2
10.2.2 Watchdog Timer Control Register (WDTCON)......................................................10-3
10.2.3 Watchdog Timer Mode Register (WDTMOD).........................................................10-4
10.3 Description of Operation......................................................................................................... 10-5
10.3.1 The process example when not using Watchdog Timer........................................10-7
Chapter 11
11. Synchronous Serial Port...............................................................................................................11-1
11.1 Overview .................................................................................................................................. 11-1
11.1.1 Features..................................................................................................................11-1
11.1.2 Configuration...........................................................................................................11-1
11.1.3 List of Pins ..............................................................................................................11-1
11.2 Description of Registers.......................................................................................................... 11-2
11.2.1 List of Registers......................................................................................................11-2
11.2.2 Serial Port 0 Transmit/Receive Buffers (SIO0BUF)...............................................11-3
11.2.3 Serial Port Control Register (SIO0CON)................................................................11-4
11.2.4 Serial Port Mode Register (SIO0MOD)................................................................11-5
11.3 Description of Operation......................................................................................................... 11-7
11.3.1 Transmit Operation.................................................................................................11-7
11.3.2 Receive Operation..................................................................................................11-9
11.3.3 Transmit/Receive Operation.................................................................................11-11
11.3.4 Pin Settings...........................................................................................................11-11
Chapter 12
12. Synchronous Serial Port with FIFO (SSIOF)................................................................................12-1
12.1 General Description ................................................................................................................12-1
12.1.1 Features..................................................................................................................12-1
12.1.2 Configuration...........................................................................................................12-2
12.1.3 List of Pins ..............................................................................................................12-2
12.2 Description of Registers..........................................................................................................12-3
12.2.1 List of Registers......................................................................................................12-3
12.2.2 SIOF0 Control Register (SF0CTRL).......................................................................12-4
12.2.3 SIOF0 Interrupt Control Register (SF0INTC).........................................................12-6
12.2.4 SIOF0 Transfer Interval Control Register (SF0TRAC)...........................................12-8
12.2.5 SIOF0 Baud Rate Register (SF0BRR)...................................................................12-9
12.2.6 SIOF0 Status Register (SF0SRR)........................................................................12-11
12.2.7 SIOF0 Status Clear Register (SF0SRC)..............................................................12-14
12.2.8 SIOF0 FIFO Status Register (SF0FSR)...............................................................12-16
12.2.9 SIOF0 Write Data Register (SF0DWR)................................................................12-17
12.2.10 SIOF0 Read Data Register (SF0DRR)...............................................................12-18

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12.3 Description of Operation.......................................................................................................12-19
12.3.1 Master Mode and Slave Mode..............................................................................12-19
12.3.2 Control of Polarity and Phase of Serial Clock......................................................12-19
12.3.3 Data Transfer Timing When SF0CPHA Is "0"......................................................12-19
12.3.4 Data Transfer Timing When SF0CPHA Is "1"......................................................12-20
12.3.5 Serial Clock Baud Rate.........................................................................................12-20
12.3.6 Transfer Size.........................................................................................................12-21
12.3.7 Transfer Interval Setting .......................................................................................12-22
12.3.8 Transmit Operation (Master Mode) ......................................................................12-24
12.3.9 Receive Operation (Master Mode) .......................................................................12-25
12.3.10 FIFO Operation...................................................................................................12-26
12.3.11 Write Overflow ....................................................................................................12-26
12.3.12 Overrun Error......................................................................................................12-26
12.3.13 FIFO Clearance ..................................................................................................12-26
12.3.14 Transfer When Slave Has Different Number of FIFO Transfer Bytes/Words....12-27
12.3.15 Mode Fault (MDF)...............................................................................................12-28
12.3.16 Interrupt Source..................................................................................................12-29
12.3.16.1 SSIOF Interrupt Source..............................................................................12-29
12.3.16.2 Clear SSIOF Interrupt.................................................................................12-29
12.3.16.3 SSIOF Interrupt Timing...............................................................................12-29
12.3.16.4 Interrupt processing flow.............................................................................12-30
12.3.17 Hi-Z Operation ....................................................................................................12-31
12.3.18 Interval from SF0MST Setting to Transfer Start.................................................12-31
12.3.19 Pin Settings.........................................................................................................12-31
Chapter 13
13.UART............................................................................................................................................13-1
13.1 General Description ................................................................................................................13-1
13.1.1 Features..................................................................................................................13-1
13.1.2 Configuration...........................................................................................................13-1
13.1.3 List of Pins ..............................................................................................................13-2
13.2 Description of Registers..........................................................................................................13-2
13.2.1 List of Registers......................................................................................................13-2
13.2.2 UART0 Receive Buffer (UA0BUF)..........................................................................13-3
13.2.3 UART0 Transmit Buffer (UA1BUF).........................................................................13-3
13.2.4 UART0 Control Register (UA0CON)......................................................................13-4
13.2.5 UART0 Transmit Monitor Register (UA1CON).......................................................13-5
13.2.6 UART0 Mode Register (UA0MOD).........................................................................13-6
13.2.7 UART0 Baud Rate Registers (UA0BRT)................................................................13-8
13.2.8 UART0 Receive Status Register (UA0STAT) ........................................................13-9
13.2.9 UART0 Transmit Status Register (UA1STAT).....................................................13-10
13.3 Description of Operation....................................................................................................... 13-11
13.3.1 Transfer Data Format ...........................................................................................13-11
13.3.2 Baud Rate.............................................................................................................13-12
13.3.3 Transmitted Data Direction...................................................................................13-13
13.3.4 Transmit Operation...............................................................................................13-14
13.3.5 Receive Operation................................................................................................13-16
13.3.5.1 Detection of Start Bit.....................................................................................13-18
13.3.5.2 Sampling Timing............................................................................................13-18
13.3.5.3 Receive Margin..............................................................................................13-19

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Chapter 14
14. UART with FIFO (UARTF)............................................................................................................14-1
14.1 General Description ................................................................................................................14-1
14.1.1 Features..................................................................................................................14-1
14.1.2 Configuration...........................................................................................................14-2
14.1.3 List of Pins ..............................................................................................................14-3
14.2 Description of Registers..........................................................................................................14-3
14.2.1 List of Registers......................................................................................................14-3
14.2.2 UARTF0 Transmit/Receive Buffer (UAF0BUF)......................................................14-4
14.2.3 UARTF0 Interrupt Enable Register (UAF0IER)......................................................14-5
14.2.4 UARTF0 Interrupt Status Register (UAF0IIR)........................................................14-6
14.2.5 UARTF0 Mode Register (UAF0MOD)....................................................................14-8
14.2.6 UARTF0 Line Status Register (UAF0LSR) ..........................................................14-11
14.2.7 UARTF0 Clock Adjustment Register (UAF0CAJ) ................................................14-14
14.2.8 UARTF0 Interrupt Request Register (UAF0IRQ).................................................14-15
14.3 Description of Operation.......................................................................................................14-16
14.3.1 Data Transmission................................................................................................14-16
14.3.2 Data Reception.....................................................................................................14-17
14.3.3 Baud Rate Clock Generation................................................................................14-19
14.3.4 FIFO Mode............................................................................................................14-20
14.3.5 FIFO Polled Mode.................................................................................................14-21
14.3.6 Error Status...........................................................................................................14-22
14.3.7Reset By Block Control Register..........................................................................14-23
Chapter 15
15. I2C Bus Interface...........................................................................................................................15-1
15.1 General Description ................................................................................................................15-1
15.1.1 Features..................................................................................................................15-1
15.1.2 Configuration...........................................................................................................15-1
15.1.3 List of Pins ..............................................................................................................15-1
15.2 Description of Registers..........................................................................................................15-2
15.2.1 List of Registers......................................................................................................15-2
15.2.2 I2C Bus n Receive Data Register (I2CnRD : n=0,1)...............................................15-3
15.2.3 I2C Bus n Slave Address Register (I2CnSA : n=0,1)..............................................15-4
15.2.4 I2C Bus n Transmit Data Register (I2CnTD : n=0,1)..............................................15-5
15.2.5 I2C Bus n Control Register (I2CnCON : n=0,1)......................................................15-6
15.2.6 I2C Bus n Mode Register (I2CnMOD : n=0,1) ........................................................15-8
15.2.7 I2C Bus n Status Register (I2CnSTAT : n=0,1) ....................................................15-10
15.3 Description of Operation....................................................................................................... 15-11
15.3.1 Communication Operation Mode..........................................................................15-11
15.3.1.1 Start Condition............................................................................................... 15-11
15.3.1.2 Restart Condition........................................................................................... 15-11
15.3.1.3 Slave Address Transmit Mode..................................................................... 15-11
15.3.1.4 Data Transmit Mode...................................................................................... 15-11
15.3.1.5 Data receive mode........................................................................................ 15-11
15.3.1.6 Control Register Setting Wait State.............................................................15-12
15.3.1.7 Stop Condition...............................................................................................15-12
15.3.2 Communication Operation Timing........................................................................15-13
15.3.3 Operation Waveforms...........................................................................................15-15
15.3.4 Pin Settings...........................................................................................................15-16

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Chapter 16
16.Port XT..........................................................................................................................................16-1
16.1 General Description ................................................................................................................16-1
16.1.1 Features..................................................................................................................16-1
16.1.2 Configuration...........................................................................................................16-1
16.1.3 List of Pins ..............................................................................................................16-1
16.2 Description of Registers..........................................................................................................16-2
16.2.1 List of Registers......................................................................................................16-2
16.2.2 Port XT Data Register (PXTD) ...............................................................................16-3
16.2.3 Port XT Direction Register (PXTDIR).....................................................................16-4
16.3 Description of Operation.........................................................................................................16-5
16.3.1 Input Port Function .................................................................................................16-5
16.3.2 Primary Function Other Than Input Port ................................................................16-5
Chapter 17
17. Port0 .............................................................................................................................................17-1
17.1 Overview..................................................................................................................................17-1
17.1.1 Features..................................................................................................................17-1
17.1.2 Configuration...........................................................................................................17-1
17.1.3 List of Pins ..............................................................................................................17-2
17.2 Description of Registers..........................................................................................................17-3
17.2.1 List of Registers......................................................................................................17-3
17.2.2 Port 0 Data Register (P0D).....................................................................................17-4
17.2.3 Port 0 Direction Register (P0DIR) ..........................................................................17-5
17.2.4 Port 0 Control Registers (P0CON) .........................................................................17-6
17.2.5 Port 0 Mode Registers (P0MOD)............................................................................17-8
17.3 Description of Operation.......................................................................................................17-10
17.3.1 Input/Output Port Functions..................................................................................17-10
17.3.2 Primary Function except for Input/Output Port.....................................................17-10
17.3.3 Secondary ,Tertiary and Fourthly Functions ........................................................17-10
Chapter 18
18.Port1 .............................................................................................................................................18-1
18.1 Overview..................................................................................................................................18-1
18.1.1 Features..................................................................................................................18-1
18.1.2 Configuration...........................................................................................................18-1
18.1.3 List of Pins ..............................................................................................................18-2
18.2 Description of Registers..........................................................................................................18-2
18.2.1 List of Registers......................................................................................................18-2
18.2.2 Port 1 Data Register (P1D).....................................................................................18-3
18.2.3 Port 1 Direction Register (P1DIR) ..........................................................................18-4
18.2.4 Port 1 Control Registers (P1CON).........................................................................18-5
18.3 Description of Operation.........................................................................................................18-6
18.3.1 Input/Output Port Function .....................................................................................18-6
18.3.2 Other Function........................................................................................................18-6
Chapter 19
19. Port2 .............................................................................................................................................19-1
19.1 Overview..................................................................................................................................19-1
19.1.1 Features..................................................................................................................19-1
19.1.2 Configuration...........................................................................................................19-1
19.1.3 List of Pins ..............................................................................................................19-2
19.2 Description of Registers..........................................................................................................19-3

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19.2.1 List of Registers......................................................................................................19-3
19.2.2 Port 2 Data Register (P2D).....................................................................................19-4
19.2.3 Port 2 Direction Register (P2DIR) ..........................................................................19-5
19.2.4 Port 2 Control Registers (P2CON).........................................................................19-6
19.2.5 Port 2 Mode Registers (P2MOD)............................................................................19-8
19.3 Description of Operation.......................................................................................................19-10
19.3.1 Input/Output Port Functions..................................................................................19-10
19.3.2 Primary Function except for Input/Output Port.....................................................19-10
19.3.3 Secondary, Tertiary and Fourthly Functions ........................................................19-10
Chapter 20
20.Port 3 ............................................................................................................................................20-1
20.1 General Description ................................................................................................................20-1
20.1.1 Features..................................................................................................................20-1
20.1.2 Configuration...........................................................................................................20-2
20.1.3 List of Pins ..............................................................................................................20-3
20.2 Description of Registers..........................................................................................................20-4
20.2.1 List of Registers......................................................................................................20-4
20.2.2 Port 3 Data Register (P3D).....................................................................................20-5
20.2.3 Port 3 Direction Register (P3DIR) ..........................................................................20-7
20.2.4 Port 3 Control Register (P3CON)...........................................................................20-9
20.2.5 Port 3 Mode Register (P3MOD)...........................................................................20-15
20.3 Description of Operation.......................................................................................................20-15
20.3.1 Input/Output Port Functions..................................................................................20-15
20.3.2 Primary Function Other Than Input/Output Port...................................................20-15
20.3.3 Secondary to Quartic Functions...........................................................................20-15
Chapter 21
21.Port 4 ............................................................................................................................................21-1
21.1 General Description ................................................................................................................21-1
21.1.1 Features..................................................................................................................21-1
21.1.2 Configuration...........................................................................................................21-2
21.1.3 List of Pins ..............................................................................................................21-3
21.2 Description of Registers..........................................................................................................21-4
21.2.1 List of Registers......................................................................................................21-4
21.2.2 Port 4 Data Register (P4D).....................................................................................21-5
21.2.3 Port 4 Direction Register (P4DIR) ..........................................................................21-7
21.2.4 Port 4 Control Register (P4CON)...........................................................................21-8
21.2.5 Port 4 Mode Register (P4MOD)...........................................................................21-11
21.3 Description of Operation.......................................................................................................21-14
21.3.1 Input/Output Port Functions..................................................................................21-14
21.3.2 Primary Function Other Than Input/Output Port...................................................21-14
21.3.3 Secondary to Quartic Functions...........................................................................21-14
Chapter 22
22.Port 5 ............................................................................................................................................22-1
22.1 General Description ................................................................................................................22-1
22.1.1 Features..................................................................................................................22-1
22.1.2 Configuration...........................................................................................................22-2
22.1.3 List of Pins ..............................................................................................................22-3
22.2 Description of Registers..........................................................................................................22-4
22.2.1 List of Registers......................................................................................................22-4
22.2.2 Port 5 Data Register (P5D).....................................................................................22-5
22.2.3 Port 5 Direction Register (P5DIR) ..........................................................................22-7

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22.2.4 Port 5 Control Register (P5CON)...........................................................................22-9
22.2.5 Port 5 Mode Register (P5MOD)...........................................................................22-12
22.3 Description of Operation.......................................................................................................22-15
22.3.1 Input/Output Port Functions..................................................................................22-15
22.3.2 Primary Function Other Than Input/Output Port...................................................22-15
22.3.3 Secondary to Quartic Functions...........................................................................22-15
Chapter 23
23. Melody Driver................................................................................................................................23-1
23.1 Overview..................................................................................................................................23-1
23.1.1 Features..................................................................................................................23-1
23.1.2 Configuration...........................................................................................................23-1
23.1.3 List of Pins ..............................................................................................................23-1
23.2 Description of Registers..........................................................................................................23-2
23.2.1 List of Registers......................................................................................................23-2
23.2.2 Melody 0 Control Register (MD0CON)...................................................................23-3
23.2.3 Melody 0 Tempo Code Register (MD0TMP)..........................................................23-4
23.2.4 Melody 0 Scale/Tone Length Code Register (MD0TL)..........................................23-5
23.3 Description of Operation.........................................................................................................23-7
23.3.1 Operation of Melody Output ...................................................................................23-7
23.3.2 Example of Using Melody Circuit............................................................................23-8
23.3.3 Tempo Codes .........................................................................................................23-9
23.3.4 Tone Length Codes..............................................................................................23-10
23.3.5 Scale Codes..........................................................................................................23-11
23.3.6 Operations of Buzzer Output................................................................................23-12
Chapter 24
24. RC Oscillation Type A/DConverter (RC-ADC).............................................................................24-1
24.1 General Description ................................................................................................................24-1
24.1.1 Features..................................................................................................................24-1
24.1.2 Configuration...........................................................................................................24-1
24.1.3 List of Pins ..............................................................................................................24-2
24.2 Description of Registers..........................................................................................................24-3
24.2.1 List of Registers......................................................................................................24-3
24.2.2 RC-ADC Counter A Register 0 (RADCA0).............................................................24-4
24.2.3 RC-ADC Counter A Register 1 (RADCA1).............................................................24-4
24.2.4 RC-ADC Counter B Register 0 (RADCB0).............................................................24-5
24.2.5 RC-ADC Counter B Register 1 (RADCB1).............................................................24-5
24.2.6 RC-ADC Mode Register (RADMOD)......................................................................24-6
24.2.7 RC-ADC Control Register (RADCON) ...................................................................24-8
24.3 Description of Operation.........................................................................................................24-9
24.3.1 RC Oscillator Circuits............................................................................................24-10
24.3.2 Counter A/B Reference Modes.............................................................................24-14
24.3.3 Example of Use of RC Oscillation Type A/D Converter.......................................24-17
24.3.4 Monitoring RC Oscillation.....................................................................................24-22
Chapter 25
25. Successive Approximation Type A/DConverter (SA-ADC)..........................................................25-1
25.1 General Description ................................................................................................................25-1
25.1.1 Features..................................................................................................................25-1
25.1.2 Configuration...........................................................................................................25-1
25.1.3 List of Pins ..............................................................................................................25-2
25.2 Description of Registers..........................................................................................................25-3
25.2.1 List of Registers......................................................................................................25-3

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25.2.2 SA-ADC Result Register n (SADRn) n=0 to 9, A, B...............................................25-4
25.2.3 SA-ADC Control Register 0(SADCON0)................................................................25-5
25.2.4 SA-ADC Control Register1 (SADCON1)................................................................25-7
25.2.5 SA-ADC Enable Register (SADEN)........................................................................25-8
25.2.6 SA-ADC Touch Sensor Register (SADTCH)..........................................................25-9
25.2.7 SA-ADC Trigger Register (SADTRG)...................................................................25-10
25.2.8 SA-ADC Accuracy Control Register (SADCVT)...................................................25-12
25.3 Description of Operation.......................................................................................................25-13
25.3.1 Setting of A/D Conversion Channels....................................................................25-13
25.3.2 Operation of the Successive Approximation Type A/D Converter.......................25-14
25.3.3 Capacitive Touch sensor mode operation............................................................25-15
25.3.4 Notes on Use of SA-ADC .....................................................................................25-16
Chapter 26
26. Analog Comparator.......................................................................................................................26-1
26.1 Overview..................................................................................................................................26-1
26.1.1 Features..................................................................................................................26-1
26.1.2 Configuration...........................................................................................................26-1
26.1.3 List of Pins ..............................................................................................................26-1
26.2 Description of Registers..........................................................................................................26-2
26.2.1 List of Registers......................................................................................................26-2
26.2.2 Comparator n Control Register (CMPnCON : n=0,1)..........................................26-3
26.2.3 Comparator n mode Registers (CMPnMOD : n=0,1).............................................26-4
26.3 Function description................................................................................................................26-6
26.3.1 Comparator function...............................................................................................26-6
26.3.2 Supervisor mode.........................................................................................................26-6
26.3.3 Single mode ................................................................................................................26-7
26.3.4 Singlemonitor mode....................................................................................................26-9
Chapter 27
27.Flash Memory Control..................................................................................................................27-1
27.1 General Description ................................................................................................................27-1
27.1.1 Features..................................................................................................................27-1
27.2 Description of Registers..........................................................................................................27-2
27.2.1 List of Registers......................................................................................................27-2
27.2.2 Flash Address Register (FLASHA).........................................................................27-3
27.2.3 Flash Data Register (FLASHD)..............................................................................27-4
27.2.4 Flash Control Register (FLASHCON).....................................................................27-5
27.2.5 Flash Acceptor (FLASHACP).................................................................................27-6
27.2.6 Flash Segment Register (FLASHSEG)..................................................................27-6
27.2.7 Flash Self Register (FLASHSLF)............................................................................27-7
27.2.8 Remap Address Register (REMAPADD) ...............................................................27-8
27.3 Description of Operation.........................................................................................................27-9
27.3.1Address Setting for Erase.....................................................................................27-10
27.3.2Data Flash Rewriting ............................................................................................27-11
27.3.3Program Memory Rewrite (ISP Function) ............................................................27-11
27.3.4Boot Area Remap Function by Software..............................................................27-12
27.3.5Boot Area Remap Function by Hardware.............................................................27-13
27.3.6Notes of the program after remapping .................................................................27-14
27.3.7Sample Program...................................................................................................27-15

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Chapter 28
28. Voltage Level Supervisor..............................................................................................................28-1
28.1 General Description..................................................................................................................28-1
28.1.1 Features..................................................................................................................28-1
28.1.2 Configuration...........................................................................................................28-1
28.2 Description of Registers ...........................................................................................................28-2
28.2.1 List of Registers......................................................................................................28-2
28.2.2 Voltage level supervisor control register (VLSCON)..............................................28-3
28.2.3 Voltage level supervisor mode register (VLSMOD) ...............................................28-5
28.3 Description of Operation...........................................................................................................28-7
28.3.1 Supervisor mode.....................................................................................................28-8
Chapter 29
29.LLD circuit.....................................................................................................................................29-1
29.1 General Description ................................................................................................................29-1
29.1.1 Features..................................................................................................................29-1
29.2 Description of resister.............................................................................................................29-1
29.3 Description of operation..........................................................................................................29-1
Chapter 30
30.On –Chip Debug Function............................................................................................................30-1
30.1 Overview..................................................................................................................................30-1
30.2 Method of Connecting to On-Chip Debug Emulator.............................................................30-1
30.3 Flash Memory Rewrite Function............................................................................................30-2
Appendixes
Appendix A Registers.................................................................................................................................. A1
Appendix B Package Dimensions..............................................................................................................B1
Appendix C Electrical Characteristics........................................................................................................C1
Appendix D Application Circuit Example...................................................................................................D1
Revision History
Revision History..............................................................................................................................................R1

Chapter 1
Overview

ML620Q503/Q504 User’s Manual
Chapter 1 Overview
FEUL620Q504 1–1
1. Overview
1.1 Features
This LSI family is a high-performance 16-bit CMOS microcontroller into which rich peripheral circuits, such as
synchronous serial port, UART, I2C bus interface (master), supply voltage level detect circuit, RC oscillation type A/D
converter, and successive approximation type A/D converter are incorporated around 16-bit CPU nX-U16/100.
The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe line
architecture parallel processing. The Flash ROM that is installed as program memory achieves low-voltage low-power
consumption operation (read operation) is most suitable for battery-driven applications. And, this LSI has a data
flash-memory fill area by a software which can be written in.
The on-chip debug function that is installed enables program debugging and programming.
•CPU
−16-bit RISC CPU (CPU name: nX-U16/100)
−Instruction system: 16-bit instructions
−Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations,
arithmetic shift, and so on
−Build-in On-Chip debug function
−Minimum instruction execution time
30.5 µs (@32.768 kHz system clock)
62.5ns (@16 MHz system clock)
•Built-in coprocessor for multiplication, division, and multiply-accumulate operations
−Signed or unsigned operation setting
−Multiplication: 16bit ×16bit (operation time 4 cycles)
−Division: 32bit / 16bit (operation time 8 cycles)
−Division: 32bit / 32bit (operation time 16 cycles)
−Multiply-accumulate (non-saturating): 16bit ×16bit + 32bit (operation time 4 cycles)
−Multiply-accumulate (saturating): 16bit ×16bit + 32bit (operation time 4 cycles)
•Internal memory
−Supports ISP function (re-writing the program memory area by software)
−Number of segments
Product name
Flash memory
SRAM
Program area*
Data area
ML620Q503
32KB (16K×16bit)
2KB(1K×16bit)
2KB(1K×16bit
）
ML620Q504
64KB (32K×16bit)
2KB(1K×16bit)
6KB(3K×16bit
）
*: including 1KB of unusable test area
•Interrupt controller (INTC)
−1 non-maskable interrupt sources (Internal source: 1)
−37 maskable interrupt sources (Internal sources: 29, External sources: 8)
−Software interrupt (SWI): maximum 64 sources
−External interrupts and comparator allow edge selection and sampling selection
−Priority level (4-level) can be set for each interrupt
•Time base counter (TBC)
−Low-speed time base counter ×1 channel

ML620Q503/Q504 User’s Manual
Chapter 1 Overview
FEUL620Q504 1–2
•Timers (TMR)
−8 bits ×8 channels
(Timer0-7: 16-bit ×4 configuration available by using Timer0-1 or Timer2-3, Timer4-5, Timer6-7)
−Selection of one shot timer mode is possible
−External clock can be selected as timer clock.
•Function Timers (FTM)
−16-bit ×4 channels
−Equipped with the timer/capture/PWM functions using a 16-bit counter
−Timer start/stop function by software/event trigger(external pin or other timer)
−External pin can be selected as counter clock
−Capture function (the measurement such as the pulse width is possible using external trigger input)
−Two types of PWM with the same period and different duties and complementary PWM with the dead time set can
be output.
•Watchdog timer (WDT)
−Non-maskable interrupt and reset
−Free running
−Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s when LSCLK = 32.768 kHz)
•Synchronous serial port (SSIOF/ SSIO)
−without FIFOs (SSIO) : 1 channel
−with 4-byte transmits and receives FIFOs (SSIOF) : 1 channel
−Master/slave are selectable
−LSB first/MSB first are selectable
−8-bit length/16-bit length are selectable
−Phase/Polarity of clock are selectable
−supports slave-select signal (only SSIOF)
•UART (UARTF/ UART)
−without FIFOs (UART) : 1ch
−with 4-byte transmits and receives FIFOs (UARTF) : 1ch
−Full duplex buffer system
−Communication speed: Settable within the range of 2400bps to 115200bps.
−Programmable interface (data length, parity, stop bits are selectable)
•I2C bus interface (I2C)
−Master function ×2 channel
−Fast mode (400 kbps), standard mode (100 kbps)
•General-purpose ports (PORT)
−Input port x 2, Input/output port ×36 channels
•Melody driver (MELODY)
−Tempo: 15 types
−Scale: 29 types (Melody sound frequency: 508 Hz to 10.922 kHz)
−Tone length: 63 types
−Buzzer output mode (4 output modes, 8 buzzer frequencies, 7duty levels at 4.096kHz/15 duty levels at other buzzer
frequencies)
•RC oscillation type A/D converter (RC-ADC)
−Time division ×2 channels
−24-bit counter