Rohm LAPIS Semiconductor ML620Q151B User manual

ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
User’s Manual
Rev.5
Issue Date: Oct.10, 2019
FEUL620Q150B-05

ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9BUser's Manual
FEUL620Q150B i
Notes
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Copyright 2016-2019 LAPIS Semiconductor Co., Ltd.
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http://www.lapis-semi.com/en/

ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual
FEUL620Q150B ii
Preface
This manual describes the operation of the hardware of the 16-bit microcontroller
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B.
The following manuals are also available. Read them as necessary.
nX-U16/100 Core Instruction Manual
Description on the basic architecture and the each instruction of the nX-U16/100 Core.
MACU8 Assembler Package User’s Manual
Description on the method of operating the relocatable assembler, the linker, the librarian,
and the object converter and also on the specifications of the assembler language.
CCU8 User’s Manual
Description on the method of operating the compiler.
CCU8 Programming Guide
Description on the method of programming.
CCU8 Language Reference
Description on the language specifications.
DTU8 Debugger User’s Manual
Description on the method of operating the debugger DTU8.
IDEU8 User’s Manual
Description on the integrated development environment IDEU8.
uEASE User’s Manual
Description on the on-chip debug tool uEASE.
uEASE connection Manual
Description about the connection between uEASE.
FWuEASE Flash Writer Host Program User’s Manual
Description on the Flash Writer host program FWuEASE.

ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual
FEUL620Q150B iii
Notation
Classification Notation Description
Numeric value xxh, xxH Indicates a hexadecimal number
xxb Indicates a binary number
Unit word, W 1 word = 16 bits
byte, B 1 byte = 8 bits
nibble, N 1 nibble = 4 bits
mega-, M 106
kilo-, K 210 = 1024
kilo-, k 103= 1000
milli-, m 10-3
micro-, µ 10-6
nano-, n 10-9
second, s (lower case) second
Terminology “H” leve Indicates high voltage signal levels VIH and VOH as specified by the electrical
characteristics.
“L” level Indicates low voltage signal levels VIL and VOL as specified by the electrical
characteristics.
Register description
R/W: Indicates that Read/Write attribute. “R” indicates that data can be read and “W” indicates that data can be written.
“R/W”indicates that data can be read or written. If a bit symbol name exists, one bit read/write operation is available.
MSB: The highest bit of 8-bit register
LSB: The lowest bit of 8-bit register
MSB
LSB
FCON0


OUTC1
OUTC0
OSCM1
OSCM0
SYSC1
SYSC0
R/W


R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
1
1
1
0
1
1
Bit name
Register name
Initial value after reset
Invalid bit: Read value is always “0”. Write is invalid.

ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9BUser's Manual
Contents
FEUL620Q150B Contents-1
Contents
Chapter 1
1. Overview .........................................................................................................................................................1-1
1.1 Features .......................................................................................................................................................1-1
1.2 Configuration of Functional Blocks.............................................................................................................1-4
1.2.1 Block Diagram.......................................................................................................................................1-4
1.3 Pins..............................................................................................................................................................1-7
1.3.1 Pin Layout..............................................................................................................................................1-7
1.3.1.1 Pin Layout of package......................................................................................................................1-7
1.3.2 List of Pins...........................................................................................................................................1-10
1.3.3 Pin Description ....................................................................................................................................1-14
1.3.4 Handling of Unused Pins .....................................................................................................................1-17
Chapter 2
2 CPU and Memory Space .................................................................................................................................2-1
2.1 Genral Description.......................................................................................................................................2-1
2.2 Program Memory Space ..............................................................................................................................2-1
2.3 Data Memory Space ....................................................................................................................................2-4
2.4 Instruction Length........................................................................................................................................2-7
2.5 Data Type....................................................................................................................................................2-7
2.6 Description of Registers ..............................................................................................................................2-7
2.6.1 List of Registers.....................................................................................................................................2-7
2.6.2 Data Segment Register (DSR) ...............................................................................................................2-7
Chapter 3
3. Reset Function.................................................................................................................................................3-1
3.1 General Description.....................................................................................................................................3-1
3.1.1 Features..................................................................................................................................................3-1
3.1.2 Configuration.........................................................................................................................................3-1
3.1.3 List of Pin ..............................................................................................................................................3-1
3.2 Description of Registers ..............................................................................................................................3-2
3.2.1 List of Registers.....................................................................................................................................3-2
3.2.2 Reset Status Register (RSTAT) .............................................................................................................3-2
3.3 Description of Operation.............................................................................................................................3-4
3.3.1 Operation of System Reset Mode ..........................................................................................................3-4
Chapter 4
4. MCU Control Function....................................................................................................................................4-1
4.1 General Description.....................................................................................................................................4-1
4.1.1 Features..................................................................................................................................................4-1
4.1.2 Configuration.........................................................................................................................................4-1
4.2 Description of Registers ..............................................................................................................................4-2
4.2.1 List of Registers.....................................................................................................................................4-2
4.2.2 Stop Code Acceptor (STPACP).............................................................................................................4-3
4.2.3 Standby Control Register (SBYCON) ...................................................................................................4-4
4.2.4 Block Control Register 0 (BLKCON0) .................................................................................................4-5
4.2.5 Block Control Register 2 (BLKCON2) .................................................................................................4-6
4.2.6 Block Control Register 3 (BLKCON3) .................................................................................................4-7
4.2.7 Block Control Register 4 (BLKCON4) .................................................................................................4-8
4.2.8 Block Control Register 6 (BLKCON6) .................................................................................................4-9
4.2.9 Block Control Register 7 (BLKCON7) ...............................................................................................4-10
4.3 Description of Operation...........................................................................................................................4-11
4.3.1 Program Operating Mode ....................................................................................................................4-11
4.3.2 HALT Mode ........................................................................................................................................4-11
4.3.3 STOP Mode.........................................................................................................................................4-12

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4.3.3.1 Stop mode when the CPU runs with low-speed clock....................................................................4-12
4.3.3.2 Stop mode when the CPU runs with high-speed clock...................................................................4-16
4.3.3.3 Note on Return Operation from STOP/HALT Mode.....................................................................4-20
4.3.4 Block control Function ........................................................................................................................4-21
Chapter 5
5. Interrupts (INTs)..............................................................................................................................................5-1
5.1 Genral Description.......................................................................................................................................5-1
5.1.1 Features................................................................................................................................................5-1
5.2 Description of Registers ..............................................................................................................................5-2
5.2.1 List of Registers...................................................................................................................................5-2
5.2.2 Interrupt Enable Register 0 (IE0)...........................................................................................................5-3
5.2.3 Interrupt Enable Register 1 (IE1)...........................................................................................................5-4
5.2.4 Interrupt Enable Register 2 (IE2)...........................................................................................................5-6
5.2.5 Interrupt Enable Register 3 (IE3)...........................................................................................................5-7
5.2.6 Interrupt Enable Register 4 (IE4)...........................................................................................................5-8
5.2.7 Interrupt Enable Register 5 (IE5)...........................................................................................................5-9
5.2.8 Interrupt Enable Register 6 (IE6).........................................................................................................5-10
5.2.9 Interrupt Enable Register 7 (IE7).........................................................................................................5-12
5.2.10 Interrupt Request Register 0 (IRQ0)....................................................................................................5-13
5.2.11 Interrupt Request Register 1 (IRQ1)....................................................................................................5-14
5.2.12 Interrupt Request Register 2 (IRQ2)....................................................................................................5-16
5.2.13 Interrupt Request Register 3 (IRQ3)....................................................................................................5-17
5.2.14 Interrupt Request Register 4 (IRQ4)....................................................................................................5-19
5.2.15 Interrupt Request Register 5 (IRQ5)....................................................................................................5-20
5.2.16 Interrupt Request Register 6 (IRQ6)....................................................................................................5-21
5.2.17 Interrupt Request Register 7 (IRQ7)....................................................................................................5-23
5.2.18 Interrupt Level Control Enable Register (ILENL)...............................................................................5-24
5.2.19 Current Interrupt Request Level Register (CILL)................................................................................5-25
5.2.20 Interrupt Level Control Register 01 (ILC01).......................................................................................5-26
5.2.21 Interrupt Level Control Register 10 (ILC10).......................................................................................5-27
5.2.22 Interrupt Level Control Register 11 (ILC11).......................................................................................5-28
5.2.23 Interrupt Level Control Register 20 (ILC20).......................................................................................5-29
5.2.24 Interrupt Level Control Register 21 (ILC21).......................................................................................5-30
5.2.25 Interrupt Level Control Register 30 (ILC30).......................................................................................5-31
5.2.26 Interrupt Level Control Register 31 (ILC31).......................................................................................5-32
5.2.27 Interrupt Level Control Register 40 (ILC40).......................................................................................5-33
5.2.28 Interrupt Level Control Register 51 (ILC51).......................................................................................5-34
5.2.29 Interrupt Level Control Register 60 (ILC60).......................................................................................5-35
5.2.30 Interrupt Level Control Register 61 (ILC61).......................................................................................5-36
5.2.31 Interrupt Level Control Register 70 (ILC70).......................................................................................5-37
5.3 Description of Operation...........................................................................................................................5-38
5.3.1 Maskable Interrupt Processing.............................................................................................................5-40
5.3.2 Non-Maskable Interrupt Processing.....................................................................................................5-40
5.3.3 Software Interrupt Processing..............................................................................................................5-40
5.3.4 Notes on Interrupt Routine (When Interrupt Level Control Disabled) ................................................5-41
5.3.5 Flow Chart When Interrupt Level Control Enabled.............................................................................5-44
5.3.6 How To Write Interrupt Processing When Interrupt Level Control Enabled.......................................5-45
5.3.6.1 Writing Interrupt function to disable multiple interrupts ..................................................................5-45
5.3.6.2 Writing Interrupt function to enable multiple interrupts ...................................................................5-47
5.3.7 Interrupt Disable State .........................................................................................................................5-48
Chapter 6
6. Clock Generation Circuit.................................................................................................................................6-1
6.1 Genral Description.......................................................................................................................................6-1
6.1.1 Features..................................................................................................................................................6-1
6.1.2 Configuration.........................................................................................................................................6-2
6.1.3 List of Pins.............................................................................................................................................6-3
6.1.4 Clock Configuration Diagram................................................................................................................6-3
6.2 Description of Registers ..............................................................................................................................6-4

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FEUL620Q150B Contents-3
6.2.1 List of Registers.....................................................................................................................................6-4
6.2.2 Frequency Control Register 0(FCON0).................................................................................................6-5
6.2.3 Frequency Control Register 1 (FCON1)................................................................................................6-6
6.2.4 Frequency Control Register 3 (FCON3)................................................................................................6-7
6.2.5 Frequency Status Register (FSTAT)......................................................................................................6-9
6.3 Description of Operation...........................................................................................................................6-10
6.3.1 Low-Speed Clock.................................................................................................................................6-10
6.3.1.1 Low-Speed Crystal Oscillation Circuit...........................................................................................6-10
6.3.1.2 Low-Speed Built-In RC Oscillation Circuit ...................................................................................6-10
6.3.1.3 Operation of Low-Speed Clock Generation Circuit .......................................................................6-11
6.3.2 High-Speed Clock................................................................................................................................6-14
6.3.2.1 High-Speed Built-in RC Oscillation Circuit...................................................................................6-14
6.3.2.2 PLL Oscillation Circuit ..................................................................................................................6-14
6.3.2.3 Operation of High-Speed Clock.....................................................................................................6-15
6.3.3 Switching of System Clock..................................................................................................................6-17
6.4 Specifying Port Registers ..........................................................................................................................6-18
6.4.1 Functioning P21(OUTCLK) as the high-speed clock output...............................................................6-18
6.4.2 Functioning P20 (LSCLK) as the low-speed clock output...................................................................6-19
6.4.3 Functioning P36 (LSCLK) as the low-speed clock output...................................................................6-20
Chapter 7
7. Time Base Counter..........................................................................................................................................7-1
7.1 Genral Description.......................................................................................................................................7-1
7.1.1 Features..................................................................................................................................................7-1
7.1.2 Configuration.........................................................................................................................................7-1
7.2 Description of Registers ..............................................................................................................................7-2
7.2.1 List of Registers.....................................................................................................................................7-2
7.2.2 Low-Speed Time Base Counter (LTBR) ...............................................................................................7-3
7.2.3 Low-Speed Time Base Counter Frequency Adjustment Registers (LTBADJL, LTBADJH)................7-4
7.2.4 Low-Speed Time Base Counter Interrupt select Registers (LTBINT0, LTBINT1) .............................7-6
7.3 Description of Operation.............................................................................................................................7-7
7.3.1 Low-Speed Time Base Counter .............................................................................................................7-7
Chapter 8
8. 8bit Timer........................................................................................................................................................8-1
8.1 Genral Description.......................................................................................................................................8-1
8.1.1 Features..................................................................................................................................................8-1
8.1.2 Configuration.........................................................................................................................................8-1
8.2 Description of Registers ..............................................................................................................................8-2
8.2.1 List of Registers.....................................................................................................................................8-2
8.2.2 Timer 0 Data Register (TM0D) .............................................................................................................8-3
8.2.3 Timer 1 Data Register (TM1D) .............................................................................................................8-4
8.2.4 Timer 0 Counter Register (TM0C) ........................................................................................................8-5
8.2.5 Timer 1 Counter Register (TM1C) ........................................................................................................8-6
8.2.6 Timer 0 Control Register (TM0CON) ...................................................................................................8-7
8.2.7 Timer 1 Control Register (TM1CON) ...................................................................................................8-9
8.2.8 Timer Start Register 0 (TMSTR0).......................................................................................................8-10
8.2.9 Timer Stop Register 0 (TMSTP0) .......................................................................................................8-11
8.2.10 Timer Status Register 0 (TMSTAT0)..................................................................................................8-12
8.3 Description of Operation...........................................................................................................................8-13
Chapter 9
9. 16bit Timer......................................................................................................................................................9-1
9.1 Genral Description.......................................................................................................................................9-1
9.1.1 Features..................................................................................................................................................9-1
9.1.2 Configuration.........................................................................................................................................9-1
9.2 Description of Registers ..............................................................................................................................9-2
9.2.1 List of Registers.....................................................................................................................................9-2
9.2.2 16bit timer 8 data register L,H (TMH8DL,H) .......................................................................................9-3

ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual
Contents
FEUL620Q150B Contents-4
9.2.3 16bit timer 9 data register L,H (TMH9DL,H) .......................................................................................9-4
9.2.4 16bit timer A data register L,H (TMHADL,H)......................................................................................9-5
9.2.5 16bit timer B data register L,H (TMHBDL,H)......................................................................................9-6
9.2.6 16bit timer 8 counter register L,H (TMH8CL,H) ..................................................................................9-7
9.2.7 16bit timer 9 counter register L,H (TMH9CL,H) ..................................................................................9-8
9.2.8 16bit timer A counter register L,H (TMHACL,H).................................................................................9-9
9.2.9 16bit timer B counter register L,H (TMHBCL,H)...............................................................................9-10
9.2.10 16bit timer 8 control register L,H (TMH8CON) .................................................................................9-11
9.2.11 16bit timer 9 control register L,H (TMH9CON) .................................................................................9-12
9.2.12 16bit timer A control register L,H (TMHACON)................................................................................9-13
9.2.13 16bit timer B control register L,H (TMHBCON)................................................................................9-14
9.2.14 16bit timer start register 0 (TMHSTR0)..............................................................................................9-15
9.2.15 16bit timer stop register 0 (TMHSTP0)...............................................................................................9-16
9.2.16 16bit timer status register 0 (TMHSTAT0) .........................................................................................9-17
9.3 Description of Operation...........................................................................................................................9-18
Chapter 10
10. Watchdog Timer............................................................................................................................................10-1
10.1 General Description...................................................................................................................................10-1
10.1.1 Features................................................................................................................................................10-1
10.1.2 Configuration.......................................................................................................................................10-1
10.2 Description of Registers ............................................................................................................................10-2
10.2.1 List of Registers...................................................................................................................................10-2
10.2.2 Watchdog Timer Control Register (WDTCON)..................................................................................10-3
10.2.3 Watchdog Timer Mode Register (WDTMOD)....................................................................................10-4
10.3 Description of Operation ...........................................................................................................................10-5
10.3.1 Handling example when you do not want to use the watch dog timer .................................................10-7
Chapter 11
11. PWM .............................................................................................................................................................11-1
11.1 General Description...................................................................................................................................11-1
11.1.1 Features................................................................................................................................................11-1
11.1.2 Configuration.......................................................................................................................................11-2
11.1.3 List of Pins...........................................................................................................................................11-6
11.2 Description of Registers ............................................................................................................................11-7
11.2.1 List of Registers...................................................................................................................................11-7
11.2.2 PWM4 period register L, H (PW4PL, PW4PH)..................................................................................11-9
11.2.3 PWM4 duty register L, H (PW4DL, PW4DH)..................................................................................11-10
11.2.4 PWM4 counter register L, H (PW4CL, PW4CH) .............................................................................11-11
11.2.5 PWM4 control register 0 (PW4CON0) .............................................................................................11-12
11.2.6 PWM4 control register 1 (PW4CON1) .............................................................................................11-14
11.2.7 PWM4 control register 2 (PW4CON2) .............................................................................................11-15
11.2.8 PWM4 control register 3 (PW4CON3) .............................................................................................11-17
11.2.9 PWM4 control register 4 (PW4CON4) .............................................................................................11-18
11.2.10 PWM4 control register 5 (PW4CON5) .............................................................................................11-19
11.2.11 PWM4 control register 6 (PW4CON6) .............................................................................................11-20
11.2.12 PWM5 period register L, H (PW5PL, PW5PH)................................................................................11-21
11.2.13 PWM5 duty register L, H (PW5DL, PW5DH)..................................................................................11-22
11.2.14 PWM5 counter register L, H (PW5CL, PW5CH)..............................................................................11-23
11.2.15 PWM5 control register 0 (PW5CON0)..............................................................................................11-24
11.2.16 PWM5 control register 1 (PW5CON1)..............................................................................................11-26
11.2.17 PWM5 control register 2 (PW5CON2)..............................................................................................11-27
11.2.18 PWM5 control register 4 (PW5CON4) .............................................................................................11-29
11.2.19 PWM5 control register 5 (PW5CON5) .............................................................................................11-30
11.2.20 PWM5 control register 6 (PW5CON6) .............................................................................................11-31
11.2.21 PWM6 period register L, H (PW6PL, PW6PH)................................................................................11-32
11.2.22 PWM6 duty register L, H (PW6DL, PW6DH)..................................................................................11-33
11.2.23 PWM6 counter register L, H (PW6CL, PW6CH)..............................................................................11-34
11.2.24 PWM6 control register 0 (PW6CON0)..............................................................................................11-35
11.2.25 PWM6 control register 1 (PW6CON1)..............................................................................................11-37

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11.2.26 PWM6 control register 2 (PW6CON2)..............................................................................................11-38
11.2.27 PWM6 control register 3 (PW6CON3) .............................................................................................11-40
11.2.28 PWM6 control register 4 (PW6CON4) .............................................................................................11-41
11.2.29 PWM6 control register 5 (PW6CON5) .............................................................................................11-42
11.2.30 PWM6 control register 6 (PW6CON6) .............................................................................................11-43
11.2.31 PWM7 period register L, H (PW7PL, PW7PH)................................................................................11-44
11.2.32 PWM7 duty register L, H (PW7DL, PW7DH)..................................................................................11-45
11.2.33 PWM7 counter register L, H (PW7CL, PW7CH)..............................................................................11-46
11.2.34 PWM7 control register 0 (PW7CON0)..............................................................................................11-47
11.2.35 PWM7 control register 1 (PW7CON1)..............................................................................................11-49
11.2.36 PWM7 control register 2 (PW7CON2)..............................................................................................11-50
11.2.37 PWM7 control register 4 (PW7CON4) .............................................................................................11-52
11.2.38 PWM7 control register 5 (PW7CON5) .............................................................................................11-53
11.2.39 PWM7 control register 6 (PW7CON6) .............................................................................................11-54
11.3 Description of Operation .........................................................................................................................11-55
11.3.1 PWM Single mode / Continuous mode..............................................................................................11-57
11.3.2 PWM Single mode / One shot mode..................................................................................................11-59
11.3.3 PWM Coupled mode / Continuous mode ..........................................................................................11-61
11.3.3.1 with no dead-time specified ..........................................................................................................11-61
11.3.3.2 with dead-time specified ...............................................................................................................11-63
11.3.4 PWM Coupled mode / One shot mode ..............................................................................................11-65
11.3.4.1 with no dead-time specified ..........................................................................................................11-65
11.3.4.2 with dead-time specified ...............................................................................................................11-67
11.3.5 PWM Control by the software ...........................................................................................................11-69
11.3.5.1 start/stop/clear operation ...............................................................................................................11-69
11.3.5.2 period and duty update ..................................................................................................................11-69
11.3.6 PWM Control by the external input...................................................................................................11-70
11.3.6.1 start/stop/clear operation ...............................................................................................................11-70
11.3.6.2 period and duty update ..................................................................................................................11-71
11.3.7 PWM Control Mode ..........................................................................................................................11-72
11.3.7.1 Software Start Mode......................................................................................................................11-72
11.3.7.2 Software Start Mode or External Start Mode ................................................................................11-72
11.3.7.3 External Input Start Mode .............................................................................................................11-74
11.3.7.4 Software Start or External Input Clear Mode ................................................................................11-76
11.3.8 PWM Emergency Stop Operation......................................................................................................11-79
11.4 Specifying Port Registers ........................................................................................................................11-81
11.4.1 Functioning P34 Pin (PWM4) as PWM Output.................................................................................11-81
11.4.2 Functioning P43 Pin (PWM4) as PWM Output.................................................................................11-82
11.4.3 Functioning P35 Pin (PWM5) as PWM Output.................................................................................11-83
11.4.4 Functioning P47 Pin (PWM5) as PWM Output.................................................................................11-84
Chapter 12
12. Synchronous Serial Port (SSIO)....................................................................................................................12-1
12.1 Genral Description.....................................................................................................................................12-1
12.1.1 Features................................................................................................................................................12-1
12.1.2 Configuration.......................................................................................................................................12-1
12.1.3 List of Pins...........................................................................................................................................12-2
12.2 Description of Registers ............................................................................................................................12-3
12.2.1 List of Registers...................................................................................................................................12-3
12.2.2 Serial Port Transmit/Receive Buffers (SIO0BUFL, SIO0BUFH) .......................................................12-4
12.2.3 Serial Port Control Register (SIO0CON).............................................................................................12-5
12.2.4 Serial Port Mode Register 0 (SIO0MOD0) .........................................................................................12-6
12.2.5 Serial Port Mode Register 1 (SIO0MOD1) .........................................................................................12-7
12.3 Description of Operation...........................................................................................................................12-8
12.3.1 Transmit Operation..............................................................................................................................12-8
12.3.2 Receive Operation................................................................................................................................12-9
12.3.3 Transmit/Receive Operation..............................................................................................................12-10
12.4 Specifying port registers..........................................................................................................................12-11
12.4.1 Functioning P42 (SOUT0: Output), P41 (SCK0: Input/output), and P40 (SIN0: Input)
as the SSIO/ “Master mode” ..............................................................................................................12-11

ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual
Contents
FEUL620Q150B Contents-6
12.4.2 Functioning P42 (SOUT0: Output), P41 (SCK0: Input/output), and P40 (SIN0: Input)
as the SSIO/ ”Slave mode” ................................................................................................................12-12
Chapter 13
13. UART............................................................................................................................................................13-1
13.1 Genral Description.....................................................................................................................................13-1
13.1.1 Features................................................................................................................................................13-1
13.1.2 Configuration.......................................................................................................................................13-1
13.1.3 List of Pins...........................................................................................................................................13-2
13.2 Description of Registers ............................................................................................................................13-2
13.2.1 List of Registers...................................................................................................................................13-2
13.2.2 UART0 Transmit/Receive Buffer (UA0BUF).....................................................................................13-3
13.2.3 UART1 Transmit/Receive Buffer (UA1BUF).....................................................................................13-4
13.2.4 UART0 Control Register (UA0CON) .................................................................................................13-5
13.2.5 UART1 Control Register (UA1CON) .................................................................................................13-6
13.2.6 UART0 Mode Register 0 (UA0MOD0) ..............................................................................................13-7
13.2.7 UART1 Mode Register 0 (UA1MOD0) ..............................................................................................13-9
13.2.8 UART0 Mode Register 1 (UA0MOD1) ............................................................................................13-10
13.2.9 UART1 Mode Register 1 (UA1MOD1) ............................................................................................13-12
13.2.10 UART0 Baud Rate Registers L, H (UA0BRTL, UA0BRTH)...........................................................13-14
13.2.11 UART1 Baud Rate Registers L, H (UA1BRTL, UA1BRTH)...........................................................13-15
13.2.12 UART0 Status Register (UA0STAT) ................................................................................................13-16
13.2.13 UART1 Status Register (UA1STAT) ................................................................................................13-18
13.3 Description of Operation .........................................................................................................................13-20
13.3.1 Transfer Data Format.........................................................................................................................13-20
13.3.2 Baud Rate ..........................................................................................................................................13-21
13.3.3 Transmitted Data Direction................................................................................................................13-22
13.3.4 Transmit Operation (Full-Duplex Communication Mode).................................................................13-23
13.3.5 Transmit Operation (Half -Duplex Communication Mode)...............................................................13-24
13.3.6 Receive Operation (Full-Duplex/Half-Duplex Communication Mode).............................................13-25
13.3.6.1 Detection of Start bit ....................................................................................................................13-27
13.3.6.2 Sampling Timing..........................................................................................................................13-27
13.3.6.3 Reception Margin.........................................................................................................................13-28
13.4 Specifying Port Registers ........................................................................................................................13-29
13.4.1 Functioning P53 (TXD1: Output) and P54 pins (RXD0: Input) as the UART (Full-duplex)..............13-29
13.4.2 Functioning P43 (TXD1: Output) and P02 pins (RXD0: Input) as the UART (Full-duplex)..............13-30
13.4.3 Functioning P85 (TXD1: Output) and P86 pins (RXD0: Input) as the UART (Full-duplex)..............13-32
13.4.4 Functioning P53 (TXD1: Output) and P03 pins (RXD1: Input) as the UART (Half-duplex) .............13-33
13.4.5 Functioning P55 (TXD0: Output) and P42 pins (RXD0: Input) as the UART (Half-duplex) .............13-35
13.4.6 Functioning P43 (TXD0: Output) and P54 pins (RXD0: Input) as the UART (Half-duplex) .............13-37
13.4.7 Functioning P85 (TXD1: Output) and P72 pins (RXD1: Input) as the UART (Half-duplex) .............13-39
Chapter 14
14. I2C Bus Interface ...........................................................................................................................................14-1
14.1 Genral Description.....................................................................................................................................14-1
14.1.1 Features................................................................................................................................................14-1
14.1.2 Configuration.......................................................................................................................................14-1
14.1.3 List of Pins...........................................................................................................................................14-2
14.2 Description of Registers ............................................................................................................................14-3
14.2.1 List of Registers...................................................................................................................................14-3
14.2.2 I2C Bus 0 Receive Register (I2C0RD).................................................................................................14-4
14.2.3 I2C Bus 0 Slave Address Register (I2C0SA) .......................................................................................14-5
14.2.4 I2C Bus 0 Transmit Data Register (I2C0TD).......................................................................................14-6
14.2.5 I2C Bus 0 Control Register 0 (I2C0CON0)..........................................................................................14-7
14.2.6 I2C Bus 0 Mode Register L (I2C0MODL)...........................................................................................14-8
14.2.7 I2C Bus 0 Mode Register H (I2C0MODH)..........................................................................................14-9
14.2.8 I2C Bus 0 Status Register (I2C0STAT) .............................................................................................14-10
14.3 Description of Operation .........................................................................................................................14-11
14.3.1 Communication Operating Mode.......................................................................................................14-11
14.3.1.1 Start Condition .............................................................................................................................14-11