NXP Semiconductors LPC21 Series User manual

UM10114
LPC21xx and LPC22xx User manual
Rev. 03 — 2 April 2008 User manual
Document information
Info Content
Keywords LPC2109/00, LPC2109/01, LPC2119, LPC2119/01, LPC2129,
LPC2129/01, LPC2114, LPC2114/01, LPC2124, LPC2124/01, LPC2194,
LPC2194/01, LPC2210, LPC2220, LPC2210/01, LPC2212, LPC2212/01,
LPC2214, LPC2214/01, LPC2290, LPC2290/01, LPC2292, LPC2292/01,
LPC2294, LPC2294/01, ARM, ARM7, 32-bit, Microcontroller
Abstract User manual for LPC2109/19/29/14/24/94 and
LPC2210/20/12/14/90/92/94 including /01 parts

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Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
NXP Semiconductors UM10114
LPC21xx and LPC22xx
Revision history
Rev Date Description
3.0 20080402 •Flash chapter updated with correct boot process flowchart.
•The Reinvoke ISP command has been removed from the ISP command description
because it is not implemented in the LPC21xx/LPC22xx.
•Description of CRP levels has been corrected, and CRP description for different
bootloader code versions has been added.
•Numbering of CAN controllers in the global CAN filter look-up table has been corrected
for /01 devices.
•Part ID’s have been updated for LPC2210/20 parts.
2.0 20080104 Integrated related parts into this manual and made numerous editorial and content updates
throughout the document:
•The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Parts LPC2109, LPC2119, LPC2129, LPC2114, LPC2124, LPC2194, LPC2212,
LPC2214, LPC2290, LPC2292, LPC2294 and /01 parts added.
•PWM mode description updated.
•Fractional baud rate generator updated.
•CTCR register updated.
•ADC pin description updated.
•SPI clock conditions updated.
•JTAG pin description updated.
•Startup sequence diagram added.
•SPI master mode: SPI SSEL line conditioning for LPC2210/20 added in SPI pin
description table.
1.0 20051012 Moved the UM document into the new structured FrameMaker template. Many changes
were made to the format throughout the document. Here are the most important:
•UART0 and UART1 description updated (fractional baudrate generator and hardware
handshake features added - auto-CTS/RTS)
•ADC chapter updated with the dedicated result registers
•GPIO chapter updated with the description of the Fast IOs

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1. Introduction
The LPC21xx and LPC22xx are based on a 16/32 bit ARM7TDMI-STM CPU with real-time
emulation and embedded trace support, together with 64/128/256 kilobytes (kB) of
embedded high speed flash memory. A 128-bit wide internal memory interface and a
unique accelerator architecture enable 32-bit code execution at maximum clock rate. For
critical code size applications, the alternative 16-bit Thumb Mode reduces code by more
than 30% with minimal performance penalty.
With their compact 64 and 144 pin packages, low power consumption, various 32-bit
timers, up to 12external interrupt pins, and four channel 10-bit ADC and 46 GPIOs (64 pin
packages), or 8-channel 10-bit ADC and 112 GPIOs (144 pin package), these
microcontrollers are particularly targeted for industrial control, medical systems, access
control, and point-of-sale. With a wide range of serial communications interfaces, they are
also very well suited for communication gateways, protocol converters, and embedded soft
modems as well as many other general-purpose applications.
2. How to read this manual
The LPC21xx and LPC22xx user manual covers the following parts and versions:
•LPC2109, LPC2119, LPC2129, /00 and /01 versions
•LPC2114, LPC2124, /00 and /01 versions
•LPC2194 and LPC2194/01
•LPC2210, LPC2210/01, and LPC2220
•LPC2212, LPC2214, /00 and /01 versions
•LPC2290 and LPC2290/01
•LPC2292, LPC2294, /00 and /01 versions
All parts exist in legacy versions and enhanced versions. Enhanced parts are equipped
with enhanced GPIO, SSP, ADC, UART, and timer peripherals. They are also backward
compatible to the “legacy” parts containing legacy versions of the same peripherals.
Therefore, enhanced parts contain all features of legacy parts as well. See Table 1–16 for
an overview.
To denote different versions the following suffixes are used (see Section 1–4 “Ordering
options”); no suffix, /00, /01, and /G. All /01 versions and the LPC2220 (no suffix) contain
enhanced features.
UM10114
Chapter 1: Introductory information
Rev. 03 — 2 April 2008 User manual

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NXP Semiconductors UM10114
Chapter 1: Introductory information
This user manual describes enhanced features together with legacy features for all
LPC21xx and LPC22xx parts. Part specific and legacy/enhanced specific pinning,
registers, and configurations are listed in a table at the beginning of each chapter (see for
example Table 6–52 “LPC21xx/22xx part-specific register bits”). Use this table to
determine which parts of the user manual apply.
3. Features
3.1 Legacy features common to all LPC21xx and LPC22xx parts
•16-bit/32-bit ARM7TDMI-S microcontroller in a 64 or 144 pin package.
•8/16/64 kB of on-chip static RAM and 64/128/256 kB of on-chip flash program
memory (except for flashless LPC2210/20/90). 128-bit wide interface/accelerator
enables high-speed 60 MHz operation.
•Diversified Code Read Protection (CRP) enables different security levels to be
implemented.
In-System/In-Application Programming (ISP/IAP) via on-chip boot loader software.
Single flash sector or full chip erase in 100 ms and programming of 256 bytes in 1 ms.
•External 8, 16, or 32-bit bus (144 pin package).
•EmbeddedICE RT and Embedded Trace offer real-time debugging with the on-chip
RealMonitor software and high speed tracing of instruction execution.
•Up to four interconnected CAN interfaces with advanced acceptance filters.
•10-bit A/D converter providing four/eight analog inputs with conversion times as low
as 2.44 ms per channel and dedicated result registers to minimize interrupt overhead.
•Two 32-bit timers/external event counters with four capture and four compare
channels each, PWM unit (6 outputs), Real Time Clock (RTC), and watchdog.
•Multiple serial interfaces including two UARTs (16C550), a fast I2C-bus (400 kbit/s),
and two SPI interfaces.
•Vectored interrupt controller with configurable priorities and vector addresses.
•Up to forty-eight 5 V tolerant fast general purpose I/O pins.
Table 1. LPC21xx and LPC22xx legacy/enhanced parts overview
Legacy parts Enhanced parts
LPC2109/00
LPC2119, LPC2119/00
LPC2129, LPC2129/00
LPC2109/01
LPC2119/01
LPC2129/01
LPC2114, LPC2114/00
LPC2124, LPC2124/00 LPC2114/01 LPC2124/01
LPC2194, LPC2194/00 LPC2194/01
LPC2210 LPC2210/01
LPC2220, LPC2220/G
LPC2212, LPC2212/00
LPC2214, LPC2214/00 LPC2212/01 LPC2214/01
LPC2290 LPC2290/01
LPC2292, LPC2292/00
LPC2294, LPC2294/00 LPC2292/01 LPC2294/01

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Chapter 1: Introductory information
•Up to 12 edge or level sensitive external interrupt pins available.
•60 MHz maximum CPU clock available from programmable on-chip PLL with a
possible input frequency of 10 MHz to 25 MHz and a settling time of 100 ms.
•For flashless LPC2210/20/90 only: 60 MHz (LPC2210/90), 72 MHz (LPC2290/01), or
75 MHz (LPC2210/01 and LPC2220) maximum CPU clock available from
programmable on-chip Phase-Locked Loop (PLL) with settling time of 100 μs.
•On-chip integrated oscillator operates with an external crystal in the range from
1 MHz to 25 MHz and with an external oscillator up to 50 MHz.
•Two power saving modes, Idle mode and Power-down mode.
•Peripheral clock scaling and individual enable/disable of peripheral functions for
additional power optimization.
•Processor wake-up from Power-down mode via external interrupt or CAN controllers.
•Dual power supply:
–CPU operating voltage range of 1.65 V to 1.95 V (1.8 V ± 8.3 %).
–I/O power supply range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O pads.
3.2 Enhanced features
•Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original
device. They also allow for a port pin to be read at any time regardless of its function.
•Dedicated result registers for ADC reduce interrupt overhead. The ADC pads are 5 V
tolerant when configured for digital I/O function(s).
•UART0/1 include fractional baud rate generator, auto-bauding capabilities, and
handshake flow-control fully implemented in hardware.
•Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.
•SPI programmable data length and master mode enhancement.
•General purpose timers can operate as external event counters.
4. Ordering options
4.1 LPC2109/2119/2129
Table 2. LPC2109/2119/2129 Ordering information
Type number Package
Name Description Version
LPC2109FBD64/00 LQFP64 plastic low profile quad flat package; 64 leads;
body 10 ×10 ×1.4 mm SOT314-2
LPC2109FBD64/01 LQFP64 plastic low profile quad flat package; 64 leads;
body 10 ×10 ×1.4 mm SOT314-2
LPC2119FBD64 LQFP64 plastic low profile quad flat package; 64 leads;
body 10 ×10 ×1.4 mm SOT314-2
LPC2119FBD64/00 LQFP64 plastic low profile quad flat package; 64 leads;
body 10 ×10 ×1.4 mm SOT314-2
LPC2119FBD64/01 LQFP64 plastic low profile quad flat package; 64 leads;
body 10 ×10 ×1.4 mm SOT314-2

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Chapter 1: Introductory information
4.2 LPC2114/2124
LPC2129FBD64 LQFP64 plastic low profile quad flat package; 64 leads;
body 10 ×10 ×1.4 mm SOT314-2
LPC2129FBD64/00 LQFP64 plastic low profile quad flat package; 64 leads;
body 10 ×10 ×1.4 mm SOT314-2
LPC2129FBD64/01 LQFP64 plastic low profile quad flat package; 64 leads;
body 10 ×10 ×1.4 mm SOT314-2
Table 3. LPC2109/2119/2129 Ordering options
Type number Flash
memory RAM CAN Fast GPIO/ SSP/
Enhanced
UART, ADC,
Timer
Temperature range
LPC2109FBD64/00 64 kB 8 kB 1 channel no −40 °C to +85 °C
LPC2109FBD64/01 64 kB 8 kB 1 channel yes −40 °C to +85 °C
LPC2119FBD64 128 kB 16 kB 2 channels no −40 °C to +85 °C
LPC2119FBD64/00 128 kB 16 kB 2 channels no −40 °C to +85 °C
LPC2119FBD64/01 128 kB 16 kB 2 channels yes −40 °C to +85 °C
LPC2129FBD64 256 kB 16 kB 2 channels no −40 °C to +85 °C
LPC2129FBD64/00 256 kB 16 kB 2 channels no −40 °C to +85 °C
LPC2129FBD64/01 256 kB 16 kB 2 channels yes −40 °C to +85 °C
Table 2. LPC2109/2119/2129 Ordering information …continued
Type number Package
Name Description Version
Table 4. LPC 2114/2124 Ordering information
Type number Package
Name Description Version
LPC2114FBD64 LQFP64 plastic low profile quad flat package; 64 leads;
body 10 ×10 ×1.4 mm SOT314-2
LPC2114FBD64/00 LQFP64 plastic low profile quad flat package; 64 leads;
body 10 ×10 ×1.4 mm SOT314-2
LPC2114FBD64/01 LQFP64 plastic low profile quad flat package; 64 leads;
body 10 ×10 ×1.4 mm SOT314-2
LPC2124FBD64 LQFP64 plastic low profile quad flat package; 64 leads;
body 10 ×10 ×1.4 mm SOT314-2
LPC2124FBD64/00 LQFP64 plastic low profile quad flat package; 64 leads;
body 10 ×10 ×1.4 mm SOT314-2
LPC2124FBD64/01 LQFP64 plastic low profile quad flat package; 64 leads;
body 10 ×10 ×1.4 mm SOT314-2

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Chapter 1: Introductory information
4.3 LPC2194
4.4 LPC2210/2220
Table 5. LPC2114/2124 Ordering options
Type number Flash
memory RAM Fast GPIO/SSP/ Enhanced
UART, ADC,
Timer
Temperature range
LPC2114FBD64 128 kB 16 kB no −40 °C to +85 °C
LPC2114FBD64/00 128 kB 16 kB no −40 °C to +85 °C
LPC2114FBD64/01 128 kB 16 kB yes −40 °C to +85 °C
LPC2124FBD64 256 kB 16 kB no −40 °C to +85 °C
LPC2124FBD64/00 256 kB 16 kB no −40 °C to +85 °C
LPC2124FBD64/01 256 kB 16 kB yes −40 °C to +85 °C
Table 6. LPC2194 Ordering information
Type number Package
Name Description Version
LPC2194HBD64 LQFP64 plastic low profile quad flat package; 64 leads;
body 10 ×10 ×1.4 mm SOT314-2
LPC2194HBD64/00 LQFP64 plastic low profile quad flat package; 64 leads;
body 10 ×10 ×1.4 mm SOT314-2
LPC2194HBD64/01 LQFP64 plastic low profile quad flat package; 64 leads;
body 10 ×10 ×1.4 mm SOT314-2
Table 7. LPC2194 Ordering options
Type number Flash
memory RAM CAN Fast GPIO/ SSP/
Enhanced
UART, ADC,
Timer
Temperature range
LPC2194HBD64 256 kB 16 kB 4 channels no −40 °C to +125 °C
LPC2194HBD64/00 256 kB 16 kB 4 channels no −40 °C to +125 °C
LPC2194HBD64/01 256 kB 16 kB 4 channels yes −40 °C to +125 °C
Table 8. LPC2210/2220 Ordering information
Type number Package
Name Description Version
LPC2210FBD144 LQFP144 plastic low profile quad flat package; 144
leads; body 20 ×20 ×1.4 mm SOT486-1
LPC2210FBD144/01 LQFP144 plastic low profile quad flat package; 144
leads; body 20 ×20 ×1.4 mm SOT486-1

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Chapter 1: Introductory information
4.5 LPC2212/2214
LPC2220FBD144 LQFP144 plastic low profile quad flat package; 144
leads; body 20 ×20 ×1.4 mm SOT486-1
LPC2220FET144 TFBGA144 plastic thin fine-pitch ball grid array package;
144 balls; body 12 ×12 ×0.8 mm SOT569-1
LPC2220FET144/G TFBGA144 plastic thin fine-pitch ball grid array package;
144 balls; body 12 ×12 ×0.8 mm SOT569-1
Table 9. LPC2210/2220 Ordering options
Type number RAM Fast GPIO/
SSP/
Enhanced
UART, ADC,
Timer
Temperature range
LPC2210FBD144 16 kB no −40 °C to +85 °C
LPC2210FBD144/01 16 kB yes −40 °C to +85 °C
LPC2220FBD144 64 kB yes −40 °C to +85 °C
LPC2220FET144 64 kB yes −40 °C to +85 °C
LPC2220FET144/G 64 kB yes −40 °C to +85 °C
Table 8. LPC2210/2220 Ordering information …continued
Type number Package
Name Description Version
Table 10. LPC2212/2214 Ordering information
Type number Package
Name Description Version
LPC2212FBD144 LQFP144 plastic low profile quad flat package; 144 leads;
body 20 ×20 ×1.4 mm SOT486-1
LPC2212FBD144/00 LQFP144 plastic low profile quad flat package; 144 leads;
body 20 ×20 ×1.4 mm SOT486-1
LPC2212FBD144/01 LQFP144 plastic low profile quad flat package; 144 leads;
body 20 ×20 ×1.4 mm SOT486-1
LPC2214FBD144 LQFP144 plastic low profile quad flat package; 144 leads;
body 20 ×20 ×1.4 mm SOT486-1
LPC2214FBD144/00 LQFP144 plastic low profile quad flat package; 144 leads;
body 20 ×20 ×1.4 mm SOT486-1
LPC2214FBD144/01 LQFP144 plastic low profile quad flat package; 144 leads;
body 20 ×20 ×1.4 mm SOT486-1

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Chapter 1: Introductory information
4.6 LPC2290
4.7 LPC2292/2294
Table 11. LPC2212/2214 Ordering options
Type number Flash memory RAM Fast GPIO/
SSP/
Enhanced
UART, ADC,
Timer
Temperature range
LPC2212FBD144 128 kB 16 kB no −40 °C to +85 °C
LPC2212FBD144/00 128 kB 16 kB no −40 °C to +85 °C
LPC2212FBD144/01 128 kB 16 kB yes −40 °C to +85 °C
LPC2214FBD144 256 kB 16 kB no −40 °C to +85 °C
LPC2214FBD144/00 256 kB 16 kB no −40 °C to +85 °C
LPC2214FBD144/01 256 kB 16 kB yes −40 °C to +85 °C
Table 12. LPC2290 Ordering information
Type number Package
Name Description Version
LPC2290FBD144 LQFP144 plastic low profile quad flat package;
144 leads; body 20 ×20 ×1.4 mm SOT486-1
LPC2290FBD144/01 LQFP144 plastic low profile quad flat package;
144 leads; body 20 ×20 ×1.4 mm SOT486-1
Table 13. LPC2290 Ordering options
Type number RAM CAN Enhancements Temperature range
LPC2290FBD144 16 kB 2 channels None −40 °C to +85 °C
LPC2290FBD144/01 64 kB 2 channels Higher CPU clock, more
on-chip SRAM, Fast I/Os,
improved UARTs, added SSP,
upgraded ADC
−40 °C to +85 °C
Table 14. LPC2292/2294 Ordering information
Type number Package
Name Description Version
LPC2292FBD144 LQFP144 plastic low profile quad flat package;
144 leads; body 20 ×20 ×1.4 mm SOT486-1
LPC2292FBD144/00 LQFP144 plastic low profile quad flat package;
144 leads; body 20 ×20 ×1.4 mm SOT486-1
LPC2292FBD144/01 LQFP144 plastic low profile quad flat package;
144 leads; body 20 ×20 ×1.4 mm SOT486-1
LPC2292FET144/00 TFBGA144 plastic thin fine-pitch ball grid array package;
144 balls; body 12 ×12 ×0.8 mm SOT569-1
LPC2292FET144/01 TFBGA144 plastic thin fine-pitch ball grid array package;
144 balls; body 12 ×12 ×0.8 mm SOT569-1
LPC2292FET144/G TFBGA144 plastic thin fine-pitch ball grid array package;
144 balls; body 12 ×12 ×0.8 mm SOT569-1

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Chapter 1: Introductory information
LPC2294HBD144 LQFP144 plastic low profile quad flat package;
144 leads; body 20 ×20 ×1.4 mm SOT486-1
LPC2294HBD144/00 LQFP144 plastic low profile quad flat package;
144 leads; body 20 ×20 ×1.4 mm SOT486-1
LPC2294HBD144/01 LQFP144 plastic low profile quad flat package;
144 leads; body 20 ×20 ×1.4 mm SOT486-1
Table 15. LPC2292/2294 Ordering options
Type number Flash
memory RAM CAN Fast GPIO/ SSP/
Enhanced
UART, ADC,
Timer
Temperature range
LPC2292FBD144 256 kB 16 kB 2 channels no −40 °C to +85 °C
LPC2292FBD144/00 256 kB 16 kB 2 channels no −40 °C to +85 °C
LPC2292FBD144/01 256 kB 16 kB 2 channels yes −40 °C to +85 °C
LPC2292FET144/00 256 kB 16 kB 2 channels no −40 °C to +85 °C
LPC2292FET144/01 256 kB 16 kB 2 channels yes −40 °C to +85 °C
LPC2292FET144/G 256 kB 16 kB 2 channels no −40 °C to +85 °C
LPC2294HBD144 256 kB 16 kB 4 channels no −40 °C to +125 °C
LPC2294HBD144/00 256 kB 16 kB 4 channels no −40 °C to +125 °C
LPC2294HBD144/01 256 kB 16 kB 4 channels yes −40 °C to +125 °C
Table 14. LPC2292/2294 Ordering information …continued
Type number Package
Name Description Version

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Chapter 1: Introductory information
5. Block diagram
Grey-shaded blocks indicate configuration or pinout dependent on part and version number, see Table 1–16.
Fig 1. LPC21xx and LPC22xx block diagram
system
clock
SCL
P0[30:27], P[25:0]
P2[31:0]
P1[31:16], P1[1:0]
P3[31:0]
SDA
CS3 to CS0
A23 to A0
BLS3 to BLS0
OE, WE
D31 to D0
TRST(1)
TMS(1)
TCK(1)
TDI(1)
TDO(1)
XTAL2
XTAL1
SCK1
MOSI1
MISO1
EINT3 to EINT0
4 ×CAP0
4 ×CAP1
4 ×MAT1
4 ×MAT0
n ×AIN
PWM6 to PWM1
SSEL1
n × TD
n × RD
TXD0, TXD1
RXD0, RXD1
DSR1, CTS1,
DCD1, RI1
AMBA AHB
(Advanced High-performance Bus)
AHB BRIDGE
EMULATION
TRACE MODULE
TEST/DEBUG
INTERFACE
AHB
DECODER
AHB TO APB
BRIDGE
APB
DIVIDER
VECTORED
INTERRUPT
CONTROLLER
SYSTEM
FUNCTIONS
PLL
SPI1/SSP
SERIAL INTERFACE
I2C-BUS SERIAL
INTERFACE
UART0/UART1
CAN
WATCHDOG
TIMER
EXTERNAL
INTERRUPTS
GENERAL
PURPOSE I/O
PWM0
CAPTURE/
COMPARE
TIMER 0/TIMER 1
A/D CONVERTER
ARM7TDMI-S
LPC21xx
LPC22xx
INTERNAL
SRAM
CONTROLLER
8/16 kB
SRAM
ARM7 local bus
APB (advanced
peripheral bus)
SCK0
MOSI0
MISO0
SSEL0
SPI0
SERIAL INTERFACE
REAL-TIME CLOCK
SYSTEM CONTROL
INTERNAL
FLASH
CONTROLLER
64/128/256 kB
FLASH
RST
EXTERNAL MEMORY
CONTROLLER
P0, P1 HIGH-SPEED
GPI/O

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Chapter 1: Introductory information
6. Architectural overview
The LPC21xx/LPC22xx consist of an ARM7TDMI-S CPU with emulation support, the
ARM7 Local Bus for interface to on-chip memory controllers, the AMBA Advanced
High-performance Bus (AHB) for interface to the interrupt controller, and the ARM
Peripheral Bus (APB, a compatible superset of ARM’s AMBA Advanced Peripheral Bus)
for connection to on-chip peripheral functions. The LPC21xx/LPC22xx configures the
ARM7TDMI-S processor in little-endian byte order.
Table 16. LPC21xx/22xx part-specific configuration
Part EMC SRAM Flash Legacy
GPIO Fast GPIO SSP CAN ADC Enhanced UART Enhanced timers
channels channels/
enhanced
ADC
No-suffix and /00 parts
LPC2109 - 8 kB 64 kB P0/1 - - 1 4/- - -
LPC2119 - 16 kB 128 kB P0/1 - - 2 4/- - -
LPC2129 - 16 kB 256 kB P0/1 - - 2 4/- - -
LPC2114 - 16 kB 128 kB P0/1 - - - 4/- - -
LPC2124 - 16 kB 256 kB P0/1 - - - 4/- - -
LPC2194 - 16 kB 256 kB P0/1 - - 4 4/- - -
LPC2210 yes 16 kB - P0/1/2/3 - - - 4/- - -
LPC2220 yes 64 kB - P0/1/2/3 P0/1 yes - 8/yes yes yes
LPC2212 yes 16 kB 128 kB P0/1/2/3 - - - 8/- - -
LPC2214 yes 16 kB 256 kB P0/1/2/3 - - - 8/- - -
LPC2290 yes 16 kB - P0/1/2/3 - - 2 8/- - -
LPC2292 yes 16 kB 256 kB P0/1/2/3 - - 2 8/- - -
LPC2294 yes 16 kB 256 kB P0/1/2/3 - - 4 8/- - -
/01 parts
LPC2109 - 8 kB 64 kB P0/1 P0/1 yes 1 4/yes yes yes
LPC2119 - 16 kB 128 kB P0/1 P0/1 yes 2 4/yes yes yes
LPC2129 - 16 kB 256 kB P0/1 P0/1 yes 2 4/yes yes yes
LPC2114 - 16 kB 128 kB P0/1 P0/1 yes - 4/yes yes yes
LPC2124 - 16 kB 256 kB P0/1 P0/1 yes - 4/yes yes yes
LPC2194 - 16 kB 256 kB P0/1 P0/1 yes 4 4/yes yes yes
LPC2210 yes 16 kB - P0/1/2/3 P0/1 yes - 8/yes yes yes
LPC2212 yes 16 kB 128 kB P0/1/2/3 P0/1 yes - 8/yes yes yes
LPC2214 yes 16 kB 256 kB P0/1/2/3 P0/1 yes - 8/yes yes yes
LPC2290 yes 64 kB - P0/1/2/3 P0/1 yes 2 8/yes yes yes
LPC2292 yes 16 kB 256 kB P0/1/2/3 P0/1 yes 2 8/yes yes yes
LPC2294 yes 16 kB 256 kB P0/1/2/3 P0/1 yes 4 8/yes yes yes

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Chapter 1: Introductory information
AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the
4 gigabyte ARM memory space. Each AHB peripheral is allocated a 16 kB address space
within the AHB address space. LPC21xx/LPC22xx peripheral functions (other than the
interrupt controller) are connected to the APB bus. The AHB to APB bridge interfaces the
APB bus to the AHB bus. APB peripherals are also allocated a 2 megabyte range of
addresses, beginning at the 3.5 gigabyte address point. Each APB peripheral is allocated
a 16 kB address space within the APB address space.
The connection of on-chip peripherals to device pins is controlled by a Pin Connect Block
(see Section 8–6). This must be configured by software to fit specific application
requirements for the use of peripheral functions and pins.
7. ARM7TDMI-S processor
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
THUMB, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
•The standard 32-bit ARM instruction set.
•A 16-bit THUMB instruction set.
The THUMB set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because THUMB code
operates on the same 32-bit register set as ARM code.
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S data sheet that
can be found on official ARM website.
8. On-chip flash memory system
The LPC21xx/LPC22xx incorporate a 64 kB to 256 kB flash memory. This memory may
be used for both code and data storage. Programming of the flash memory may be
accomplished in several ways:

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Chapter 1: Introductory information
•using the serial built-in JTAG interface
•using In System Programming (ISP) and UART
•using In Application Programming (IAP) capabilities
The application program, using the IAP functions, may also erase and/or program the
flash while the application is running, allowing a great degree of flexibility for data storage
field firmware upgrades, etc. The entire flash memory is available for user code because
the boot loader resides in a separate memory location.
The LPC21xx/LPC22xx flash memory provides minimum of 100,000 erase/write cycles
and 20 years of data-retention.
9. On-chip Static RAM (SRAM)
On-chip Static RAM (SRAM) may be used for code and/or data storage. The on-chip
SRAM may be accessed as 8-bits, 16-bits, and 32-bits.
The LPC21xx/LPC22xx SRAM is designed to be accessed as a byte-addressed memory.
Word and halfword accesses to the memory ignore the alignment of the address and
access the naturally-aligned value that is addressed (so a memory access ignores
address bits 0 and 1 for word accesses, and ignores bit 0 for halfword accesses).
Therefore valid reads and writes require data accessed as halfwords to originate from
addresses with address line 0 being 0 (addresses ending with 0, 2, 4, 6, 8, A, C, and E in
hexadecimal notation) and data accessed as words to originate from addresses with
address lines 0 and 1 being 0 (addresses ending with 0, 4, 8, and C in hexadecimal
notation).
The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls
during back-to-back writes. The write-back buffer always holds the last data sent by
software to the SRAM. This data is only written to the SRAM when another write is
requested by software (the data is only written to the SRAM when software does another
write). If a chip reset occurs, actual SRAM contents will not reflect the most recent write
request (i.e. after a "warm" chip reset, the SRAM does not reflect the last write operation).
Any software that checks SRAM contents after reset must take this into account. Two
identical writes to a location guarantee that the data will be present after a Reset.
Alternatively, a dummy write operation before entering idle or power-down mode will
similarly guarantee that the last data written will be present in SRAM after a subsequent
Reset.

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User manual Rev. 03 — 2 April 2008 15 of 386
1. How to read this chapter
Remark: The LPC21xx and LPC22xx contain different memory configurations and
APB/AHB peripherals. See Table 2–17 for part-specific memory and peripherals.
For an overview of how LPC21xx and LPC22xx parts and versions are described in this
manual, see Section 1–2 “How to read this manual”.
UM10114
Chapter 2: LPC21xx/22xx Memory map
Rev. 03 — 2 April 2008 User manual
Table 17. LPC21xx and LPC22xx memory and peripheral configuration
Part EMC
Figure 2–2 SRAM Figure 2–2 Flash Figure 2–2 Fast GPIO Figure 2–2 SSP Table 2–18 CAN Table 2–18
addresses size/ addresses size/
addresses addresses APB base addresses
No suffix and /01 parts
LPC2109 - 8 kB/
0x4000 0000 -
0x4000 1FFF
64 kB/
0x0000 0000 -
0x0000 FFFF
- - 0xE003 8000 -
0xE004 0000
CAN1: 0xE004 4000
LPC2119 - 16 kB/
0x4000 0000 -
0x4000 2FFF
128 kB/
0x0000 0000 -
0x0001 FFFF
- - 0xE003 8000 -
0xE004 0000
CAN1:0xE004 4000
CAN2: 0xE004 8000
LPC2129 - 16 kB/
0x4000 0000 -
0x4000 2FFF
256 kB/
0x0000 0000 -
0x0003 FFFF
- - 0xE003 8000 -
0xE004 0000
CAN1: 0xE004 4000
CAN2: 0xE004 8000
LPC2114 - 16 kB/
0x4000 0000 -
0x4000 2FFF
128 kB/
0x0000 0000 -
0x0001 FFFF
---
LPC2124 - 16 kB/
0x4000 0000 -
0x4000 2FFF
256 kB/
0x0000 0000 -
0x0003 FFFF
---
LPC2194 - 16 kB/
0x4000 0000 -
0x4000 2FFF
256 kB/
0x0000 0000 -
0x0003 FFFF
- - 0xE003 8000 -
0xE004 0000
CAN1: 0xE004 4000
CAN2: 0xE004 8000
CAN3: 0xE004 C000
CAN4: 0xE005 0000
LPC2210 0x8000 0000 -
0x83FF FFFF 16 kB/ 0x4000 0000 -
0x4000 2FFF
-- --
LPC2220 0x8000 0000 -
0x83FF FFFF 64 kB/ 0x4001 0000 -
0x4000 FFFF
- 0x3FFF C000 -
0x3FFF FFFF 0xE005 C000 -
LPC2212 0x8000 0000 -
0x83FF FFFF 16 kB/ 0x4000 0000 -
0x4000 2FFF
128 kB/
0x0000 0000 -
0x0001 FFFF
---

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NXP Semiconductors UM10114
Chapter 2: LPC21xx/22xx Memory map
LPC2214 0x8000 0000 -
0x83FF FFFF 16 kB/ 0x4000 0000 -
0x4000 2FFF
256 kB/
0x0000 0000 -
0x0003 FFFF
---
LPC2290 0x8000 0000 -
0x83FF FFFF 16 kB/ 0x4000 0000 -
0x4000 2FFF
- - - 0xE003 8000 -
0xE004 0000
CAN1: 0xE004 4000
CAN2: 0xE004 8000
LPC2292 0x8000 0000 -
0x83FF FFFF 16 kB/ 0x4000 0000 -
0x4000 2FFF
256 kB/
0x0000 0000 -
0x0003 FFFF
- - 0xE003 8000 -
0xE004 0000
CAN1: 0xE004 4000
CAN2: 0xE004 8000
LPC2294 0x8000 0000 -
0x83FF FFFF 16 kB/ 0x4000 0000 -
0x4000 2FFF
256 kB/
0x0000 0000 -
0x0003 FFFF
- - 0xE003 8000 -
0xE004 0000
CAN1: 0xE004 4000
CAN2: 0xE004 8000
CAN3: 0xE004 C000
CAN4: 0xE005 0000
/01 parts
LPC2109 - 8 kB/
0x4000 0000 -
0x4000 1FFF
64 kB/
0x0000 0000 -
0x0000 FFFF
0x3FFF C000 -
0x3FFF FFFF 0xE005 C000 0xE003 8000 - 0xE004 0000
CAN1: 0xE004 4000
LPC2119 - 16 kB/
0x4000 0000 -
0x4000 2FFF
128 kB/
0x0000 0000 -
0x0001 FFFF
0x3FFF C000 -
0x3FFF FFFF 0xE005 C000 0xE003 8000 - 0xE004 0000
CAN1: 0xE004 4000
CAN2: 0xE004 8000
LPC2129 - 16 kB/
0x4000 0000 -
0x4000 2FFF
256 kB/
0x0000 0000 -
0x003 FFFF
0x3FFF C000 -
0x3FFF FFFF 0xE005 C000 0xE003 8000 - 0xE004 0000
CAN1: 0xE004 4000
CAN2: 0xE004 8000
LPC2114 - 16 kB/
0x4000 0000 -
0x4000 2FFF
128 kB/
0x0000 0000 -
0x0001 FFFF
0x3FFF C000 -
0x3FFF FFFF 0xE005 C000 -
LPC2124 - 16 kB/
0x4000 0000 -
0x4000 2FFF
256 kB/
0x0000 0000 -
0x003 FFFF
0x3FFF C000 -
0x3FFF FFFF 0xE005 C000 -
LPC2194 - 16 kB/
0x4000 0000 -
0x4000 2FFF
256 kB/
0x0000 0000 -
0x0003 FFFF
0x3FFF C000 -
0x3FFF FFFF 0xE005 C000 0xE003 8000 - 0xE004 0000
CAN1: 0xE004 4000
CAN2: 0xE004 8000
CAN3: 0xE004 C000
CAN4: 0xE005 0000
LPC2210 0x8000 0000 -
0x83FF FFFF 16 kB/ 0x4000 0000 -
0x4000 2FFF
- 0x3FFF C000 -
0x3FFF FFFF 0xE005 C000 -
LPC2212 0x8000 0000 -
0x83FF FFFF 16 kB/ 0x4000 0000 -
0x4000 2FFF
128 kB/
0x0000 0000 -
0x0001 FFFF
0x3FFF C000 -
0x3FFF FFFF 0xE005 C000 -
Table 17. LPC21xx and LPC22xx memory and peripheral configuration
Part EMC
Figure 2–2 SRAM Figure 2–2 Flash Figure 2–2 Fast GPIO Figure 2–2 SSP Table 2–18 CAN Table 2–18
addresses size/ addresses size/
addresses addresses APB base addresses

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Chapter 2: LPC21xx/22xx Memory map
2. Memory maps
The LPC21xx and LPC22xx incorporate several distinct memory regions, shown in the
following figures. Figure 2–2 shows the overall map of the entire address space from the
user program viewpoint following reset. The interrupt vector area supports address
remapping, which is described later in this section.
LPC2214 0x8000 0000 -
0x83FF FFFF 16 kB/ 0x4000 0000 -
0x4000 2FFF
256 kB/
0x0000 0000 -
0x0003 FFFF
0x3FFF C000 -
0x3FFF FFFF 0xE005 C000 -
LPC2290 0x8000 0000 -
0x83FF FFFF 64 kB/ 0x4001 0000 -
0x4000 FFFF
- 0x3FFF C000 -
0x3FFF FFFF 0xE005 C000 0xE003 8000 - 0xE004 0000
CAN1: 0xE004 4000
CAN2: 0xE004 8000
LPC2292 0x8000 0000 -
0x83FF FFFF 16 kB/ 0x4000 0000 -
0x4000 2FFF
256 kB/
0x0000 0000 -
0x0003 FFFF
0x3FFF C000 -
0x3FFF FFFF 0xE005 C000 0xE003 8000 - 0xE004 0000
CAN1: 0xE004 4000
CAN2: 0xE004 8000
LPC2294 0x8000 0000 -
0x83FF FFFF 16 kB/ 0x4000 0000 -
0x4000 2FFF
256 kB/
0x0000 0000 -
0x0003 FFFF
0x3FFF C000 -
0x3FFF FFFF 0xE005 C000 0xE003 8000 - 0xE004 0000
CAN1: 0xE004 4000
CAN2: 0xE004 8000
CAN3: 0xE004 C000
CAN4: 0xE005 0000
Table 17. LPC21xx and LPC22xx memory and peripheral configuration
Part EMC
Figure 2–2 SRAM Figure 2–2 Flash Figure 2–2 Fast GPIO Figure 2–2 SSP Table 2–18 CAN Table 2–18
addresses size/ addresses size/
addresses addresses APB base addresses

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NXP Semiconductors UM10114
Chapter 2: LPC21xx/22xx Memory map
Fig 2. LPC21xx and LPC22xx system memory map
AHB PERIPHERALS
APB PERIPHERALS
RESERVED ADDRESS SPACE
EXTERNAL MEMORY BANKS 0 TO 4
BOOT BLOCK (RE-MAPPED FROM
ON-CHIP FLASH MEMORY)
RESERVED ADDRESS SPACE
UP TO 64 kB ON-CHIP STATIC RAM
FAST GPIO REGISTERS
RESERVED ADDRESS SPACE
UP TO 256 kB ON-CHIP FLASH MEMORY
0xFFFF FFFF
0xF000 0000
0xEFFF FFFF
0xE000 0000
0xC000 0000
0xDFFF FFFF
0x8000 0000
0x7FFF FFFF
0x8400 0000
0x83FF FFFF
0x7FFF E000
0x7FFF DFFF
0x4001 0000
0x4000 FFFF
0x4000 0000
0x3FFF FFFF
0x3FFF C000
0x0004 0000
0x0003 FFFF
4.0 GB
3.75 GB
3.5 GB
3.0 GB
2.0 GB
1.0 GB
0.0 GB 0x0000 0000

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Chapter 2: LPC21xx/22xx Memory map
Figures 3through 4and Table 2–18 show different views of the peripheral address space.
Both the AHB and APB peripheral areas are 2 megabyte spaces which are divided up into
128 peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying the
address decoding for each peripheral. All peripheral register addresses are word aligned
AHB section is 128 x 16 kB blocks (totaling 2 MB).
APB section is 128 x 16 kB blocks (totaling 2MB).
Fig 3. Peripheral memory map
RESERVED
RESERVED
0xF000 0000
0xEFFF FFFF
APB PERIPHERALS
0xE020 0000
0xE01F FFFF
0xE000 0000
AHB PERIPHERALS
0xFFFF FFFF
0xFFE0 0000
0xFFDF FFFF
3.75 GB
3.5 GB
3.5 GB + 2 MB
4.0 GB - 2 MB
4.0 GB

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Chapter 2: LPC21xx/22xx Memory map
(to 32-bit boundaries) regardless of their size. This eliminates the need for byte lane
mapping hardware that would be required to allow byte (8-bit) or half-word (16-bit)
accesses to occur at smaller boundaries. An implication of this is that word and half-word
registers must be accessed all at once. For example, it is not possible to read or write the
upper byte of a word register separately.
Fig 4. AHB peripheral map
VECTORED INTERRUPT CONTROLLER
(AHB PERIPHERAL #0)
0xFFFF F000 (4G - 4K)
0xFFFF C000
0xFFFF 8000
(AHB PERIPHERAL #125)
(AHB PERIPHERAL #124)
(AHB PERIPHERAL #3)
(AHB PERIPHERAL #2)
(AHB PERIPHERAL #1)
(AHB PERIPHERAL #126)
0xFFFF 4000
0xFFFF 0000
0xFFE1 0000
0xFFE0 C000
0xFFE0 8000
0xFFE0 4000
0xFFE0 0000
NOT USED
NOT USED
NOT USED
EXTERNAL MEMORY CONTROLLER
NOT USED
NOT USED