Samsung LTN154X3-L01 - 15.4 WXGA Laptop LCD Screen User manual

Doc.No. ISSUED DATE Page / 13LTN154X3-L01 1
2006-06-13
Product Information
SAMSUNG TFT-LCD
MODEL NO. : LTN154X3-L01
SAMSUNG TFT-LCD
MODEL NO. : LTN154X3-L01
Product Information
LCD Product Planning Group 1, Marketing Team
Samsung Electronics Co . , LTD.

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2006-06-13
Product Information
CONTENTS
General Description
1. Electrical Absolute Ratings
2. Optical Characteristics
3. Electrical Characteristics
3.1 TFT LCD Module
3.2 Backlight Unit
4. Block Diagram
4.1 TFT LCD Module
4.2 Backlight Unit
5. Input Terminal Pin Assignment
5.1 Input Signal & Power
5.2 Backlight Unit
5.3 Timing Diagrams of LVDS For Transmitting
6. Interface Timing
6.1 Timing Parameters
6.2 Timing Diagrams of interface Signal
6.3 Power ON/OFF Sequence
7. Outline Dimension
-------------------( 3 )
-------------------( 4 )
-------------------( 5 )
-------------------( 6 )
-------------------( 7 )
-------------------( 8 )
-------------------( 10 )
-------------------( 12 )

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2006-06-13
Product Information
GENERAL DESCRIPTION
DESCRIPTION
LTN154X3-L01 is a color active matrix TFT (Thin Film Transistor) liquid crystal display
(LCD) that uses amorphous silicon TFT as switching devices. This model is composed of a
TFT LCD panel, a driver circuit and a backlight system. The resolution of a 15.4" contains
1280 x 800 pixels and can display up to 262,144 colors. 6 O'clock direction is the Optimum
viewing angle.
APPLICATIONS
• Notebook PC
• If the usage of this product is not for PC application, but for others, please contact SEC
GENERAL INFORMATION
FEATURES
• Thin and light weight
• High contrast ratio, high aperture structure
• Wide XGA (1280x800 pixels) resolution
• Fast Response Time
• Low power consumption
• Single CCFL
• DE (Data enable) only mode.
• 3.3V LVDS Interface
• On board EDID chip
• Pb-free product
Haze 0(Glare)
Haze 25(Anti-Glare), Hard-Coating 3H
Surface treatment
Normally whiteDisplay Mode
mm
0.25875(H) x 0.25875(V)
Pixel pitch
RGB vertical stripePixel arrangement
pixel
1280 x 800 ( 16 : 10, Wide XGA )Number of pixel
262,144Display colors
a-si TFT active matrixDriver element
mm
331.2(H) X 207.0(V) (15.4”diagonal)Display area
NoteUnitSpecificationItem

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2006-06-13
Product Information
1. ELECTRICAL ABSOLUTE RATINGS
MECHANICAL INFORMATION
545
6.5
222.5
344.5
Max.
g530-Weight
(1)mm6.2-Depth (D)
mm222.0221.5Vertical (V)
mm344.0343.5Horizontal (H)
Module
size
NoteUnitTyp.Min.Item
Note (1) Measurement condition of outline dimension
. Equipment : Vernier Calipers
. Push Force : 500g ⋅f (minimum)
(1) TFT LCD MODULE
(2) BACK-LIGHT UNIT
Note (1) Within Ta (25 ±2 °C)
Note 1) Permanent damage to the device may occur if maximum values are exceeded
Functional operation should be restricted to the conditions described under normal operating conditions.
Ta = 25 ±2 °C
VDD =3.3V, VSS = GND = 0V
(1)VVDD + 0.3VDD –0.3VDDPower Supply Voltage
(1)VVDD + 0.3VDD –0.3VDDLogic Input Voltage
NoteUnitMax.Min.SymbolItem
(1)kHz8050FL Lamp frequency
(1)mArms7.03.0IL
Lamp Current
NoteUnitMax.Min.SymbolItem

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2006-06-13
Product Information
2. OPTICAL CHARACTERISTICS
The following items are measured under stable conditions. The optical characteristics
should be measured in a dark room or equivalent state.
Measuring equipment : TOPCON BM-5A and PR-650
* Ta = 25 ±2 °C, VDD=3.3V, fv= 60Hz, fDCLK =68.9MHz, IL= 6.0 mA
-
Degrees
-
cd/m2
msec
-
Unit
2.2--δL
13 Points
White Variation
-3025φL
-1510φH
Ver.
-4540θH
-4540
CR ≥10
θL
Hor.
Viewing
Angle
0.3590.3290.299WY
0.3430.3130.283WX
White
0.1600.1300.100
BY
0.1850.1550.125
BX
Blue
0.5800.5500.520
GY
0.3500.3200.290
GX
Green
0.3700.3400.310
RY
0.6250.5950.565
RX
Red
Color
Chromaticity
( CIE )
-200175YL,AVE
Average Luminance
of White (5 Points)
3525-TRT
Response Time at Ta
( Rising + Falling )
--300
Normal
Viewing
Angle
φ= 0
θ= 0
CR
Contrast Ratio
(5 Points)
MaxTyp.Min.ConditionSymbolItem

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Product Information
3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
Note (1) Display data pins and timing signal pins should be connected.( GND = 0V )
(2) fV= 60Hz, fDCLK = 68.9MHZ, VDD = 3.3V , DC Current.
(3) Power dissipation pattern
Ta= 25 ±2°C
mA500410-V. Stripe
mA-340-Mosaic
mA-330-
IDD
White
Current of Power
Supply
A1.5--IRUSHRush Current
MHz70.968.966.9fDCLKMain Frequency
KHz-48.96-fHHsync Frequency
Hz-60-fvVsync Frequency
mV---100VILLow
VCM = +1.2VmV+100--VIHHigh
Differential Input
Voltage for LVDS
Receiver Threshold
V3.63.33.0VDDVoltage of Power Supply
NoteUnitMax.Typ.Min.SymbolItem
3.2 BACK-LIGHT UNIT
Ta= 25 ±2 °C
The backlight system is an edge-lighting type with a single CCFT ( Cold Cathode Fluorescent Tube ).
The characteristics of a single lamp are shown in the following table.
0°CVrms1,395
25°CVrms1,160
--VSStartup Voltage
sec1.0--Lamp startup time
Hour10,000HrOperating Life Time
IL=6.0mAW4.2PLPower Consumption
KHz656050fLFrequency
IL=6.0mAVrms-705-VLLamp Voltage
mArms6.56.03.0ILLamp Current
NoteUnitMax.Typ.Min.SymbolItem
- INVERTER : SEM SIC 130T

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Product Information
Converter
4. BLOCK DIAGRAM
4.1 TFT LCD Module
4.2 BACK-LIGHT UNIT
Note) The output of the inverter may change according to the material of the reflector.
COLD(White)
LAMP HOT (Pink)
1
2
Reflector
Input- LVDS Input/RSDS Output
Timing Controller
15.4” WXGA
TFT-LCD Panel
Source
Driver
IC
DC-DC
Control Signal
VCOM
Gamma
DVDD
AVDD
Von/Voff
Video Signal
Gamma
Generator
Connector
FI-XB30S-HF10
or Compatible
LVDS
Gate Pulse
Generator
SOURCE PCB
RSDS
EDID
EEPROM
I2 C bus
VCOM
Generator
Gate IC

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2006-06-13
Product Information
5. INPUT TERMINAL PIN ASSIGNMENT
5.1. Input Signal & Power LVDS, Connector : (JAE, FI-XB30SL-HF10 or Compatible)
Mating Connector :(JAE FI-X30M or Compatible)
PIN NO SYMBOL POLARITY REMARK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VSS
VDD
VEEDID
NC
NC
NC
RxIN0-
RxIN0+
RxIN1-
RxIN1+
RxIN2-
RxIN2+
RxCLK-
RxCLK+
Ground
DDC 3.3V Power
No Connection
FUNCTION
POWER SUPPLY +3.3V
No Connection
LVDS Differential Data INPUT (R0-R5,G0)
LVDS Differential Data INPUT (R0-R5,G0)
LVDS Differential Data INPUT (G1-G5,B0-B1)
LVDS Differential Data INPUT (G1-G5,B0-B1)
LVDS Differential Data INPUT (B2-B5,Sync,DE)
LVDS Differential Data INPUT (B2-B5,Sync,DE)
LVDS Differential Data INPUT (Clock)
LVDS Differential Data INPUT (Clock)
Negative
Positive
Negative
Positive
Negative
Positive
Negative
Positive
21
22
23
24
25
26
27
28
29
30
VDD POWER SUPPLY +3.3V
VSS Ground
VSS Ground
VSS Ground
VSS Ground
CLKEDID DDC Clock
DATAEDID DDC data
NC No Connection
NC No Connection
NC No Connection
NC No Connection
NC No Connection
NC No Connection
NC No Connection
NC No Connection
NC No Connection
No Connection

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2006-06-13
Product Information
5.2 BACK LIGHT UNIT
Connector : JST BHSR - 02VS -1
Mating Connector : SM02B-BHSS-1(JST)
5.3 Timing Diagrams of LVDS For Transmission
LVDS Receiver : Integrated T-CON
TxIN20 TxIN19 TxIN17TxIN18 TxIN16 TxIN15 TxIN14
TxIN13 TxIN12 TxIN10TxIN11 TxIN9 TxIN8 TxIN7
TxIN6 TxIN5 TxIN3TxIN4 TxIN2 TxIN1 TxIN0
T
T/7
Vsync B2Hsync B5 B3B4
G4B1 G5B0 G3 G2 G1
G0 R4 R5 R2 R1 R0
O_TxCLK OUT
0_RxCLK IN
O_RxIN1
O_RxIN0
O_RxIN2
DE
R3
Low VoltageWhiteCOLD2
High VoltagePinkHOT1
FunctionColorSymbolPin NO.

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2006-06-13
Product Information
6. INTERFACE TIMING
6.1 Timing Parameters
6.2 Timing diagrams of interface signal
-Clocks-1280-THD
Display
Period
Horizontal Active
Display Term
-Clocks155014081350THCycle
One Line
Scanning Time
-Lines-800-TVD
Display
Period
Vertical Active
Display Term
-Lines1000816804TVCycleFrame Frequency
NoteUnitMax.Typ.Min.SymbolItemSignal
TVD
TV
DE
TH
TC
THD
Valid display data ( 1280 clocks)
DCLK
DE
DATA
SIGNALS

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2006-06-13
Product Information
6.3 Power ON/OFF Sequence
: To prevent a latch-up or DC operation of the LCD module, the power on/off sequence
should be as the diagram below.
NOTE.
(1) The supply voltage of the external system for the module input should be the same
as the definition of VDD.
(2) Apply the lamp voltage within the LCD operation range. When the back-light turns on
before the LCD operation or the LCD turns off before the back-light turns off, the
display may momentarily become white.
(3) In case of VDD = off level, please keep the level of input signals on the low or keep
a high impedance.
(4) T4 should be measured after the module has been fully discharged between power
off and on period.
(5) Interface signal shall not be kept at high impedance when the power is on.
Power Supply
VDD 0.9 VDD 0.9 VDD
0V
0 V
VALID
Signals
T3
0.5 <T1 ≤10 msec
0 <T2 ≤50 msec
0 <T3 ≤50 msec
500 msec ≤T4
T1
T2T4
0.1 VDD 0.1 VDD
Power ON/OFF Sequence
Back-light
200 msec ≤T5
200 msec ≤T6
Power On Power Off
T5T6
50% 50%
T1 : Vdd rising time from 10% to 90%
T2 : The time from Vdd to valid data at power ON.
T3 : The time from valid data off to Vdd off at power Off.
T4 : Vdd off time for Windows restart
T5 : The time from valid data to B/L enable at power ON.
T6 : The time from valid data off to B/L disable at power Off.

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2006-06-13
Product Information
7. MECHANICAL OUTLINE DIMENSION
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