seeed studio Digi-Key Electronics Spartan Edge Accelerate... User manual

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SEA Board Manual
– FPGA Part

Spartan Edge Accelerate Board Development Manual--- FPGA Part
Spartan Edge Accelerate Board
Development Manual
—FPGA Part
Revision V1.0
September 15,2020
Written by:
[email protected]
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
Preview
Shenzhen Seeed Technology Co.,Ltd. in cooperation with Southeast University and Southwest Jiaotong University,
developed the Spartan Edge Accelerate Board (abbrev.SEA-Board), based on Xilinx Spartan-7 Series FPGA Chip
(xc7s15ftgb196- 1).
In order to understand the SEA development platform more quickly, we have released 3 manuals (ESP32 Part,
FPGA Part, and Comprehensive Experiment Part) that support entry-level development. Regardless of whether you
have the relevant development foundation or not, you can easily learn FPGA by studying this series of development
manuals.
Fig.1-1 Top view of the SEA development platform
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
About the Board
Spartan Edge Accelerator Board (Spartan Edge Accelerator Board, hereinafter referred to as SEA) is a Xilinx
Spartan FPGA development board with Arduino UNO interface. It can be used as an FPGA expansion board and
an independent FPGA development board together with Arduino. By carrying the ESP32 chip, SEA also has 2.4GHz
WiFi and Bluetooth 4.1 functions. Moreover, the development board integrates a rich set of peripherals and
interfaces, which is extremely playable. For example, an 8-bit ADC, a 6-axis accelerometer, two RGB LEDs, a MINI
HDMI interface, a CSI camera interface, two Grove interfaces and so on. In conclusion, it will become an ideal FPGA
entry-level development board for manufacturers and enthusiasts.
SEA is based on Xilinx Spartan-7 XC7S15 FPGA, which is a cost-effective but powerful FPGA chip.When talking
about Arduino FPGA, we always mention the first driver Arduino MKR Vidor 4000. Compared with the official Arduino
MKR Vidor 4000, the Spartan Edge Accelerator Board has similar performance, but the price is less than its half !
The Spartan Edge Accelerator Board can run at a clock speed of up to 100Mhz, and provides 12.8K logic units and
360Kb block RAM. Well, driving a camera or HDMI display is just a piece of cake. In addition to our breakthrough
XC7S15's 10 user programmable I/O pins, you can also configure them as PWM, I2C, I2S, UART, SPI, etc.
• ESP32
We know you like ESP32, so we use it as a wireless core. It supports 802.11 b / g / n 2.4GHz WiFi and Bluetooth
4.1 with BLE. Isn't it amazing that you can make your Arduino have FPGA and wireless functions with just one
board?
• Arduino FPGA API
Most importantly, even if you don't know anything about FPGA theory, we still provide a complete Arduino FPGA
API, which can help you use FPGA resources to control FPGA I/O through Arduino IDE. SEA will provide Arduino
with previously unimaginable functions, such as edge technology,image recognition,signal sampling and processing.
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
Hardware Overview
In order to more clearly grasp the characteristics of the SEA development board, we provide a detailed module
description diagram.
Fig.1-2 Module Details
⚫
High-speed image processing
➢ Support Raspberry Pi 1st Generation camera (OV5640)
➢ Support a maximum transmission rate of 30 frames
⚫
Encrypted IoT
➢ Support Cloud Service (AWS Cloud, Azure Cloud and etc)
➢ Support software encryption and decryption
⚫ Multi-channel expansion I/O
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
➢ 20-channel expansion I/O interface (FPGA independent mode)
➢ 10-channel expansion I/O interface (Arduino interface mode)
➢ Support Arduino expansion interface
⚫
Target users
➢ IoT developer
➢ Arduino developer
➢ FPGA developer
About This Document
The SEA Development Manual consists of three parts in total. This part is the second part- FPGA. This part will
focus on the three main directions of on-board FPGA resources, environment configuration and development
program.
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
Specification of safety use
⚫Please turn off the main switch of the circuit board before using the expansion interface to expand the
circuit application to avoid damage to the device.
⚫It is recommended that the circuit board should be used on an insulated platform, otherwise it may cause
damage to the circuit board.
⚫Prevent static electricity when using the circuit.
⚫Be careful when defining the positive and negative poles of the power supply and I/O port to avoid
damage to the development board due to reverse connection.
⚫Keep the surface of the circuit board clean.
⚫Handle with care to avoid unnecessary hardware damage.
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
Table of Contents
1.Development Description of FPGA ................................................................................................................................10
1.1 Introduction of on-board FPGA configuration..............................................................................................................10
1.2 Detailed description of the on-board FPGA pins.........................................................................................................11
1.3 Description of on-board FPGA interface ............................................................................................................. .17
1.3.1 LED of on-board FPGA peripheral interface.....................................................................................17
1.3.2 Mini HDMI of on-board FPGA peripheral interface ................................................................................. .18
1.3.3 MIPI camera of on-board FPGA peripheral interface.......................................................................18
1.3.4 Gyro of on-board FPGA peripheral interface .................................................................................. 19
1.3.5 ADC of on-board FPGA peripheral interface .......................................................................................... 19
1.3.6 DAC of on-board FPGA peripheral interface .......................................................................................... 20
1.3.7 Buttons of on-board FPGA peripheral interface ..................................................................................... 20
1.3.8 Arduino compatible IO interface of on-board FPGA interface ............................................................. 20
1.3.9 FPGA expansion IO interface of on-board FPGA interface ................................................................. 21
1.4 Peripheral I/O pin of on-board FPGA .................................................................................................................. 21
1.5 Arduino compatible pin of on-board FPGA ........................................................................................................ 22
1.6 IO expansion pin of on-board FPGA ................................................................................................................... 23
2.Front Installation Description of FPGA .................................................................................. .........................................24
2.1 JTAG downloader .................................................................................................................................................. 24
2.2 Additional peripherals ............................................................................................................................................... 26
2.2.1MIPI interface camera of additional peripherals ...................................................................................... 26
2.2.2Display screen of additional peripherals ..................................................................................................... 26
3. Description of FPGA Development Platform ...................................................................... .........................................27
3.1 Configuration of Vivado development environment...................................................................................27
3.1 Introduction of use for Vivado IDE ....................................................................................................................... 30
3.2.1 Introduction of start interface ....................................................................................................................... 30
3.2.2 Introduction of main interface ...................................................................................................................... 31
3.2.3 Introduction of simulation interface ............................................................................................................. 38
4.Introduction of FPGA Development Program ...................................................................... .........................................42
4.1 Verilog development ...................................................................................................................................................... 42
4.1.1 Verilog grammar module ................................................................................................................ 42
4.1.2 Execution block of Verilog grammar .............................................................................................. 42
4.1.3 Delay expression of Verilog grammar ............................................................................................ 43
4.1.4 Event expression of Verilog grammar ............................................................................................ 43
4.1.5 If conditional statement of Verilog grammar ................................................................................... 44
4.1.6 Case conditional statement of Verilog grammar ............................................................................. 44
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
4.1.7 While loop statement of Verilog grammar ...................................................................................... 45
4.1.8 For loop statement of Verilog grammar .......................................................................................... 45
4.1.9 Forever loop statement of Verilog grammar ................................................................................... 46
4.1.10 Repeat loop statement of Verilog grammar ................................................................................. 46
4.1.11 Structure description statement of Verilog grammar ................................................................... 47
4.1.12 System functions of Verilog grammar .......................................................................................... 47
4.1.13 System pre-compilation of Verilog grammar ................................................................................ 47
4.2 Constraint development ................................................................................................................................. 47
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