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– FPGA Part

Spartan Edge Accelerate Board Development Manual--- FPGA Part
Spartan Edge Accelerate Board
Development Manual
—FPGA Part
Revision V1.0
September 15,2020
Written by:
[email protected]
Contributed by:
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
Preview
Shenzhen Seeed Technology Co.,Ltd. in cooperation with Southeast University and Southwest Jiaotong University,
developed the Spartan Edge Accelerate Board (abbrev.SEA-Board), based on Xilinx Spartan-7 Series FPGA Chip
(xc7s15ftgb196- 1).
In order to understand the SEA development platform more quickly, we have released 3 manuals (ESP32 Part,
FPGA Part, and Comprehensive Experiment Part) that support entry-level development. Regardless of whether you
have the relevant development foundation or not, you can easily learn FPGA by studying this series of development
manuals.
Fig.1-1 Top view of the SEA development platform
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
About the Board
Spartan Edge Accelerator Board (Spartan Edge Accelerator Board, hereinafter referred to as SEA) is a Xilinx
Spartan FPGA development board with Arduino UNO interface. It can be used as an FPGA expansion board and
an independent FPGA development board together with Arduino. By carrying the ESP32 chip, SEA also has 2.4GHz
WiFi and Bluetooth 4.1 functions. Moreover, the development board integrates a rich set of peripherals and
interfaces, which is extremely playable. For example, an 8-bit ADC, a 6-axis accelerometer, two RGB LEDs, a MINI
HDMI interface, a CSI camera interface, two Grove interfaces and so on. In conclusion, it will become an ideal FPGA
entry-level development board for manufacturers and enthusiasts.
SEA is based on Xilinx Spartan-7 XC7S15 FPGA, which is a cost-effective but powerful FPGA chip.When talking
about Arduino FPGA, we always mention the first driver Arduino MKR Vidor 4000. Compared with the official Arduino
MKR Vidor 4000, the Spartan Edge Accelerator Board has similar performance, but the price is less than its half !
The Spartan Edge Accelerator Board can run at a clock speed of up to 100Mhz, and provides 12.8K logic units and
360Kb block RAM. Well, driving a camera or HDMI display is just a piece of cake. In addition to our breakthrough
XC7S15's 10 user programmable I/O pins, you can also configure them as PWM, I2C, I2S, UART, SPI, etc.
• ESP32
We know you like ESP32, so we use it as a wireless core. It supports 802.11 b / g / n 2.4GHz WiFi and Bluetooth
4.1 with BLE. Isn't it amazing that you can make your Arduino have FPGA and wireless functions with just one
board?
• Arduino FPGA API
Most importantly, even if you don't know anything about FPGA theory, we still provide a complete Arduino FPGA
API, which can help you use FPGA resources to control FPGA I/O through Arduino IDE. SEA will provide Arduino
with previously unimaginable functions, such as edge technology,image recognition,signal sampling and processing.
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
Hardware Overview
In order to more clearly grasp the characteristics of the SEA development board, we provide a detailed module
description diagram.
Fig.1-2 Module Details
⚫
High-speed image processing
➢ Support Raspberry Pi 1st Generation camera (OV5640)
➢ Support a maximum transmission rate of 30 frames
⚫
Encrypted IoT
➢ Support Cloud Service (AWS Cloud, Azure Cloud and etc)
➢ Support software encryption and decryption
⚫ Multi-channel expansion I/O
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
➢ 20-channel expansion I/O interface (FPGA independent mode)
➢ 10-channel expansion I/O interface (Arduino interface mode)
➢ Support Arduino expansion interface
⚫
Target users
➢ IoT developer
➢ Arduino developer
➢ FPGA developer
About This Document
The SEA Development Manual consists of three parts in total. This part is the second part- FPGA. This part will
focus on the three main directions of on-board FPGA resources, environment configuration and development
program.
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
Specification of safety use
⚫Please turn off the main switch of the circuit board before using the expansion interface to expand the
circuit application to avoid damage to the device.
⚫It is recommended that the circuit board should be used on an insulated platform, otherwise it may cause
damage to the circuit board.
⚫Prevent static electricity when using the circuit.
⚫Be careful when defining the positive and negative poles of the power supply and I/O port to avoid
damage to the development board due to reverse connection.
⚫Keep the surface of the circuit board clean.
⚫Handle with care to avoid unnecessary hardware damage.
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
Table of Contents
1.Development Description of FPGA ................................................................................................................................10
1.1 Introduction of on-board FPGA configuration..............................................................................................................10
1.2 Detailed description of the on-board FPGA pins.........................................................................................................11
1.3 Description of on-board FPGA interface ............................................................................................................. .17
1.3.1 LED of on-board FPGA peripheral interface.....................................................................................17
1.3.2 Mini HDMI of on-board FPGA peripheral interface ................................................................................. .18
1.3.3 MIPI camera of on-board FPGA peripheral interface.......................................................................18
1.3.4 Gyro of on-board FPGA peripheral interface .................................................................................. 19
1.3.5 ADC of on-board FPGA peripheral interface .......................................................................................... 19
1.3.6 DAC of on-board FPGA peripheral interface .......................................................................................... 20
1.3.7 Buttons of on-board FPGA peripheral interface ..................................................................................... 20
1.3.8 Arduino compatible IO interface of on-board FPGA interface ............................................................. 20
1.3.9 FPGA expansion IO interface of on-board FPGA interface ................................................................. 21
1.4 Peripheral I/O pin of on-board FPGA .................................................................................................................. 21
1.5 Arduino compatible pin of on-board FPGA ........................................................................................................ 22
1.6 IO expansion pin of on-board FPGA ................................................................................................................... 23
2.Front Installation Description of FPGA .................................................................................. .........................................24
2.1 JTAG downloader .................................................................................................................................................. 24
2.2 Additional peripherals ............................................................................................................................................... 26
2.2.1MIPI interface camera of additional peripherals ...................................................................................... 26
2.2.2Display screen of additional peripherals ..................................................................................................... 26
3. Description of FPGA Development Platform ...................................................................... .........................................27
3.1 Configuration of Vivado development environment...................................................................................27
3.1 Introduction of use for Vivado IDE ....................................................................................................................... 30
3.2.1 Introduction of start interface ....................................................................................................................... 30
3.2.2 Introduction of main interface ...................................................................................................................... 31
3.2.3 Introduction of simulation interface ............................................................................................................. 38
4.Introduction of FPGA Development Program ...................................................................... .........................................42
4.1 Verilog development ...................................................................................................................................................... 42
4.1.1 Verilog grammar module ................................................................................................................ 42
4.1.2 Execution block of Verilog grammar .............................................................................................. 42
4.1.3 Delay expression of Verilog grammar ............................................................................................ 43
4.1.4 Event expression of Verilog grammar ............................................................................................ 43
4.1.5 If conditional statement of Verilog grammar ................................................................................... 44
4.1.6 Case conditional statement of Verilog grammar ............................................................................. 44
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
4.1.7 While loop statement of Verilog grammar ...................................................................................... 45
4.1.8 For loop statement of Verilog grammar .......................................................................................... 45
4.1.9 Forever loop statement of Verilog grammar ................................................................................... 46
4.1.10 Repeat loop statement of Verilog grammar ................................................................................. 46
4.1.11 Structure description statement of Verilog grammar ................................................................... 47
4.1.12 System functions of Verilog grammar .......................................................................................... 47
4.1.13 System pre-compilation of Verilog grammar ................................................................................ 47
4.2 Constraint development ................................................................................................................................. 47
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
1.Development Description of FPGA
1.1 Introduction of on-board FPGA configuration
SEA on-board FPGA uses Xilinx's Spartan-7 Series xc7s15ftgb196-1, and the FPGA chip is shown in the figure
below:
Fig.1-1 xc7s15ftgb196-1
The resource configuration of chip is as follows:
⚫
12800 logic cells, 2000 slices, each containing 4 6-input LUTs and 8 flip-flops (total of 8,000
LUTs and 16,000 flip-flops)
⚫
150Kb of distributed RAM
⚫
20 DSP48E cells
⚫
10 blocks of 36Kb/20 blocks of 18Kb BRAM (total storage capacity of 360Kb)
⚫
2 clock management cells, each containing a MMCM and PLL
⚫
100 Max. user I/O number
Fig. 1-2 xc7s15 Series resource configuration
Other off-chip configurations are as follows:
⚫Equipped with universal video Mini HDMI output interface, universal camera MIPI interface, AD/DA conversion
chip, 6-axis sensor
⚫Equipped with 2 ordinary LEDs, 2 cascaded RGB LEDs, 3 programmable buttons
⚫With 10 expansion IO ports, 14 Arduino compatible ports
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
⚫Equipped with 6-wire JTAG download interface
The pin diagram is as follows:
Fig.1-3 xc7s15 Series Pin Assignment
1.2 Detailed description of the on-board FPGA pins
FPGA PIN NAME
PIN NAME OF
ACTUAL
CONNECTION
Note
A1
GND
Ground
A2
FPGA_AR_D9
Connect to output terminal AR_D9, pull down 2k by default
A3
FPGA_AR_D7
Connect to output terminal AR_D7, pull down 2k by default
A4
FPGA_AR_D6
Connect to output terminal AR_D6, pull down 2k by default
A5
FPGA_AR_D4
Connect to output terminal AR_D4, pull down 2k by default
A6
GND
Ground
A7
FPGA_TCK
JTAG ‘s TCK
A8
FPGA_CCLK
Directly connect to ESP32 pin FPGA_CCLK_ESP, programmable
A9
GND
Ground
A10
FPGA_AR_D2
Connect to output terminal AR_D2, pull down 2k by default
A11
GND
Ground
A12
FPGA_AR_D0/RX
When FPGA_AR_OE1 is at high level, connect to output terminal AR_D0/RX
A13
FPGA_LED2
Red LED
A14
GND
Ground
B1
FPGA_AR_D11
Connect to output terminal AR_D11, pull down 2k by default
B2
FPGA_AR_D10
Connect to output terminal AR_D10, pull down 2k by default
B3
FPGA_AR_D8
Connect to output terminal AR_D8, pull down 2k by default
B4
GND
Ground
B5
FPGA_AR_D5
Connect to output terminal AR_D5, pull down 2k by default
B6
FPGA_AR_D3
Connect to output terminal AR_D3, pull down 2k by default
B7
GND
Ground
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
B8
GND
Ground
B9
GND
Ground
B10
/
Pull-down ground
B11
FPGA_AR_DET
Related to VCC_3V3_AR (external power supply pin), when the external power
supply is normal, it is 3V; otherwise, it is 0v
B12
FPGA_CONFIG_DIN
Connect to the FPGA_CONFIG_DIN_ESP pin of ESP32, and reserved
programmable pin
B13
FPGA_IO3
One of 10 expansion IO ports
B14
FPGA_IO6
One of 10 expansion IO ports
C1
FPGA_HDMI_TD2-
Mini HDMI send data port DN2
C2
GND
Ground
C3
FPGA_IO10
Connect with on-board button K1, default is high level
C4
FPGA_IO2
One of 10 expansion IO ports
C5
ADC_CLK
Clock port of ADC1173 module
C6
GND
Ground
C7
GND
Ground
C8
GND
Ground
C9
GND
Ground
C10
FPGA_IO12
Connect to FPGA_CAM_DNO through a 100Ω resistor, not available
C11
ADC_D5
D5 data port of ADC1173 module
C12
FPGA_AR_D1/TX
When FPGA_AR_OE1 is at high level, connect to output terminal AR_D1/TX
C13
GND
Ground
C14
VERSION_3
If the test point is not welded, the default pull-down is 10K; when welding, it is
pulled up to 3.3V power supply
D1
FPGA_HDMI_TD2+
Mini HDMI send data port DP2
D2
FPGA_HDMI_TD1-
Mini HDMI send data port DN1
D3
FPGA_IO7
One of 10 expansion IO ports
D4
HDMI_HPD_DET
Hot plug, the host can read this port to judge whether the display is connected, if it
is high level, then connect, otherwise it is disconnected, and the HDMI signal
transmission is stopped (usually not used)
D5
GND
Ground
D6
VCC_1V
Power supply
D7
GND
Ground
D8
VCC_1V
Series 1 uF capacitor grounding
D9
GND
Ground
D10
FPGA_IO13
Connect to FPGA_CAM_DPO through a 100Ω resistor, not available
D11
GND
Ground
D12
ADC_D2
D2 data port of ADC1173 module
D13
FPGA_QSPI_HD
And ESP_ QSPI_ HD is connected by a 33 Ω resistor as a hold signal for QSPI
communication between ESP32 and FPGA
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
D14
FPGA_RST
Reset button, default high level (need to be programmed, otherwise it can be used
as ordinary key)
E1
GND
Ground
E2
FPGA_HDMI_TD1+
Mini HDMI send data port DP1
E3
GND
Ground
E4
HDMI_CEC
HDMI device control port, high level is selected by default and cannot be used
E5
VCC_1V
Series 22 uF capacitor grounding
E6
GND
Ground
E7
VCC_1V
Series 1 uF capacitor grounding
E8
GND
Ground
E9
VCC_1V
Series 1 uF capacitor grounding
E10
GND
Ground
E11
FPGA_IO9
One of 10 expansion IO ports
E12
ADC_D3
D3 data port of ADC1173 module
E13
FPGA_ESP_IO5
CS sharing flash with ESP32
E14
GND
Ground
F1
FPGA_HDMI_TD0-
Mini HDMI send data port DN0
F2
FPGA_HDMI_SDA
Through the level converter (default operation, cannot be changed), convert to 5V,
and HDMI_DDCSDA port is connected and needs 100kHz clock IIC signal for
EDID data transmission, which is not needed in general
F3
FPGA_HDMI_SCL
Through the level converter (default operation, cannot be changed), convert to 5V,
and HDMI_DDCSCL port is connected and needs 100kHz clock IIC signal for
EDID data transmission, which is not needed in general
F4
FPGA_HDMI_TCK-
Clock of HDMI transmitting DN data channel
F5
GND
Ground
F6
VCC_1V
Series 1 uF capacitor grounding
F7
GND
Ground
F8
VCC_1V8
/
F9
GND
Ground
F10
VCC_1V8
Series 22 uF capacitor grounding
F11
FPGA_CAM_CN
Clock of MIPI transmitting DN data channel
F12
ADC_D4
D4 data port of ADC1173 module
F13
FPGA_ESP_IO7
SDO sharing flash with ESP32
F14
FPGA_ESP_IO6
SCK sharing flash with ESP32
G1
FPGA_HDMI_TD0+
Mini HDMI send data port DP0
G2
VCC_3V3
Power supply
G3
GND
Ground
G4
FPGA_HDMI_TCK+
Clock of HDMI transmitting DP data channel
G5
VCC_1V
Series 22 uF capacitor grounding
G6
GND
Ground
G7
GND
Ground
G8
GND
Ground
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
G9
VCC_1V
Series 1 uF capacitor grounding
G10
GND
Ground
G11
FPGA_CAM_CP
Clock of MIPI transmitting DP data channel
G12
GND
Ground
G13
VCC_3V3
Power supply
G14
FPGA_ESP_IO8
SDI sharing flash with ESP32
H1
FPGA_AR_D12
Connect to output terminal AR_D12, pull down 20k by default
H2
FPGA_AR_D13
Connect to output terminal AR_D13, pull down 2k by default
H3
FPGA_ESP_IN1/2
As the enable of analog switch, 10K is pulled down by default,
• At low level: ESP32 ESP_ SDA_ A4 connected to FPGA_ ESP_ SDA (IIC
data line of gyroscope), ESP_ SDA_ A5 connected to FPGA_ ESP_ SCL
(IIC clock line of gyroscope) and pull up by default.
⚫
At high level: ESP_SDA_A4 与 ESP_SDA_A5 of ESP32 is connected to the
output terminal AR_A4 and AR_A5 by default (pull down by default)
H4
SYSCLK
Clock pin connected to external crystal oscillator 100MHz
H5
GND
Ground
H6
VCC_1V
Series 1 uF capacitor grounding
H7
GND
Ground
H8
GND
Ground
H9
GND
Ground
H10
VCC_1V8
Series 22 uF capacitor grounding
H11
ADC_D6
D6 data port of ADC1173
H12
ADC_D7
D7 data port of ADC1173
H13
FPGA_AR_SCK
External pin, on Arduino compatible interface 2 * 3 terminal, when FPGA_AR_OE2
is at high level, the signal will be connected to the output terminal
H14
FPGA_QSPI_CLK
And ESP_ QSPI_ CLK is connected with 33 Ω resistor as the clock for QSPI
communication between ESP32 and FPGA
J1
FPGA_LED1
Green LED
J2
ADC_D1
D1 data port of ADC1173
J3
ADC_D0
D0 data port of ADC1173
J4
ADC_EN
Enable of ADC1173 module makes low level effective
J5
VCC_1V
Series 470nF capacitor grounding
J6
GND
Ground
J7
GND
Ground
J8
GND
Ground
J9
VCC_1V
Series 1 uF capacitor grounding
J10
GND
Ground
J11
FPGA_CAM_DP0
DP0 data port output of MIPI camera
J12
FPGA_CAM_DN0
DN0 data port output of MIPI camera
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
J13
FPGA_QSPI_WP
And ESP_ QSPI_ WP is connected by 33 Ω resistor as the signal of QSPI
communication between ESP32 and FPGA
J14
IMU_AD
Gyroscope address SA0 selection, pull up by default
K1
GND
Ground
K2
VCC_3V3
Power supply
K3
FPGA_K4
K4 of the corresponding DIP switch, it is at high level when ON, and low level when
OFF
K4
FPGA_AR_RESET
External pin, on Arduino compatible interface 2 * 3 terminal, when FPGA_AR_OE2
is at high level, the signal will be connected to the output terminal
K5
GND
Ground
K6
VCC_1V
Series 1 uF capacitor grounding
K7
GND
Ground
K8
VCC_1V
Series 1 uF capacitor grounding
K9
GND
Ground
K10
VCC_1V8
Series 470nF capacitor grounding
K11
FPGA_CAM_SCL
IIC interface clock line initialized by MIPI camera
K12
FPGA_CAM_SDA
IIC interface data line initialized by MIPI camera
K13
VCC_3V3
Power supply
K14
GND
Ground
L1
DAC_DIN
Data port of DAC7311 module
L2
FPGA_K2
K2 of the corresponding DIP switch, it is at high level when ON, and low level when
OFF
L3
FPGA_K3
K3 of the corresponding DIP switch, it is at high level when ON, and low level when
OFF
L4
GND
Ground
L5
FPGA_AR_MISO
External pin, on Arduino compatible interface 2 * 3 terminal, when FPGA_AR_OE2
is at high level, the signal will be connected to the output terminal
L6
GND
Ground
L7
FPGA_PROGRAM
Directly connected with And ESP32 pin FPGA_ PROGRAM_ ESP, externally pull up
4.7K by default, and programmable
L8
GND
Ground
L9
VCC_1V8
Series 470nF capacitor grounding
L10
GND
Ground
L11
GND
Ground
L12
IMU_INT2
Gyroscope interrupt port
L13
AR_3V3_EN
Enable external power supply, and external power supply by low level
L14
FPGA_QSPI_Q
And ESP_ QSPI_ Q is connected by 33 Ω resistor as the signal of QSPI
communication between ESP32 and FPGA
M1
DAC_SCLK
Clock of DAC7311 module
M2
FPGA_K1
K1 of the corresponding DIP switch, it is at high level when ON, and low level when
OFF
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
M3
FPGA_AR_OE2
As the enabled terminal of voltage level converter, the high level is effective
(otherwise the output high level is 5V)
Input Output
FPGA_AR_SCK AR_SCK
FPGA_AR_MOSI AR_MOSI
FPGA_AR_MISO AR_MISO
FPGA_AR_RESET
AR_RESET
M4
FPGA_IO11
Connected with on-board key K2, the default is high level
M5
FPGA_AR_MOSI
External pin, on Arduino compatible interface 2 * 3 terminal, when FPGA_AR_OE2
is at high level, the signal will be connected to the output terminal
M6
FPGA_TMS
JTAG ‘s TMS
M7
FPGA_M0
Pull up 1K by default
M8
FPGA_M1
Externally connected to the DIP switch, pull up 1K by default
M9
FPGA_M2
Pull up 1K by default
M10
FPGA_IO5
One of 10 expansion IO ports
M11
FPGA_CAM_GPIO1
MIPI camera output, not available
M12
FPGA_CAM_RST
Low level reset
M13
FPGA_QSPI_CS
And ESP_ QSPI_ CS is connected with 33 Ω resistor as a chip selection signal for
QSPI communication between ESP32 and FPGA
M14
FPGA_IO1
One of 10 expansion IO ports
N1
DAC_SYNC
The enabling port of DAC311 module is effective at low level
N2
VCC_3V3
Power supply
N3
GND
Ground
N4
FPGA_AR_OE1
As the enabled terminal of voltage level converter, the high level is effective
(otherwise output high level 5V, SCL and SDA have 4.7K pull-up)
Input Output
FPGA_ESP_SDA AR_SDA
FPGA_ESP_SCL AR_SCL
FPGA_AR_D0/RX AR_D0/RX
FPGA_AR_D1/TX AR_D1/TX
N5
GND
Ground
N6
VCC_3V3
Power supply
N7
VCC_3V3
/
N8
VCC_3V3
Power supply
N9
GND
Ground
N10
FPGA_IO4
One of 10 expansion IO ports
N11
FPGA_RGB
Data line of RGB LED
N12
GND
Ground
N13
VCC_3V3
Power supply
N14
FPGA_IO0
One of 10 expansion IO ports
P1
GND
Ground
P2
FPGA_QSPI_D
And ESP_ QSPI_ D is connected by a 33 Ω resistor as the data port for QSPI
communication between ESP32 and FPGA
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
P3
VERSION_2
If the test point is not welded, the default pull-down is 10K; when welding, it is pulled
up to 3.3V power supply
P4
VERSION_1
If the test point is not welded, the default pull-down is 10K; when welding, it is pulled
up to 3.3V power supply
P5
FPGA_IO8
One of 10 expansion IO ports
P6
FPGA_TDO
JTAG ‘s TDO
P7
FPGA_TDI
JTAG ‘s TDI
P8
FPGA_INTB
Directly connect to ESP32 pin FPGA_INTB_ESP, programmable
P9
FPGA_DONE
Directly connected with ESP32 pin FPGA_ DONE_ ESP, external pull-up,
programmable
P10
FPGA_CAM_DP1
DP1 data port output of MIPI camera
P11
FPGA_CAM_DN1
DN1 data port output of MIPI camera
P12
FPGA_ESP_SCL
The IIC clock line of the gyroscope, when FPGA_AR_OE1 is at high level, the IIC
bus will be connected to the output terminal
P13
FPGA_ESP_SDA
The IIC data line of the gyroscope, when FPGA_AR_OE1 is at high level, the IIC bus
will be connected to the output terminal
P14
GND
Ground
1.3 Description of on-board FPGA interface
1.3.1 LED of on-board FPGA peripheral interface
On-board LED has two general LEDs and two RGB LEDs.
Note:
⚫ RGB LED is driven by SK6805 Series chips, which can be cascaded in multiple stages for display
development
⚫ Provide basic routines such as LED breathing light, RGB LED breathing light, LED blinking, etc.
Fig.1-4 LED and RGB LED
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
1.3.2 Mini HDMI of on-board FPGA peripheral interface
The Mini HDMI interface has the same signal interface mode except its size is smaller than HDMI interface. At
present, the specific support of on-board HDMI interface is as follows:
⚫
Support basic functions such as video output, programmable HDMI hot plug, EDID recognition, etc.
⚫
Do not support DCC multi-channel selection (selected by default)
The official case provides HDMI-driven display cases, including color bar display, checkerboard, pictures, etc.,
using Digilent's rgb2dvi interface IP (cannot transmit audio, only supports 24-bit RGB data transmission).
Fig.1-5 Mini HDMI interface
1.3.3 MIPI camera of on-board FPGA peripheral interface
Unlike other OV Series interfaces, the MIPI interface on the SEA board is 15pin, which is an industrial-grade camera
interface (the MIPI CSI interface used by mobile phones and Raspberry Pi cameras).Currently, it supports the
following:
⚫
Default IIC to initialize the MIPI camera (the initial communication method cannot be changed)
⚫
Camera access, support OV5647 camera, 720p@60Hz
The official case provides the driver of the OV5647 camera and the basic cases of image processing, including
camera image display, edge detection, HSV spatial domain transformation, color tracking, shape
recognition, etc.
Fig 1-6 MIPI interface
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Spartan Edge Accelerate Board Development Manual--- FPGA Part
1.3.4 Gyro of on-board FPGA peripheral interface
The board is equipped with a 6-axis sensor chip LSM6DS3TR, which can read posture data. The specific support
is as follows:
⚫
The Gyro is hung on the IIC bus (FPGA_ESP_SDA, FPGA_ESP_SCL), FPGA and ESP32 can read the
posture data
⚫
The Gyro supports reading of temperature, angle, angular velocity, and magnetometer
data
The official case provides the driver of LSM6DS3TR gyro, including initial configuration (setting filter parameters,
reading order, etc.), temperature, angle, angular velocity data reading and forwarding, etc.
Fig. 1-6 6-axis sensor (LSMS3TR)
1.3.5 ADC of on-board FPGA peripheral interface
The board is equipped with the ADC1173 module, which can read analog signals. The specific support is as follows:
⚫
ADC1173 is a low-power consumption, 15MSPS analog-to-digital converter, output 8-bit digital signal,
power consumption only 33mW (typical value)
⚫
The clock for analog-to-digital conversion is provided by an external clock (pin provided by
FPGA), ranging from 1MHz to 20MHz, of which the conversion effect is best at 15MHz.
Official case provides ADC1173 driver, including ADC sampling and waveform indicator
Fig.1-7 ADC input terminal
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