Segger J-Link-OB-STM32F072-128KB User manual
2
Disclaimer
Specifications written in this document are believed to be accurate, but are not guaranteed to
be entirely free of error. The information in this manual is subject to change for functional or
performance improvements without notice. Please make sure your manual is the latest edition.
While the information herein is assumed to be accurate, SEGGER Microcontroller GmbH (SEG-
GER) assumes no responsibility for any errors or omissions. SEGGER makes and you receive no
warranties or conditions, express, implied, statutory or in any communication with you. SEGGER
specifically disclaims any implied warranty of merchantability or fitness for a particular purpose.
Copyright notice
You may not extract portions of this manual or modify the PDF file in any way without the prior
written permission of SEGGER. The software described in this document is furnished under a
license and may only be used or copied in accordance with the terms of such a license.
© 2004-2017 SEGGER Microcontroller GmbH, Hilden / Germany
Trademarks
Names mentioned in this manual may be trademarks of their respective companies.
Brand and product names are trademarks or registered trademarks of their respective holders.
Contact address
SEGGER Microcontroller GmbH
In den Weiden 11
D-40721 Hilden
Germany
Tel. +49 2103-2878-0
Fax. +49 2103-2878-28
E-mail: [email protected]
Internet: www.segger.com
J-Link-OB-STM32F072-128KB-Cortex-M User Guide
(UM08029) © 2004-2017 SEGGER Microcontroller GmbH
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Manual versions
This manual describes the current version. If you find an error in the manual, please report it to
us and we will try to assist you as soon as possible.
Contact us for further information on topics that are not yet documented.
Print date: January 18, 2018
Manual
version Revision Date By Description
0.00 1 171012 NG Initial Version
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J-Link-OB-STM32F072-128KB-Cortex-M User Guide
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About this document
Assumptions
This document assumes that you already have a solid knowledge of the following:
• The software tools used for building your application (assembler, linker, C compiler).
• The C programming language.
• The target processor.
• DOS command line.
If you feel that your knowledge of C is not sufficient, we recommend The C Programming Lan-
guage by Kernighan and Richie (ISBN 0–13–1103628), which describes the standard in C pro-
gramming and, in newer editions, also covers the ANSI C standard.
How to use this manual
This manual explains all the functions and macros that the product offers. It assumes you have
a working knowledge of the C language. Knowledge of assembly programming is not required.
Typographic conventions for syntax
This manual uses the following typographic conventions:
Style Used for
Body Body text.
Keyword Text that you enter at the command prompt or that appears on
the display (that is system functions, file- or pathnames).
Parameter Parameters in API functions.
Sample Sample code in program examples.
Sample comment Comments in program examples.
Reference Reference to chapters, sections, tables and figures or other doc-
uments.
GUIElement Buttons, dialog boxes, menu names, menu commands.
Emphasis Very important sections.
J-Link-OB-STM32F072-128KB-Cortex-M User Guide
(UM08029) © 2004-2017 SEGGER Microcontroller GmbH
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J-Link-OB-STM32F072-128KB-Cortex-M User Guide
(UM08029) © 2004-2017 SEGGER Microcontroller GmbH
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Table of contents
1 Why J-Link OB? ............................................................................................................8
2 Supported target CPU cores ........................................................................................ 9
3 Supported target interfaces ........................................................................................ 10
3.1 Target interface pins .....................................................................................11
3.2 Target interface SWD ....................................................................................12
3.3 Target interface VCOM .................................................................................. 13
4 Compatible MCUs as J-Link OB host .........................................................................14
5 Schematics ..................................................................................................................15
6 Glossary ......................................................................................................................16
J-Link-OB-STM32F072-128KB-Cortex-M User Guide
(UM08029) © 2004-2017 SEGGER Microcontroller GmbH
Chapter 1
Why J-Link OB?
The J-Link on-board (J-Link OB) was designed in order to provide a low-cost, space-saving
and on-board alternative to the general J-Link, for eval board manufacturers. J-Link OB can
be used with the same software package as the general J-Links and can be used with the
same utilities (as far as the feature set of the J-Link OB supports this)
Note
It is not allowed to use J-Link-OB-STM32F072-128KB (Cortex-M) for stand-alone em-
ulators.
J-Link-OB-STM32F072-128KB-Cortex-M User Guide
(UM08029) © 2004-2017 SEGGER Microcontroller GmbH
Chapter 3
Supported target interfaces
The J-Link-OB-STM32F072-128KB (Cortex-M) supports the following target interfaces:
• SWD (+ SWO)
It may only be used with Cortex-M target CPUs.
J-Link-OB-STM32F072-128KB-Cortex-M User Guide
(UM08029) © 2004-2017 SEGGER Microcontroller GmbH
11 CHAPTER 3 Target interface pins
3.1 Target interface pins
The J-Link-OB-STM32F072-128KB (Cortex-M) provides the following target interface sig-
nals:
• #RESET (PA1 / Pin 11)
• SWCLK (PA2 / Pin 12)
• SWO (PA3 / Pin 13)
• SWDIO (PA4 / Pin 14)
• TXD (PA9 / Pin 30)
• RXD (PA10 / Pin 31)
• CTS (PA7 / Pin 17)
• RTS (PA6 / Pin 16)
Which signals are required depends on what features shall be supported on the evaluation
board. If support for a specific feature or interface is not required, the spare pins should be
left open. For more information about which target interface requires which signals, please
refer to the following sections.
J-Link-OB-STM32F072-128KB-Cortex-M User Guide
(UM08029) © 2004-2017 SEGGER Microcontroller GmbH
12 CHAPTER 3 Target interface SWD
3.2 Target interface SWD
If SWD (+ optional SWO) support is required on the target hardware to be designed, the
following signals need to be connected:
• #RESET (PA1 / Pin 11)
• SWCLK (PA2 / Pin 12)
• SWO (PA3 / Pin 13)
• SWDIO (PA4 / Pin 14)
If SWO support is not required (e.g. when the target CPU is Cortex-M0/M0+ based, which
does not provide SWO support), the SWO signal can be left open.
J-Link-OB-STM32F072-128KB-Cortex-M User Guide
(UM08029) © 2004-2017 SEGGER Microcontroller GmbH
13 CHAPTER 3 Target interface VCOM
3.3 Target interface VCOM
This J-Link OB model can support virtual COM port (VCOM) as an optional and additional
target interface. For more information about what VCOM is, please refer to J-Link VCOM
functionality .
If VCOM (+ optional hardware flow control) support is required on the target hardware to
be designed, the following signals need to be connected:
• TXD (PA9 / Pin 30)
• RXD (PA10 / Pin 31)
• CTS (PA7 / Pin 17)
• RTS (PA6 / Pin 16)
If hardware flow control support is not required, the CTS and RTS signal can be left open.
J-Link-OB-STM32F072-128KB-Cortex-M User Guide
(UM08029) © 2004-2017 SEGGER Microcontroller GmbH
Chapter 4
Compatible MCUs as J-Link OB
host
The J-Link-OB-STM32F072-128KB (Cortex-M) is based on the ST STM32 F072C 48 MHz,
128 KB flash, 16 KB RAM series MCUs. The following microcontrollers are compatible to
this J-Link OB model:
• ST STM32F072CB LQFP 48
• ST STM32F072CB UFQFPN 48
• ST STM32F072CB WLCSP 49L
• ST STM32F072RB LQFP 64
• ST STM32F072RB UFBGA 64L
• ST STM32F072VB LQFP 100
• ST STM32F072VB UFBGA 100
J-Link-OB-STM32F072-128KB-Cortex-M User Guide
(UM08029) © 2004-2017 SEGGER Microcontroller GmbH
Chapter 5
Schematics
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B B
A A
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www.segger.com
J-Link TM Technology
Title
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Date:
File:
Revision
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SWO
GND
VCC3V3
GND
VDD, VDDA decoupling
GND
VCC3V3
GND
VCC3V3
VIN
1
GND
2
CE
3
VOUT 5
nc 4
U3
XC6219B332MRN
LED_OB
LTST-C170KGKT
C3
100n C4
100n C5
100n
C2
1u
C1
100n
C7
4u7/6V3
C6
4u7/6V3
R1
10k
GND
R3 220R
R2
220R
VCC3V3
GND
#RESET_OB
SWO
GND
Target MCU
USB OB
#RESET_OB
VCC3V3
GND
J-Link OB Programming Pads
SWCLK_OB
SWDIO_OB
For programming of OB no connector is
required. Programming is performed using
the "J-Link 6 Pin Adapter" from SEGGER.
VCC 1
DN 2
DP 3
ID 4
GND 5
A
B
C
D
J1
USB_MINI_B
R WL
SWCLK_OB
SWDIO_OB
GNDGND
X1
DNP
C17
DNP
C16
DNP
R6
DNP
GND
VCC3V3 VDD, VDDA decoupling
C12
100n C13
100n C14
100n C15
100n
C11
100n
VCC3V3
SWDIO
SWCLK
SWO
#RESET
#RESET
OB MCU
Pin Header Port A
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PB0
PB1
PB2
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
VCC3V3
LED2
LTST-C170KGKT
R5
220R
LED1
LTST-C170KGKT R4
220R
LEDs
PC5
PC4
PA[15..0] PB[15..0]PC[15..0]
D_P
D_N
SWDIO
SWCLK#RESET
SWDIO
BOOT0 60
NRST 7
PH0-OSC_IN 5
PH1-OSC_OUT 6
PA0-WKUP
14
PA1
15
PA2
16
PA3
17
PA4
20
PA5
21
PA6
22
PA7
23
PA8
41
PA9
42
PA10
43
PA11
44
PA12
45
PA13
46
PA14
49
PA15
50
PB0 26
PB1 27
PB2 28
PB3 55
PB4 56
PB5 57
PB6 58
PB7 59
PB8 61
PB9 62
PB10 29
PB11 30
PB12 33
PB13 34
PB14 35
PB15 36
PC0
8
PC1
9
PC2
10
PC3
11
PC4
24
PC5
25
PC6
37
PC7
38
PC8
39
PC9
40
PC10
51
PC11
52
PC12
53
PC13
2
PC14-OSC32_IN
3
PC15-OSC32_OUT
4
PD2 54
U2A
STM32F205RCT6
VBAT
1
VDD_2
48
VDD_3
64
VDD_4
19
VDDA
13
VCAP_1 31
VCAP_2 47
VSS_3 63
VSS_4 18
VDD_1
32 VSSA 12
U2B
STM32F205RCT6
C8
2u2/4V
C9
2u2/4V PB4
GND
GND
GND
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
C
DNP
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
A
DNP
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
B
DNP
VCC3V3
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
GND
VCC3V3
GND
VCC3V3
GND
Pin Header Port BPin Header Port C
PA15
PA0 PA1
PA2 PA3
PA4 PA5
PA6 PA7
PA8 PA9
PA10 PA11
PA12 PA15
PC0 PC1
PC2 PC3
PC4 PC5
PC6 PC7
PC8 PC9
PC10 PC11
PC12 PC13
PC14 PC15
PB0 PB1
PB2 PB5
PB6 PB7
PB8 PB9
PB10 PB11
PB12 PB13
PB14 PB15
PB4
C10
4u7/6V3
U
VTref
1SWDIO 2
#RES
3SWCLK 4
GND
5SWO 6
J2
TC2030-IDC
VUSB
VUSB
*
*
*
* PC13, PC14, PC15 only provide limited drive
capability and cannot source current.
Note:
J-Link OB
SWCLK
Not Assembled
SWO
SWDIO
SWCLK
#RESET
Not Assembled
Power Supply
Application
BOOT0
44
NRST
7
PF0/OSC_IN
5
PF1/OSC_OUT
6
PA0
10
PA1
11
PA2
12
PA3
13
PA4
14
PA5
15
PA6
16
PA7
17
PA8
29
PA9
30
PA10
31
PA11
32
PA12
33
PA13/SWDIO
34
PA14/SWCLK
37
PA15
38
PB0 18
PB1 19
PB2 20
PB3 39
PB4 40
PB5 41
PB6 42
PB7 43
PB8 45
PB9 46
PB10 21
PB11 22
PB12 25
PB13 26
PB14 27
PB15 28
PC13 2
OSC32_IN/PC14 3
OSC32_OUT/PC15 4
VBAT
1
VDD_1
24
VDDIO2
36 VDD_2
48
VDDA
9
VSS_1 23
VSS_3 35
VSS_2 47
VSSA 8
EP EP
U1
STM32F072CxU6
Rev. A:
- Changed pinning for target interface
- Added Virtual COM Port
PA9
PA10
PA12
PA11
RxD
TxD
RTS
CTS
RxD
TxD
RTS
CTS
Virtual COM Port:
- Option 1: Do not connect (VCOM support not needed)
- Option 2: Connect RxD/TxD only
- Option 3: Connect all 4 signals (VCOM incl. HW flow control)
J-Link-OB-STM32F072-128KB-Cortex-M User Guide
(UM08029) © 2004-2017 SEGGER Microcontroller GmbH
Chapter 6
Glossary
This chapter describes important terms used throughout this manual.
J-Link-OB-STM32F072-128KB-Cortex-M User Guide
(UM08029) © 2004-2017 SEGGER Microcontroller GmbH
17 CHAPTER 6
Adaptive clocking
A technique in which J-Link / J-Trace sends out a clock signal and waits for the returned
clock from the target device before generating the next clock pulse. The technique allows
the J-Link / J-Trace interface unit to adapt to different signal drive capabilities, different
cable lengths and variable target clock speeds. Adaptive clocking can be used when it is
supported by the connected target device.
RESET
Abbreviation of System Reset. The electronic signal which causes the target system other
than the TAP controller to be reset. This signal is also known as “nSRST” “nSYSRST”, “nRST”,
or “nRESET” in some other manuals. See also nTRST.
nTRST
Abbreviation of TAP Reset. The electronic signal that causes the target system TAP controller
to be reset. This signal is known as nICERST in some other manuals. See also nSRST.
RTCK
Returned TCK. The signal which allows Adaptive Clocking.
TCK
The electronic clock signal which times data on the TAP data lines TMS, TDI, and TDO.
TDI
The electronic signal input to a TAP controller from the data source (upstream). Usually,
the TDI signal of J-Link is connected to the TDI of the first TAP controller in a JTAG chain.
TDO
The electronic signal output from a TAP controller to the data sink (downstream). Usually,
the TDO signal of J-Link is connected to the TDO of the last TAP controller in a JTAG chain.
TMS
The electronic signal Test Mode Select is an input to the TAP controller and it is used to
select different stages of state machine. It is clocked in into the TAP controller using the
TCK signal.(upstream). Usually, the TMS output signal of J-Link is connected to the TMS
input of the first TAP controller in a JTAG chain. For Cortex-M CPUs this signal may also
be used as the bidirectional data signal SWDIO when the CPU is accessed in serial wire
debug mode SWD.
SWD
A serial communication protocol for Cortex M CPUs which may used for communication with
a debug device as an alternative communication channel to JTAG. The SWD communication
uses less pins.
SWDIO
The bidirectional electronic signal for communication of a Cortex M CPU accessed in serial
wire debug mode. Normally, the TMS input pin of the Cortex M CPU is used as SWDIO pin
in serial wire mode.
SWCLK
The electronic signal which times data on the SWDIO data line used in serial wire debug
mode. The SWCLK pin is typically the TCK pin used as JTAG clock input, when JTAG is also
supported by the device.
J-Link-OB-STM32F072-128KB-Cortex-M User Guide
(UM08029) © 2004-2017 SEGGER Microcontroller GmbH
18 CHAPTER 6
SWO
The electronic asynchronous signal for trace data output or SWV output data which may
be sent by the application on a Cortex-M CPU running in serial wire debug mode. J-Link-
OB-STM32F072-128KB (Cortex-M) is able to receive the data in asynchronous mode when
SWO of the target CPU is connected to the SWOin signal of J-Link-OB-STM32F072-128KB
(Cortex-M). Normally the SWO output signal of a Cortex-M CPU is directed via the TDO
signal pin, but may be separated on some devices.
J-Link-OB-STM32F072-128KB-Cortex-M User Guide
(UM08029) © 2004-2017 SEGGER Microcontroller GmbH
Table of contents
